Patent Application
20240332296
The present disclosure generally relates semiconductor fabrication methods and resulting structures, and more specifically, to fabrication methods and resulting forksheet semiconductor devices.
In contemporary semiconductor device fabrication processes, a large number of semiconductor devices, such as n-type field effect transistors (nFETs) and p-type field effect transistors (pFETs), are fabricated on a single wafer. Non-planar transistor device architectures (e.g., fin-type FETs (FinFETs) and nanosheet FETs) can provide increased device density and increased performance over planar transistors. FinFETs are non-planar, three-dimensional (3D) devices that include a fin-shaped element that defines the source, drain, and channel regions of the FinFET. A gate stack is formed over and around a central region of the fin-shaped element, and the portion of the fin that is under the gate stack functions as the FinFET channel. The portions of the fin-shaped element that are not under the gate stack function as the source region and the drain region, respectively. Nanosheet transistors are similar to FinFETs except the channel portion of the fin is formed as multiple spaced-apart channel nanosheets, and the gate stack wraps around the full perimeter of each nanosheet channel region for improved control of channel current flow. Nanosheet transistors enable full depletion in the nanosheet channel regions and reduce short-channel effects.
According to an embodiment of the present disclosure, a semiconductor device includes a vertical insulator pillar extending from a substrate. A first stack of horizontal sheets of a first channel device is coupled to a lateral first side of the vertical insulator pillar. A second stack of horizontal sheets of a second channel device is coupled to a lateral second side of the vertical insulator pillar, opposite the first stack of horizontal sheets. A first gate stack is wrapped around the first stack of horizontal sheets. A second gate stack is wrapped around the second stack of horizontal sheets. A first gate extension is coupled to a center portion of the first gate stack and extending laterally away from the second gate stack. A second gate extension is coupled to a center portion of the second gate stack and extending laterally away from the first gate stack.
In one embodiment, a first gate contact extends from a top of the semiconductor device to the first gate extension, and a second gate contact extending from the top of the semiconductor device to the second gate extension.
In one embodiment, at least a portion of the vertical insulator pillar is embedded in the substrate.
In one embodiment, a third extension is on a top portion of the first gate stack abutting the vertical insulator pillar, and a fourth extension on a top portion of the second gate stack abutting the vertical insulator pillar.
In one embodiment, a common gate contact is coupled to a top portion of the third extension of the gate stack, a top portion of the fourth extension of the gate stack, and a top of the vertical insulator pillar.
In one embodiment, a first gate cut region is adjacent the first gate stack and extending from a top of the semiconductor device to a first shallow trench isolation (STI) on top of the substrate. A second gate cut region is adjacent the second gate stack and extending from the top of the semiconductor device to a second shallow trench isolation (STI) on top of the substrate.
In one embodiment, the first stack and the second stack of horizontal sheets each are of a Silicon Germanium (SiGe) nanosheet stack.
In one embodiment, a lateral side width of the first gate stack overlapping from the first stack of horizontal sheets is substantially similar to a gap between each of the sheets of the first stack of horizontal sheets. A lateral side width of the second gate stack overlapping from the second stack of horizontal sheets is substantially similar to a gap between each of the sheets of the second stack of horizontal sheets.
In one embodiment, a shallow trench isolation (STI) extends from the substrate to a middle portion of the first gate stack and the second gate stack.
In one embodiment, the semiconductor device is a forksheet device. The first channel device is a p-channel field effect transistor (pFET). The second channel device is an n-channel field effect transistor (nFET).
In one embodiment, a width of the vertical insulator pillar is below 10 nm.
In one embodiment, the first gate stack is not directly coupled to the second gate stack and is separated by the vertical insulator pillar.
According to one embodiment, method of manufacturing a semiconductor includes providing a first stack of horizontal sheets of a first transistor device and a second stack of horizontal sheets of a second transistor device, coupled to opposite sides of a vertical insulator pillar. For each of the first and second stack of horizontal sheets, a raised shallow trench isolation (STI) is provided on a lateral first side, opposite the vertical insulator pillar. A sacrificial gate is formed that wraps around channels of the nanosheet stack. A sacrificial gate liner of the sacrificial gate is removed from a top portion of the vertical insulator pillar. A gate trench opening is formed to access the sacrificial gate. A replacement gate stack is formed wrapped around the horizontal sheets. A gate extension is formed above the raised STI.
In one embodiment, the first transistor is a p-channel field effect transistor (pFET), the second transistor is an n-channel field effect transistor (nFET), and the first stack and the second stack of horizontal sheets each are made of a Silicon Germanium (SiGe) nanosheet stack.
In one embodiment, sacrificial gate liner from the top portion of the vertical insulator pillar is removed by chamfering.
In one embodiment, a first gate contact is provided between a top surface of the semiconductor device and the gate extension of the first nanosheet stack. A second gate contact is provided between the top surface of the semiconductor device and the gate extension of the second nanosheet stack.
In one embodiment, at least a portion of the vertical insulator pillar is embedded in the substrate.
In one embodiment, for each of the first and second stack of horizontal sheets, an additional extension is provided on a top portion of the replacement gate stack, abutting the vertical insulator pillar.
In one embodiment, a common gate contact is formed coupled to a top portion of each gate stack and a top of the vertical insulator pillar.
According to one embodiment, a forksheet device includes a vertical insulator pillar. A first stack of horizontal sheets of a p-channel field effect transistor (pFET) is coupled to a lateral first side of the vertical insulator pillar.
A second stack of horizontal sheets of a n-channel field effect transistor (nFET) is coupled to a lateral second side of the vertical insulator pillar, opposite the first stack of horizontal sheets. A first gate stack is wrapped around the first stack of horizontal sheets. A second gate stack is wrapped around the second stack of horizontal sheets. A first gate extension is coupled to a center portion of the first gate stack and extending laterally away from the second gate stack. A second gate extension is coupled to a center portion of the second gate stack and extending laterally away from the first gate stack.
These and other features will become apparent from the following detailed description of illustrative embodiments thereof, which is to be read in connection with the accompanying drawings.
The drawings are of illustrative embodiments. They do not illustrate all embodiments. Other embodiments may be used in addition or instead. Details that may be apparent or unnecessary may be omitted to save space or for more effective illustration. Some embodiments may be practiced with additional components or steps and/or without all of the components or steps that are illustrated. When the same numeral appears in different drawings, it refers to the same or like components or steps.
In the following detailed description, numerous specific details are set forth by way of examples in order to provide a thorough understanding of the relevant teachings. However, it should be apparent that the present teachings may be practiced without such details. In other instances, well-known methods, procedures, components, and/or circuitry have been described at a relatively high-level, without detail, in order to avoid unnecessarily obscuring aspects of the present teachings.
In one aspect, spatially related terminology such as “front,” “back,” “top,” “bottom,” “beneath,” “below,” “lower,” above,” “upper,” “side,” “left,” “right,” and the like, is used with reference to the direction of the Figures being described. Since components of embodiments of the disclosure can be positioned in a number of different directions, the directional terminology is used for purposes of illustration and is in no way limiting. Thus, it will be understood that the spatially relative terminology is intended to encompass different directions of the device in use or operation in addition to the direction depicted in the figures. For example, if the device in the figures is turned over, elements described as “below” or “beneath” other elements or features would then be oriented “above” the other elements or features. Thus, for example, the term “below” can encompass both an orientation that is above, as well as, below. Similarly, an element described as “on top of” of another element may mean either that the element is positioned above and is not necessarily in direct contact with the underlying element. The device may be otherwise oriented (rotated 90 degrees or viewed or referenced at other directions) and the spatially relative descriptors used herein should be interpreted accordingly.
As used herein, the terms “lateral”, “planar”, and “horizontal” describe an orientation parallel to a first surface of a chip or substrate. In the disclosure herein, the “first surface” may be the top layer of a semiconductor device where individual circuit devices are patterned in the semiconductor material.
As used herein, the term “vertical” describes an orientation that is arranged perpendicular to the first surface of a chip, chip carrier, chip substrate, or semiconductor body.
As used herein, the terms “coupled” and/or “electrically coupled” are not meant to mean that the elements must be directly coupled together-intervening elements may be provided between the “coupled” or “electrically coupled” elements. In contrast, if an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present. The term “electrically connected” refers to a low-ohmic electric connection between the elements electrically connected together. The phrase “electrically connected” does not necessarily mean that the elements must be directly in physical contact together-intervening elements may be provided between the “connected” or “electrically connected” elements.
Although the terms first, second, etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of example embodiments. Nor does describing an element as “first” or “second,” etc., necessarily mean that there is an order or priority to any of the elements. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.
Example embodiments are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized or simplified embodiments (and intermediate structures). As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, may be expected. Thus, the regions illustrated in the figures are schematic in nature and their shapes do not necessarily illustrate the actual shape of a region of a device and do not limit the scope. It should be appreciated that the figures and/or drawings accompanying this disclosure are exemplary, non-limiting, and not necessarily drawn to scale.
It is to be understood that other embodiments may be used, and structural or logical changes may be made without departing from the spirit and scope defined by the claims. The description of the embodiments is not limiting. In particular, elements of the embodiments described hereinafter may be combined with elements of different embodiments.
For the sake of brevity, conventional techniques related to semiconductor device and integrated circuit (IC) fabrication may or may not be described in detail herein. Moreover, the various tasks and process steps described herein can be incorporated into a more comprehensive procedure or process having additional steps or functionality not described in detail herein. In particular, various steps in the manufacture of semiconductor devices and semiconductor-based ICs are well known and so, in the interest of brevity, many conventional steps will only be mentioned briefly herein or will be omitted entirely without providing the well-known process details.
Turning now to a description of technologies that are more specifically relevant to the present disclosure, transistors are semiconductor devices commonly found in a wide variety of ICs. A transistor is essentially a switch. When a voltage is applied to a gate of the transistor that is greater than a threshold voltage, the switch is turned ON, and current flows through the transistor. When the voltage at the gate is less than the threshold voltage, the switch is OFF, and current does not flow through the transistor.
Typical semiconductor devices are formed using active regions of a wafer. The active regions are defined by isolation regions used to separate and electrically isolate adjacent semiconductor devices. For example, in an IC having a plurality of metal oxide semiconductor field effect transistors (MOSFETs), each MOSFET has a source and a drain that are formed in an active region of a semiconductor layer by implanting n-type or p-type impurities in the layer of semiconductor material. Disposed between the source and the drain is a channel (or body) region. Disposed above the body region is a gate electrode. The gate electrode and the body are spaced apart by a gate dielectric layer.
MOSFET-based ICs are fabricated using so-called complementary metal oxide semiconductor (CMOS) fabrication technologies. In general, CMOS is a technology that uses complementary and symmetrical pairs of p-type and n-type MOSFETs to implement logic functions. The channel region connects the source and the drain, and electrical current flows through the channel region from the source to the drain. The electrical current flow is induced in the channel region by a voltage applied at the gate electrode.
The wafer footprint of an FET is related to the electrical conductivity of the channel material. If the channel material has a relatively high conductivity, the FET can be made with a correspondingly smaller wafer footprint. A known method of increasing channel conductivity and decreasing FET size is to form the FET as a non-planar FinFET architecture, wherein the channel of the FinFET is implemented as a fin-shaped structure, and wherein a gate stack is wrapped around sidewalls and a top surface of a central region of the fin-shaped structure. The portion of the fin-shaped structure that is under the gate stack functions as the channel, and the portions of the fin-shaped structure that are not under the gate stack are doped to function as the source region and the drain region, respectively. In some implementations, the fin-shaped structure is Si, and the S/D regions of the fin are formed as doped SiGe. The use of doped SiGe to form the S/D regions provides desirable device characteristics, including the introduction of strain at the various interfaces between SiGe and Si in the transistor.
Another approach in increasing channel conductivity and decreasing FET size is to form the channel as a nanosheet structure. For example, a gate-all-around (GAA) nanosheet FET is a known architecture for providing a relatively small FET footprint by forming the channel region as a series of nanosheets. In a known GAA configuration, a nanosheet-based FET includes a source region, a drain region and stacked nanosheet channels between the source and drain regions. A gate surrounds the stacked nanosheet channels and regulates electron flow through the nanosheet channels between the source and drain regions. GAA nanosheet FETs are fabricated by forming alternating layers of channel nanosheets and sacrificial layers. The sacrificial layers are released from the channel nanosheets before the FET device is finalized. For n-type FETs, the channel nanosheets are typically Si and the sacrificial layers are typically SiGe. For p-type FETs, the channel nanosheets can be SiGe and the sacrificial layers can be Si. In some implementations, the channel nanosheet of a p-type FET can be SiGe or Si, and the sacrificial layers can be Si or SiGe. Similar to FinFET architectures, the S/D regions of a GAA nanosheet architecture can be formed from doped SiGe. Forming the S/D regions from SiGe, and the use of multiple layered SiGe/Si sacrificial/channel nanosheets (or Si/SiGe sacrificial/channel nanosheets) provide desirable device characteristics, including the introduction of strain at the interface between SiGe and Si, as mentioned above.
As semiconductor devices continue to decrease in size, it has become desirable to provide distances between the nFET and pFET fins, sometimes referred to as the “N2P space.” Providing N2P spaces at small dimensions, particularly at below 10 nm, can present challenges to communicating with the pFET section and the nFET section. Specifically, N2P spaces on this order reduce the process window within which contact structures connecting the nFET section and pFET section do not electrically short with one another. N2P spaces on this order also reduce the process window within which the resistance and capacitance (R/C) electrical characteristics, sometimes referred to as parasitic components of the semiconductor device, are acceptable. While the process window can be broadened by positioning the contact structure at locations laterally offset from the N2P space, such positioning increases the electrical resistance between the contact structures and the respective pFET section and nFET section, offsetting the improvement in process window and/or electrical characteristics of the multilayer integrated circuit (IC) device.
Reference now is made to
More recently, the trend to continue reducing the footprint of FET devices has led to the development of forked nanosheet semiconductor devices, also referred to as “forksheet devices.” In this regard, reference is made to
The forksheet device 100B implements nanosheets that are controlled by a tri-gate forked structure. The tri-gate forked structure is realized by forming a dielectric wall 106 (sometimes referred to herein as a vertical insulator) between the P- and NMOS devices. The dielectric wall physically isolates the p-gate trench from the n-gate trench, allowing much tighter N2P spacing that facilitates superior area and performance scalability compared to traditional nanosheet devices (e.g., 100A). To achieve an adequate effective channel width for the forksheet device at aggressively scaled cell height, Applicants recognize that the number of stack should be increased as compared to nanosheet technology. However, increasing the stack height increases the parasitic capacitance, as the gate heigh increases.
In one aspect, the teachings herein provide an advanced transistor implemented as a forksheet device with substantially reduced parasitic capacitance and methods of creation thereof. The techniques described herein may be implemented in a number of ways. Example implementations are provided below with reference to the following figures.
With the foregoing overview of the considerations related to forksheet devices, it may be helpful to describe an example process of creating a forksheet device. The discussion below provides an example process of manufacturing a forksheet device having a particular gate extension for reduced parasitic capacitance.
The semiconductor device 200 includes a n-type field effect transistor (nFET) section 202, an p-type field effect transistor (pFET) section 204 (sometimes collectively referred to as an active region), an insulator pillar 206, and gate structures 208. The pFET section 204 is arranged on a side to the semiconductor device 200 laterally opposite the nFET section 202. The insulator pillar 206 (sometimes referred to herein as a vertical insulator pillar) is arranged laterally between the pFET section 204 and the nFET section 202 and extends longitudinally along the semiconductor device 200 between the pFET section 204 and the nFET section 202, as will be illustrated more clearly in subsequent drawings. The gate structures 208 (e.g., a gate electrodes) span the insulator pillar 206, wrap around the pFET section 204 and the nFET section 202 of the semiconductor device, and are longitudinally spaced from one another along the semiconductor device 200.
As mentioned previously, the term ‘nanosheet,’ as used herein, refers to a sheet or a layer having nanoscale dimensions. Further, the term ‘nanosheet’ is meant to encompass other nanoscale structures such as nanowires. For instance, ‘nanosheet’ can refer to a nanowire with a larger width, and/or ‘nanowire’ can refer to a nanosheet with a smaller width, and vice versa. The structure depicted in
The nanosheet stack includes alternating layers of a second nanosheet material 306 and third nanosheet material, 308, as well as a first nanosheet material 304, which may be selectively removed later (e.g., sacrificial). For instance, according to an example embodiment, the first nanosheet material 304 is SiGe60 (i.e., Silicon-Germanium having 60 Germanium), the second nanosheet material 306 may be SiGe30 (i.e., Silicon-Germanium having 30% Germanium), and the third nanosheet material 308 may be Si. However, this is merely an example and other configurations and concentrations are contemplated herein. As will be described in detail below, these nanosheet materials will be used to form the channels of the present stacked nanosheet devices and a sacrificial material in between the channels. Removal of the sacrificial material releases the channels from the stack and permits gates to be formed that fully surround (e.g., wrap around) the channels in a gate-all-around configuration. Thus, it is preferable that the first, second, and third nanosheet materials have etch selectivity with respect to one another. Thus, when one serves as the channels, the other sacrificial material can be selectively removed to release the channels from the nanosheet stack. By way of example only and not by way of limitation, Si, SiGe30, and SiGe60 provide such etch selectivity. By ‘sacrificial’ it is meant that the layer, or portion thereof, is removed during fabrication of the device. By way of example only and not by way of limitation, each of the nanosheets 304, 306 and 308 in the nanosheet stack are deposited onto the substrate 302, one on top of the other, using an epitaxial growth process. According to an example embodiment, the first second and third nanosheets 304, 306, and 308 may have a thickness range from about 6 nm to 25 nm.
According to an example embodiment, sacrificial nanosheets 304 and 306 are formed from SiGe having a high germanium (Ge) content. For example, in one exemplary embodiment, a high Ge content is from about 50% Ge to about 100% Ge (i.e., pure Ge) and ranges therebetween. For instance, in one non-limiting example, one of sacrificial nanosheets (e.g., 304) is formed from SiGe60 (which has a Ge content of about 60%). Use of a higher Ge content SiGe will enable the sacrificial nanosheet 304 to be etched selective to the sacrificial nanosheet 306 in the nanosheet stack. Notably, however, the SiGe used as for the other sacrificial nanosheet material has a low Ge content. For example, in one exemplary embodiment, a low Ge content is from about 15% Ge to about 50% Ge and ranges therebetween.
Additionally,
In some embodiments, the sacrificial gate liner 812 is conformally deposited over the nanosheet stack. The sacrificial gate liner 812 may have a thickness greater than the sacrificial layers 110, for example, of about 8 nm to about 20 nm, although other thicknesses are within the contemplated scope of the disclosure.
In some embodiments, the sacrificial gate liner 812 is formed using chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), ultrahigh vacuum chemical vapor deposition (UHVCVD), rapid thermal chemical vapor deposition (RTCVD), metalorganic chemical vapor deposition (MOCVD), low-pressure chemical vapor deposition (LPCVD), limited reaction processing CVD (LRPCVD), atomic layer deposition (ALD), physical vapor deposition (PVD), chemical solution deposition, molecular beam epitaxy (MBE), or other like process in combination with a wet or dry etch process. The sacrificial gate liner 812 can be made of any suitable sacrificial material, such as silicon germanium (SiGe), although other sacrificial materials are within the contemplated scope of the disclosure. The sacrificial gate liner 812 may be provided as a blanket on the entire device (not shown), a second sacrificial material is deposited that leaves out a top portion of the vertical insulator pillar 412 and the sacrificial liner thereon. Deep chamfering (e.g., by way of dry etch or wet etch) can be used to remove the sacrificial gate liner 812 from the top portion of the vertical insulator pillar 412, thereby separating the left side (e.g., pFET) and the right side (e.g., nFET) of the device, as illustrated in
In some embodiments, the source and drain regions 1002 and 1004 are formed on exposed sidewalls of the third nanosheet material (e.g., nanosheet layer) 308, abuts the vertical insulator pillar 412. The source and drain regions 1002 and 1004 can be epitaxially grown using, for example, vapor-phase epitaxy (VPE), molecular beam epitaxy (MBE), liquid-phase epitaxy (LPE), or other suitable processes. For example, the source and drain regions 1002 and 1004 can be semiconductor materials epitaxially grown from gaseous or liquid precursors.
In the example of
In the embodiment of
In one embodiment, a lateral side width of the first gate stack 1610 overlapping from the first stack of horizontal sheets is substantially similar to a gap between each of the sheets of the first stack of horizontal sheets. A lateral side width of the second gate stack overlapping from the second stack 1620 of horizontal sheets is also substantially similar to a gap between each of the sheets of the second stack of horizontal sheets (nFET).
It is noted that there is a shallow trench isolation (STI) 710 extending from the substrate to a middle portion of the first gate stack 1610 and the second gate stack 1620. In this way, a gate contact (e.g., 1604) that is not excessively deep can be facilitated, thereby simplifying processing complexity, as well as allowing the gate to be controlled in a more resistively uniform way, as explained above.
By way of contrast,
As is illustrated in the resulting structures depicted in
The following acts are performed for each of the first and second stack of horizontal sheets. At block 1804, a raised shallow trench isolation (STI) on a lateral first side, opposite the vertical insulator pillar is provided. At block, 1806, a sacrificial gate that wraps around channels of the nanosheet stack is formed. At block a sacrificial gate liner of the sacrificial gate from a top portion of the vertical insulator pillar, is removed.
At block 1812 a gate trench opening is formed to access the sacrificial gate. At block 1814, a replacement gate stack wrapped around the horizontal sheets is formed. At block 1816, a gate extension above the raised STI.
In one aspect, the method and structures as described above may be used in the fabrication of integrated circuit chips. The resulting integrated circuit chips can be distributed by the fabricator in raw wafer form (that is, as a single wafer that has multiple unpackaged chips), as a bare die, or in a packaged form. In the latter case, the chip may be mounted in a single chip package (such as a plastic carrier, with leads that are affixed to a motherboard or other higher-level carrier) or in a multichip package (such as a ceramic carrier that has either or both surface interconnections or buried interconnections). In any case, the chip can then be integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either (a) an intermediate product, such as a motherboard, or (b) an end product. The end product can be any product that includes integrated circuit chips, ranging from low-end applications, such as toys, to advanced computer products having a display, a keyboard or other input device, and a central processor.
The descriptions of the various embodiments of the present teachings have been presented for purposes of illustration, but are not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.
While the foregoing has described what are considered to be the best state and/or other examples, it is understood that various modifications may be made therein and that the subject matter disclosed herein may be implemented in various forms and examples, and that the teachings may be applied in numerous applications, only some of which have been described herein. It is intended by the following claims to claim any and all applications, modifications and variations that fall within the true scope of the present teachings.
The components, steps, features, objects, benefits and advantages that have been discussed herein are merely illustrative. None of them, nor the discussions relating to them, are intended to limit the scope of protection. While various advantages have been discussed herein, it will be understood that not all embodiments necessarily include all advantages. Unless otherwise stated, all measurements, values, ratings, positions, magnitudes, sizes, and other specifications that are set forth in this specification, including in the claims that follow, are approximate, not exact. They are intended to have a reasonable range that is consistent with the functions to which they relate and with what is customary in the art to which they pertain.
Numerous other embodiments are also contemplated. These include embodiments that have fewer, additional, and/or different components, steps, features, objects, benefits, and advantages. These also include embodiments in which the components and/or steps are arranged and/or ordered differently.
While the foregoing has been described in conjunction with exemplary embodiments, it is understood that the term “exemplary” is merely meant as an example, rather than the best or optimal. Except as stated immediately above, nothing that has been stated or illustrated is intended or should be interpreted to cause a dedication of any component, step, feature, object, benefit, advantage, or equivalent to the public, regardless of whether it is or is not recited in the claims.
It will be understood that the terms and expressions used herein have the ordinary meaning as is accorded to such terms and expressions with respect to their corresponding respective areas of inquiry and study except where specific meanings have otherwise been set forth herein. Relational terms such as first and second and the like may be used solely to distinguish one entity or action from another without necessarily requiring or implying any actual such relationship or order between such entities or actions. The terms “comprises,” “comprising,” or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. An element proceeded by “a” or “an” does not, without further constraints, preclude the existence of additional identical elements in the process, method, article, or apparatus that comprises the element.
The Abstract of the Disclosure is provided to allow the reader to quickly ascertain the nature of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. In addition, in the foregoing Detailed Description, it can be seen that various features are grouped together in various embodiments for the purpose of streamlining the disclosure. This method of disclosure is not to be interpreted as reflecting an intention that the claimed embodiments have more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive subject matter lies in less than all features of a single disclosed embodiment. Thus, the following claims are hereby incorporated into the Detailed Description, with each claim standing on its own as a separately claimed subject matter.
