Patent Application
20080280426
1. Field of the Invention
This invention generally relates to integrated circuit (IC) fabrication and, more particularly to a gallium nitride-on-silicon interface and associated fabrication process.
2. Description of the Related Art
Gallium nitride (GaN) is a Group III/Group V compound semiconductor material with wide bandgap (3.4 eV), which has optoelectronic, as well as other applications. Like other Group III nitrides, GaN has a low sensitivity to ionizing radiation, and so, is useful in solar cells. GaN is also useful in the fabrication of blue light-emitting diodes (LEDs) and lasers. Unlike previous indirect bandgap devices (e.g., silicon carbide), GaN LEDs are bright enough for daylight applications. GaN devices also have application in high power and high frequency devices, such as power amplifiers.
GaN LEDs are conventionally fabricated using a metalorganic chemical vapor deposition (MOCVD) for deposition on a sapphire substrate. Zinc oxide and silicon carbide (SiC) substrate are also used due to their relatively small lattice constant mismatch. However, these substrates are expensive to make, and their small size also drives fabrication costs. For example, the state-of-the-art sapphire wafer size is relatively small when compared to silicon wafers. The most commonly used substrate for GaN-based devices is sapphire. The low thermal and electrical conductivity constraints associated with sapphire make device fabrication more difficult. For example, all contacts must be made from the top side. This contact configuration complicates contact and package schemes, resulting in a spreading-resistance penalty and increased operating voltages. The poor thermal conductivity of sapphire [0.349 (W/cm-° C.)], as compared with that of Si [1.49 (W/cm-° C.)] or SiC, also prevents efficient dissipation of heat generated by high-current devices, such as laser diodes and high-power transistors, consequently inhibiting device performance.
To minimize costs, it would be desirable to integrate GaN device fabrication into more conventional Si-based IC processes, which has the added cost benefit of using large-sized (Si) wafers. Si substrates are of particular interest because they are less expansive and they permit the integration of GaN-based photonics with well-established Si-based electronics. The cost of a GaN heterojunction field-effect transistor (HFET) for high frequency and high power application could be reduced significantly by replacing the expensive SiC substrates that are conventionally used.
The film cracking problem has been analyzed in depth by various groups, and several methods have been tested and achieve different degrees of success. The methods used to grow crack-free layers can be divided into two groups. The first method uses a modified buffer layer scheme. The second method uses an in-situ silicon nitride masking step. The modified buffer layer schemes include the use of a graded AlGaN buffer layer, AlN interlayers, and AlN/GaN or AlGaN/GaN-based superlattices.
Although the lattice buffer layer may absorb part of the thermal mismatch, the necessity of using temperatures higher than 1000° C. during epi growth and other device fabrication processes may cause wafer deformation. The wafer deformation can be reduced with a very slow rate of heating and cooling during wafer processing, but this adds additional cost to the process, and doesn't completely solve the thermal stress and wafer deformation issues.
It is generally understood that a buffer layer may reduce the magnitude of the tensile growth stress and, therefore, the total accumulated stress. However, from
It would be advantageous if the thermal mismatch problem associated with GaN-on-Si device technology could be practically eliminated by pre-compressing a thermal interface interposed between the GaN and Si layers.
The “a” lattice constants of GaN, Si, and sapphire are about 0.319 nanometers (nm), 0.543 nm, and 0.476 nm, respectively. For GaN on Si(111), the relevant comparison is aGaN to aSi/(21/2) giving a mismatch of about −20.4% at room temperature. For GaN on (0001) oriented sapphire, the relevant comparison is (3/2)1/2×aGaN to asapphire/2, leading to a mismatch of about +14% at room temperature. Thus, the lattice mismatch between GaN and sapphire is less severe than that between GaN and silicon.
The thermal expansion coefficients for GaN, Si, and sapphire are 4.3e-6 at 300K for a, 3.9e-6 at 300K for c, 2.57e-6 at 300K, and ˜4.0e-6 at 300K for both a and c, respectively, but rises very rapidly with temperature. The thermal expansion mismatch between GaN and Si is more severe than that between GaN and sapphire, as the former system results in GaN films under tensile strain (leading to cracking), and the latter system produces GaN under compressive stress, which causes fewer problems. Therefore, a new structure to release the thermal expansion related stress would be useful for growing GaN on silicon substrates.
The GaN growth temperature is normally 1050° C. or higher. Therefore, when the wafer is cooled down from the growth chamber, the GaN shrinks faster than the silicon substrate, but is partly restrained by the silicon. As a result, a tensile stress is applied to the GaN film that may cause the GaN film to crack. However, if a pre-compressed layer is formed on Si substrates at GaN growth temperatures, the pre-compressed layer reduces the tensile stress as the GaN film is cooled down from growth temperature, and a crack-free GaN film on Si can be made. Film materials such as Al2O3, Si1-xGex, InP, GaP, GaAs, AlN, AlGaN, or GaN, may be initially grown at a low temperature. Then, by increasing the growth temperatures, a compressed layer of epitaxial GaN can be formed on a Si substrate.
Accordingly, a method is provided for forming a matching thermal expansion interface between silicon (Si) and gallium nitride (GaN) films. The method provides a (111) Si substrate and forms a first aluminum (Al)-containing film in compression overlying the Si substrate. Using an anodized aluminum oxide (AAO) technology, nano-column holes are formed in the first Al-containing film, which exposes regions of the underlying Si substrate. A layer of GaN layer is selectively grown from the exposed regions, covering the first Al-containing film. The GaN is grown using a lateral nanoheteroepitaxy overgrowth (LNEO) process. The above-mentioned processes are reiterated, forming a second Al-containing film in compression, forming nano-column holes in the second Al-containing film, and selectively growing a second GaN layer using the LNEO process. In some aspects, a chemical mechanical polish (CMP) is applied to the GaN top surface, and a third layer of GaN is grown.
The first and second Al-containing films may be Al or AlN. Alternately, the first and second Al-containing films may be an AlN/graded AlGaN (Al1-xGaxN (0<x<1)) stack. In another aspect, the first and second Al-containing films may be an AlN/AlGaN/GaN stack.
Additional details of the above-mentioned method and a GaN-on-Si thermal expansion interface are provided below.
Table 1 and
In one aspect (detail A), the first and second Al-containing films 304 and 310 are an AlN film having a thickness 314 in a range of about 5 to 500 nanometers (nm). Alternately, the first and second Al-containing films 304 and 310 are an Al film having a thickness 314 in the range of 0.5 to 1.5 micrometers. In a second aspect (detail B), the first and second Al-containing films 304 and 310 are an AlN/graded AlGaN (Al1-xGaxN (0<x<1)) stack, where the AlN film 316 has a thickness 318 in a range of about 5 to 500 nm and the AlGaN film 320 has a thickness 322 in a range of about 5 to 500 nm. In a third aspect (detail C), the first and second Al-containing films 304 and 310 are an AlN/AlGaN/GaN stack, where the AlN film 324 has a thickness 326 in a range of about 5 to 500 nm, the AlGaN 328 is graded and has a thickness 330 in a range of about 5 to 500 nm, and the GaN 332 has a thickness 334 in a range of about 5 to 500 nm.
In another aspect, the nano-column holes 308 have a diameter 336 in arrange of about 10 to 100 nm, and are separated from adjacent nano-column holes by a distance 338 in a range of about 50 to 200 nm.
As applied to both
A pre-compressed layer is formed on Si substrates at GaN growth temperatures. The pre-compressed layer reduces the tensile stress as the GaN film is cooled down from growth temperature, and a crack-free GaN film on Si can be made. Materials such as Al2O3, Si1-xGex, InP, GaP, GaAs, AlN, AlGaN, and GaN may be initially grown at low temperature, with a subsequent increase to higher temperatures to form a compressed layer. The compressed layer acts as an interface between an epi GaN film and a Si substrate.
When a coating is cooled after deposition, and its thermal expansion coefficient, ac, is larger than that of the substrate, as, (as in the case of GaN on Si), the coating is under tensile strain. As a result, the uncracked film-substrate composite bends, having a radius of curvature, ρ, as
1/ρ=(as−ac)(Tf−Tg)/[h/2+2(Ec*Ic+Es*Is)/h(1/Ec*tc+1/Es*ts)] (1)
where Tf is the final temperature after cooling; Tg is the growth temperature; tc and ts are the individual coating and substrate thicknesses; h is the total thickness (h=tc+ts); I is the moment of inertia, I=t3/12; and E* is the effective modulus of elasticity. These conditions apply for wide layers and plane strain conditions E*=E/(12−v2), where E is the Young's modulus of elasticity and v is the Poisson's ratio.
From formula (1), the quantity [h/2+2(Ec*Ic+Es*Is)/h(1/Ec*tc+1/Es*ts)] is called A. A decreases with an increase in the thickness of the coating materials. But if tc<<ts, the coating thickness effect for A can be ignored. The formula (1) changes to
1/ρ=(as−ac)(Tf−Tg)/A (2)
Since the coating is thin (tc<0.1 ts), the predicted inplane normal stress in the uncracked coating is uniform and is given by
σp=1/ρ[2/htc(Ec*Ic+Es*Is)+Ec*tc/2] (3)
The quantity [2/htc(Ec*Ic+Es*Is)+Ec*tc/2] is called B. B increases with an increase in the thickness of coating materials. The formula (3) changes to
σp=B(as−ac)(Tf−Tg)/A (4)
Let B/A=R, which increases with an increase in the thickness of the coating materials. The formula (4) can be written as
σp=R(as−ac)(Tf−Tg) (5)
From formula (5), when the thermal expansion coefficient of the coating material is larger than that of the substrate and is deposited at higher temperatures, the coating materials are under tensile stress (σp>0) after cooling down. In contrast, when the thermal expansion coefficient of the coating material is larger than that of the substrate and deposited at lower temperatures, the coating materials is under compressive stress (σp<0) when heated to higher temperatures.
Therefore, if materials are grown with a higher thermal expansion coefficient on Si substrates at lower temperatures, the coated materials will be under compression when the wafer is heated to higher temperature, such as the temperatures required for GaN growth. During the wafer cooling down process, the compressed layer reduces the tensile stress of the overlying GaN films, and a crack-free GaN film on a Si substrate is formed.
Table 1 and
Alumina nano-column hole with sizes from 10 nm to 100 nm, and with an average distance between two holes of 50 nm to 200 nm, can be obtained by using an anodized aluminum oxide (AAO) technology, as shown in
The lateral nanoheteroepitaxy overgrowth (LENO) of GaN on Si is performed at a higher temperature of about 700-1200° C., as shown in
As noted above, anodized aluminum oxide (AAO) can be used as a nanosized porous alumina template hardmask to form nanosized patterns in Si (111), AlN, graded AlxGa1-xN (1≧x≧0), GaN, and other materials, as part of the process of forming a high quality thick GaN overgrowth. For example, high quality aluminum films can be deposited on a silicon substrate using E-beam evaporation, with a film thickness of 0.5 to 1.5 μm. Both oxalic and sulfuric acid may be used in the anodization process. In a first step, the aluminum coated wafers are immersed in acid solution at 0° C. for 5 to 10 minutes for an anodization treatment. Then, the alumina formed in the first anodic step is removed by immersion in a mixture of H3PO4 (4-16 wt %) and H2Cr2O4 (2-10 wt %) for 10 to 20 minutes. After cleaning the wafer surface, the aluminum film is exposed to a second anodic treatment, the same as the first step described above. Finally, the porous alumina template is further treated in 2-8 wt % H3PO4 aqueous solution for 15 to 90 minutes to increase the nano-column hole sizes.
Step 1002 provides a (111) Si substrate. Step 1004 forms a first aluminum (Al)-containing film in compression overlying the Si substrate. Step 1006 forms nano-column holes in the first Al-containing film. As noted above, an AAO process may be used to form the nano-column holes. However, the invention is not limited to just AAO technology. Step 1008 exposes regions of the underlying Si substrate. Using a lateral nanoheteroepitaxy overgrowth (LNEO) process, Step 1010 selectively grows a first GaN layer from the exposed regions, covering the first Al-containing film. That is, the GaN is more likely to grow on the exposed Si (or GaN) regions than it is on AAO. Typically, the first GaN layer has a thickness in a range of 0.3 to 1 micrometers. Step 1012 repeats Step 1004, 1006, 1008, and 1010. That is, Step 1012a forms a second Al-containing film in compression, Step 1012b forms nano-column holes in the second Al-containing film. In this case, regions of the first GaN layer are exposed. Step 1012c selectively grows a second GaN layer using the LNEO process. Typically, the second GaN layer has a thickness in the range of 1 to 4 micrometers.
In one aspect, forming the first and second Al-containing films in Step 1004 and 1012a includes each step forming an AlN film having a thickness in a range of about 5 to 500 nm. In another aspect, the film is Al, and the thickness in the range of 0.5 to 1.5 micrometers. In another aspect, Steps 1004 and 1012a each form an AlN/graded AlGaN (Al1-xGaxN (0<x<1)) stack, where the AlN film has a thickness in a range of about 5 to 500 nm and the AlGaN has a thickness in a range of about 5 to 500 nm. In a different aspect, Steps 1004 and 1012a each form an AlN/AlGaN/GaN stack, where the AlN film has a thickness in a range of about 5 to 500 nm, the AlGaN is graded and has a thickness in a range of about 5 to 500 nm, and the GaN has a thickness in a range of about 5 to 600 nm.
In one aspect, the nano-column holes formed in Steps 1006 and 1012b have a diameter in a range of about 10 to 100 nm, separated from adjacent nano-column holes by a distance in a range of about 50 to 200 nm.
In another aspect, selectively growing the second GaN layer in Step 1012c includes forming a GaN top surface. Then, Step 1014 performs a chemical mechanical polishing (CMP) on the GaN top surface, and Step 1016 selectively grows a third a GaN layer using the LNEO process overlying the CMP'ed GaN top surface.
Optionally, Step 1001 cleans a top surface of the Si substrate using an in-situ hydrogen treatment, prior to forming the first Al-containing film overlying the Si substrate.
In one aspect, selectively growing the first and GaN layers in Steps 1010 and 1012c includes heating the Si substrate to a temperature in a range of 700 to 1200° C.
In a different aspect, Steps 1005 and 1012a1 coat the first and second Al-containing films, respectively, with Si dioxide, prior to selectively growing the first and second GaN layers. Then, selective growing the first and second GaN layers in Steps 1010 and 1012c includes increasing the selectively of the GaN growth in response to coating the first and second Al-containing films with Si dioxide. That is, GaN is even less likely to grow on silicon dioxide than AAO.
A GaN-on-Si thermal expansion interface and associated fabrication process have been provided. Some examples and materials, dimensions, and process steps have been given to illustrate the invention. However, the invention is not limited to merely these examples. Other variations and embodiments of the invention will occur to those skilled in the art.
