Patent Application
20070119813
The present invention relates generally to semiconductor processing and more particularly to a hard mask structure and method of patterning gate or other features in the manufacture of transistor devices.
A conventional MOS transistor generally includes a semiconductor substrate, such as silicon, having a source, a drain, and a channel positioned between the source and drain. A gate stack composed of a conductive material (a gate conductor), a gate dielectric layer (a gate oxide), and sidewall spacers, is typically located above the channel. The gate dielectric is typically located directly above the channel, while the gate conductor, generally comprised of polycrystalline silicon (polysilicon) material, is located above the gate oxide. The sidewall spacers protect the sidewalls of the gate conductor.
The semiconductor industry continuously attempts to manufacture integrated circuits having geometric features that are decreasing in size, and these attempts in turn lead to the need for photolithographic techniques using shorter wavelengths in the mid and deep ultraviolet (DUV) spectrum to achieve fine features. In the process of defining very fine patterns, optical effects are often experienced which lead to distortion of images in the photoresist that are directly responsible for line width variations, and which in turn can compromise device performance.
Many of the optical effects that lead to distortion can be attributed to reflectivity of the underlying layers of materials, such as polysilicon and metals, which can produce spatial variations in the radiation intensity in the photoresist during exposure thereof, and in turn result in non-uniform line width development. Radiation can also scatter from the substrate and photoresist interfaces into areas where exposure is not intended, again resulting in line width variation.
As the wavelength of exposure sources is shortened to bring improved resolution by minimizing diffraction limitations, the difficulty in controlling reflections is increased. In an attempt to circumvent the reflection problems, a number of anti-reflective coatings (ARC) have been developed and are interposed between the substrate (or layer of interest) and the photoresist, but such solutions sometimes suffer varying shortcomings.
To further complicate the problem, photoresists for short wavelength exposure sources to deep ultraviolet (DUV) light are necessarily very thin, and either do not withstand, or are undercut during the subsequent etch process of the underlying layer, resulting in further deterioration of the line resolution. Clean-up and removal of both the resist, and the anti-reflective coating can present additional problems in the manufacturing process of sub-micron features.
As lithography techniques progress, for example, by moving to the 193 nm (nanometer) wavelength of an ArF excimer laser light, a need exists for a method to form sub-micron integrated circuit patterns which overlay varying topographies, and often highly reflective substrate or underlying layer materials. In particular, defining precise, sub-micron features in relatively thick doped and undoped polysilicon over gate oxide presents a significant challenge to the industry. A single layer, inorganic anti-reflective coating of silicon oxynitride (Six,OyNz) has been used in the industry as a hard mask to pattern the polysilicon gate, and while it has advantages, its selectivity to oxide, and slow removal rate with phosphoric acid post etch clean-up has an adverse effect on the polysilicon line definition, and may result in damage to active areas. Alternately, a bi-layer hard mask of silicon oxynitride over doped silicon oxide has been proposed. However, the optical properties of the oxide have a narrow process window, an undesirable feature for volume manufacturing, and further the process is complicated by the requirement of a special tool for removal.
Therefore, an anti-reflective hard mask coating for deep UV exposure in the 193 nm wavelength region which is compatible with polysilicon etch and clean-up processes, and which supports volume manufacturing requirements of sub-micron polysilicon features is clearly needed by the industry.
The following presents a simplified summary in order to provide a basic understanding of one or more aspects of the invention. This summary is not an extensive overview of the invention, and is neither intended to identify key or critical elements of the invention, nor to delineate the scope thereof. Rather, the primary purpose of the summary is to present some concepts of the invention in a simplified form as a prelude to the more detailed description that is presented later.
The present invention is directed to a multi-layer hard mask structure and associated method, wherein an ARC (anti-reflective coating) bi-layer is employed that exhibits a tunable layer that is operable to substantially match the index of refraction (n) and extinction coefficient (k) with respect to the overlying photoresist layer, for example, to minimize reflection with 193 nm wavelength exposure. The bi-layer overlies a gate electrode layer (e.g., a polysilicon layer) that will ultimately become a gate structure, and operates as an ARC when an overlying photoresist is undergoing exposure, and is subsequently patterned to serve as an etch hard mask for patterning the gate electrode.
Preferably the ARC mask comprises a bottom layer of greater than 200 angstroms, and less than 800 angstroms of silicon rich oxynitride having an extinction coefficient (at 193 nm) of from about 0.4 to about 1.6, and a top layer of about 300 angstroms of silicon oxynitride having an extinction coefficient of about 0.1. The silicon rich oxynitride is in direct contact with an underlying gate electrode layer overlying a gate oxide, or other dielectric layer. An etch hard mask is formed from the ARC bi-layer by etching in selected areas unprotected by an overlying photoresist. The resist is removed, for example, by plasma ashing, and the exposed polysilicon etched along with the silicon oxynitride layer, leaving primarily the silicon rich oxynitride to be removed by a phosphoric acid or other type post polysilicon etch clean-up, which does not damage active moat and gate areas.
According to one aspect of the invention, a method of patterning a gate electrode feature is disclosed, and comprises forming a hard mask layer over the gate electrode layer. The hard mask layer comprises a bi-layer, wherein a first layer comprises a silicon rich silicon oxynitride layer directly overlying the gate electrode layer, and a silicon oxynitride layer or a bottom anti-reflective coating (BARC) layer directly overlying the silicon rich silicon oxynitride layer. A photoresist layer is formed over the hard mask layer, exposed to 193 nm ultraviolet radiation, and developed, thereby defining a photoresist feature. The photoresist feature is used to pattern at least the top layer of the hard mask, and the remaining hard mask, at least the silicon rich silicon oxynitride layer is employed as the etch mask to pattern the underlying gate electrode layer. The oxygen content within the silicon rich silicon oxynitride layer may be varied to selectively reduce the index of refraction (n) and the extinction coefficient (k) of the film, thereby advantageously facilitating improved matching of such optical parameters with respect to the overlying photoresist, thereby reducing reflections during exposure.
In accordance with another aspect of the invention, the oxygen content within the silicon rich silicon oxynitride layer is less than the oxygen content in the overlying portion of the hard mask layer, thereby making the silicon rich silicon oxynitride-more “soft” with respect to a subsequent wet clean after patterning the gate electrode layer. Consequently, the clean operation does less damage to the underlying gate electrode layer, thereby improving the pattern transfer reliability. Such feature substantially improves integration of the gate patterning process with the rest of the integrated circuit fabrication.
According to another aspect of the invention, a method of tuning the optical properties of a hard mask layer to reduce reflectance associated therewith is provided. The method comprises evaluating one or more optical properties associated associated with a photoresist to be employed in a photolithographic patterning process. The method further comprises determining an amount of oxygen to incorporate within a silicon rich silicon oxynitride film portion of a hard mask layer, wherein the determination substantially matches the optical properties of the hard mask layer with that of the photoresist, thereby reducing reflectance associated therewith during an exposure of the photoresist.
In according with still another aspect of the invention, evaluating the optical properties of the photoresist comprises evaluating one or more of a composition and a thickness of the photoresist. In addition, determining the amount of oxygen comprises selecting a feed gas flow rate of a feed gas containing oxygen for a silicon rich silicon oxynitride layer deposition recipe to achieve the desired index of refraction (n) and the extinction coefficient (k) of the film.
According to yet another aspect of the invention, a hard mask structure for use in patterning a gate electrode is disclosed. The structure includes a gate structure overlying a semiconductor body, wherein the gate structure comprises a gate dielectric layer and a gate electrode layer overlying the gate dielectric layer. A hard mask bi-layer overlies the gate structure, and comprises a silicon rich silicon oxynitride layer, and a silicon oxynitride layer or a bottom anti-reflective coating (BARC) layer overlying the silicon rich silicon oxynitride layer. In one embodiment of the invention the silicon rich silicon oxynitride film comprises a stoichiometry of SiXOYNZ, wherein X>0.75 and Y>0.
In still another aspect of the invention a gate electrode feature is disclosed, wherein the gate electrode feature is formed by the process comprising forming a hard mask layer over a gate electrode layer, wherein the hard mask layer comprises a silicon rich silicon oxynitride layer, and a silicon oxynitride layer or bottom anti-reflective coating (BARC) layer overlying the silicon rich silicon oxynitride layer. A photoresist layer is formed over the hard mask layer, selectively exposed with 193 nm ultraviolet radiation, and developed to define a photoresist feature. The hard mask layer is then patterned using the photoresist feature as an etch mask, and the gate electrode is patterned using the patterned hard mask as an etch mask. The patterning of the gate electrode results in a substantial portion of the top layer of the bi-layer hard mask being removed. Subsequently, a clean operation is performed to remove a remaining portion of the bottom layer of the bi-layer hard mask.
In one embodiment of the invention, the bottom layer of the bi-layer hard mask has less than the oxygen content than the overlying portion of the hard mask bi-layer, wherein the oxygen content thereof causes the bottom portion of the hard mask to be relatively “soft” compared to the top hard mask layer with respect to the wet clean thereof. Consequently, the removal of the remaining hard mask is relatively easy, and results in reduced damage to the underlying gate electrode layer.
The following description and annexed drawings set forth in detail certain illustrative aspects and implementations of the invention. These are indicative of but a few of the various ways in which the principles of the invention may be employed.
One or more implementations of the present invention will now be described with reference to the attached drawings, wherein like reference numerals are used to refer to like elements throughout, and wherein the illustrated structures are not necessarily drawn to scale.
According to the invention, a method is provided for fabricating a semiconductor device having narrow, sharply defined gate electrode features (e.g., polysilicon) by using deep UV exposure, such as 193 nanometers (nm). The invention includes forming and employing a bi-layer hard mask, wherein a bottom layer of the hard mask comprises a silicon rich silicon oxynitride layer. The hard mask layer is sandwiched between the gate electrode layer and the photoresist layer, and serves both as an anti-reflective coating having highly selective optical properties, and as a hard mask that is stable during the etch of the gate electrode and the subsequent clean-up processes.
The method 100 begins with the formation of a gate dielectric layer and a gate electrode layer over a semiconductor body at 102. For example, as illustrated in
Returning to
In one aspect of the invention, the dual anti-reflective thin film hardmask layer of materials (e.g., a bi-layer) includes the silicon rich oxynitride (SRON) layer 214 overlying the polysilicon 212, and the silicon oxynitride (SiON) layer 216 over the SRON. One advantageous aspect of the present invention is the inorganic bi-layer film having specific anti-reflective properties that improves a depth of focus of the lithographic process. In addition, the bi-layer film exhibits a large process window, and operates as a hard mask which is able to withstand the subsequent etch process without deterioration of either the polysilicon line width, or the underlying oxide, moat, or other active areas.
Silicon oxynitride (SiXOYNZ) is an advantageous anti-reflective coating for deep UV resist exposures largely because of the low index of refraction or “n” value. Such films have been manufactured having an index of refraction in the range of 1.8 to 1.9, for example, and having extinction coefficients or “k” values which can be varied from, for example, 0.32 to 0.86. However, the removal of these materials is difficult without resulting in damage to the moat and the gate line width, thus making the single SiXOYNZ film unsatisfactory for manufacturing some types of semiconductor devices.
The bi-layer anti-reflective coating films 214 and 216 are formed over the wafer, for example, in a parallel plate PECVD (plasma enhanced chemical vapor deposition) reactor, such as a Centura Mainframe, DxZ process chamber as supplied by Applied Materials. The deposition processes for the bi-layer hardmask 214, 216 using the reactor includes, for example, a process temperature of 350 C., a pressure of 6.2 Torr, and an RF power of 60 Watts for SRON 214, and an RF power of 120 Watts for the SiON 216. For the silicon rich silicon oxynitride 214 deposition, in one example, SiH4 is introduced at 50 sccm, NH3 at 50 sccm, He at 1000 sccm, and N2O at 20 sccm. Following the SRON 214 deposition, a silicon oxynitride 216 (SiON) is formed in the same chamber by, for example, introducing SiH4 at 63 sccm, N2O at 187 sccm, and He at 1900 sccm.
The following are example flow rates for the formation of the SRON film 214 and the resultant stoichiometries associated therewith that may be employed in accordance with the present invention. In the table below, the RF is in Watts, Space is in mils, the gas flow rates are in sccm, and the deposition times are in seconds.
A photoresist layer is then formed over the bi-layer hard mask at 108 of
The method 100 then continues at 110, wherein the photoresist is selectively exposed to ultraviolet radiation (e.g., 193 nm wavelength) through, for example, a mask (not shown), resulting in a patterned photoresist mask 220, as illustrated in
The method 100 of
The remaining photoresist 218 left on top of the patterned bi-layer hardmask 221 is then removed at 114 of
The gate electrode layer 212 is then patterned using the bi-layer hardmask 221 as the etch mask at 116 of
As can be seen in
Fabrication of the polysilicon feature is completed by removing the silicon rich silicon nitride 214 using conventional hot phosphoric acid post polysilicon etch clean-up processing. The completed polysilicon feature 226 is illustrated in
In accordance with one advantageous aspect of the present invention, the top layer 216 of the bi-layer hardmask 221 is formed with more oxygen therein than in the underlying SRON layer 214. In the above example, the top SiON layer 216 is more “hard” than the lower layer with respect to the post-etch cleaning thereof, which is used to remove such layers after the gate electrode is patterned. Since the top layer 216 is exposed during a substantial amount of the gate electrode patterning, the increased oxygen makes the layer more selective with respect to the polysilicon etch and thus although the top layer 216 does experience a substantial amount of etching thereof, thus serving as a sacrificial layer, the top layer 216 can be maintained as thin as possible. After the patterning of the gate electrode 226, the top portion of the bi-layer hardmask 221 is substantially or entirely removed. Consequently, the post-etch clean-up the wet rinse is performed primarily or entirely on the underlying SRON layer 214.
The inventor of the present invention has advantageously appreciated a heretofore unappreciated integration advantage of having the silicon rich silicon oxynitride (SRON) layer 214 formed under the silicon oxynitride (SiON) layer 216. By maintaining less oxygen in the underlying SRON layer 214, the layer is more soft with respect to the wet etchant (the hot phosphoric acid rinse) used to remove such layer after the gate electrode 226 is defined. Accordingly, it has been found that removal of the SROn layer 214 with the hot phosphoric acid rinse can be performed with a higher dilution level, or for a shorter time, or both, than compared with a wet removal of the top portion 216 of the bi-layer 221. Consequently, the bi-layer hardmask 221 of the present invention results in less damage to the formed gate electrode and the exposed moat or active regions (if exposed in the process) during post-etch clean-up than in alternative type solutions where such layers in the bi-layer hardmask 221 may be switched.
According to another aspect of the present invention, a method of ascertaining a hardmask composition associated with the patterning of a gate electrode is provided herein, as illustrated in the flow chart of
The method 300 of
As can be seen in
While the invention has been illustrated and described with respect to one or more implementations, alterations and/or modifications may be made to the illustrated examples without departing from the spirit and scope of the appended claims. In particular regard to the various functions performed by the above described components or structures (assemblies, devices, circuits, systems, etc.), the terms (including a reference to a “means”) used to describe such components are intended to correspond, unless otherwise indicated, to any component or structure which performs the specified function of the described component (e.g., that is functionally equivalent), even though not structurally equivalent to the disclosed structure which performs the function in the herein illustrated implementations of the invention. In addition, while a particular feature of the invention may have been disclosed with respect to only one of several implementations, such feature may be combined with one or more other features of the other implementations as may be desired and advantageous for any given or particular application. Furthermore, to the extent that the terms “including”, “includes”, “having”, “has”, “with”, or variants thereof are used in either the detailed description and the claims, such terms are intended to be inclusive in a manner similar to the term “comprising”.
