Patent Application
20100041241
This invention relates to the field of integrated circuits. More particularly, this invention relates to high density plasma dielectric deposition.
High density plasma (HDP) chemical vapor deposition (CVD) of dielectric films is used in semiconductor processing to deposit dielectric films over severe topography without forming voids. HDP CVD deposition combines an etching component as well as a deposition component. The etching component is more effective on upper surfaces and open areas than on the lower surfaces within a gap so the dielectric thickness increases at a faster rate on the lower surfaces within the gap aiding the gap to fill without a void. A conventional gap filling process using HDP oxide typically consists of a first deposition step that deposits a liner oxide to reduce the aspect ratio and a second deposition step to fill the gap and deposit the bulk of the dielectric film.
Semiconductor geometries have scaled to smaller dimensions faster in the horizontal dimensions than in the vertical dimension. This has been done is to slow the rate that lead resistance increases as the lead dimensions scale. The result of scaling dimensions faster horizontally than vertically is an increase in aspect ratio making gap fill increasingly more challenging.
The following presents a simplified summary in order to provide a basic understanding of one or more aspects of the invention. This summary is not an extensive overview of the invention, and is neither intended to identify key or critical elements of the invention, nor to delineate the scope thereof. Rather, the primary purpose of the summary is to present some concepts of the invention in a simplified form as a prelude to a more detailed description that is presented later.
The deposition conditions of liner oxide in a two step HDP oxide gap fill process have been carefully optimized to reduce the aspect ratio of the gap and also to provide the gap with sloped sidewalls. This new liner process enables gaps with higher aspect ratios to be filled void free.
The present invention is described with reference to the attached figures, wherein like reference numerals are used throughout the figures to designate similar or equivalent elements. The figures are not drawn to scale and they are provided merely to illustrate the invention. Several aspects of the invention are described below with reference to example applications for illustration. It should be understood that numerous specific details, relationships, and methods are set forth to provide an understanding of the invention. One skilled in the relevant art, however, will readily recognize that the invention can be practiced without one or more of the specific details or with other methods. In other instances, well-known structures or operations are not shown in detail to avoid obscuring the invention. The present invention is not limited by the illustrated ordering of acts or events, as some acts may occur in different orders and/or concurrently with other acts or events. Furthermore, not all illustrated acts or events are required to implement a methodology in accordance with the present invention.
High density plasma deposition of dielectric films is used to deposit dielectrics over severe topography without forming voids. During the deposition, there is an etching component as well as a deposition component to the process. The etching component is more effective on upper surfaces than it is on lower surfaces so the dielectric thickness increases at a faster rate on the lower surfaces thus reducing the aspect ratio in narrow gaps. The etching to deposition ratio, E/D ratio, and the deposition pressure are key factors in controlling the gap filling capability of an HDP process. During HDP deposition the etching rate is primarily controlled by the partial pressure of Ar in the plasma and also by the high frequency power (HFRF). The deposition rate is primarily controlled by the SiH4 and O2 gas flow rates, temperature, pressure, and the low frequency power (LFRF).
Semiconductor geometries have scaled to smaller dimensions faster in the horizontal dimensions than in the vertical dimension. This is to slow the rate of resistance increase as the leads scale. The result of scaling dimensions faster horizontally than vertically is an increase in aspect ratio making void free gap fill increasingly more challenging.
The term “E/D ratio” refers to the ratio of the rate of etching of the dielectric film to the rate of the deposition of the dielectric film during a high density plasma (HDP) deposition.
The term “gap” refers to the trench that forms between two closely spaced structures. The aspect ratio of the gap is the ratio of the depth of the trench divided by the width of the trench.
The HDP gapfill process is typically done in two separate deposition steps with two different E/D ratios. The purpose of the first liner deposition step is to reduce the aspect ratio (depth/width) of the gap. The reduction in aspect ratio may enable the dielectric deposited during the second step to fill the reduced aspect ratio gap without forming a void. The purpose of the second deposition step is to fill the gap and to deposit the bulk of the dielectric film. In conventional HDP gapfill processes the first step liner process is done with a E/D ratio that is significantly lower than the E/D ratio of the second step liner process.
Electrical breakdown curves (5006) between two metal leads with metal filaments (3218) such as those shown in
In an embodiment of the instant invention it was discovered that reducing the deposition rate of the step one liner deposition by lowering the LFRF and also lowering the reactant (SiH4 and O2) flow rates and also increasing the E/D ratio during the first step liner deposition to be approximately the same or greater than the E/D ratio during the second gap fill deposition by increasing the HFRF power, produces a liner with a continuously sloping profile over the top corners of the gap with no damage to the top corners as shown in
High aspect ratio metal leads have been used to illustrate this embodiment, but other high aspect ratio gaps that may be formed between other structures such as gates in FLASH transistors or may be formed between active geometries may also be filled without voids with this embodiment.
The embodiment described above is a two step HDP process. It may be appreciated that those skilled in the art may add one or more additional deposition steps to the process and still utilize the ideas of this embodiment.
The embodiment described above is for HDP SiO2 deposition, but films containing nitrogen by incorporating a nitrogen containing gas such as, N2, NO or NH3 for example or incorporating dopant gases such as boron, fluorine, phosphorus, and arsenic containing gases may also be deposited.
While various embodiments of the present invention have been described above, it should be understood that they have been presented by way of example only and not limitation. Numerous changes to the disclosed embodiments can be made in accordance with the disclosure herein without departing from the spirit or scope of the invention. Thus, the breadth and scope of the present invention should not be limited by any of the above described embodiments. Rather, the scope of the invention should be defined in accordance with the following claims and their equivalents.
| Number | Date | Country | |
|---|---|---|---|
| 61088082 | Aug 2008 | US |
