Patent Application
20090001477
1. Field of the Invention
The present invention is generally related to semiconductor devices and more specifically to forming partially silicided and fully silicided structures.
2. Description of the Related Art
Modern semiconductor devices are usually formed with one or more transistors, for example, a Metal Oxide Semiconductor Field Effect Transistor (MOSFET). Exemplary MOSFET based transistors include the n-channel (n-MOS), p-channel (p-MOS), and the Complementary Metal Oxide Semiconductor (CMOS) transistors. Conventionally, the gate structures of these MOSFETS are formed predominantly with a polysilicon material with an overlying silicide layer. Such gate structures are typically referred to as a Partially Silicided (PASI) gate structure because it comprises a silicide layer 131 formed adjacent to a polysilicon material.
One problem with using PASI gate structures is that a region depleted of majority carriers may be formed in the polysilicon material during operation of the transistor. For example, a depletion region may be formed when the gate conductor of an n-MOS is biased positively with respect to the source to invert channel region. The formation of such a depletion region may make a gate dielectric layer thicker than intended. In other words, the thickness of the dielectric layer would include the thickness of the depletion region.
As is understood in the art, variations in the thickness of the gate dielectric layer may seriously impair the performance of a transistor. For example, variations in thickness of the gate dielectric layer may affect the speed at which the transistor may be operated. Furthermore, variations in thickness of the gate dielectric layer may cause the threshold voltage to fluctuate, thereby affecting the reliability of the transistor.
To circumvent the problems of dielectric layer thickness variations in PASI gate structures, some transistors include Fully Silicided (FUSI) gate structures. FUSI gate structures comprise a silicide layer extending all the way to the gate dielectric layer. In other words, a polysilicon region is not included in the gate structure. However, there are several problems associated with using FUSI gate structures also. For instance, FUSI gate structures suffer from threshold voltage stability problems, particularly in circuits using narrow channel MOSFETs, such as Static Random Access Memories (SRAMs) and analog differential amplifiers. It is likely that the threshold voltage instability is caused due to incomplete silicide formation in small geometry structures, thereby creating regions of polysilicon at the interface of the gate dielectric material. As a result of the threshold voltage instability, devices must be modeled with a threshold voltage that is higher than desired for optimum performance. Therefore, FUSI gates are not desired in the formation of circuits using narrow channels devices.
Yet another problem with transistors using FUSI gates is that over-voltages may not be applied on a FUSI gate structure. For example, Input/Output (IO) devices may frequently be operated at voltages that are far in excess of the on chip power supply voltages. Such voltages may present severe gate dielectric reliability concerns for FUSI gated IO devices. For example, a chip operating with a 1.2 Volt internal voltage supply may have to interface with external circuits driving input gates on the chip to 3.3 Volts or higher. It is likely that the high voltages applied at the gate may result in dielectric breakdown at the dielectric layer, thereby affecting performance of the device.
To avoid dielectric breakdown in FUSI gates, it may be necessary to thicken the dielectric layer which may significantly increase fabrication cost and complexity. Therefore, in circuits involving IO devices, the use of PASI transistors may be more desirable because a polysilicon gate, by its inherent gate depletion provides reliable operation with an overvoltage. In other words, a gate depletion region formed in PASI gates may provide a buffer region that drops a portion of the high input voltage, thereby reducing the possibility of dielectric breakdown.
A given circuit may include several devices, some of which may perform better with PASI structures, while others may perform better with FUSI structures. But forming PASI structures and FUSI structures separately may greatly increase the cost and complexity of fabrication.
Accordingly, there is a need for a semiconductor structure comprising both PASI structures and FUSI structures, and methods for efficiently fabricating both PASI structures and FUSI structures on the same substrate.
The present invention is generally related to semiconductor devices and more specifically to forming partially silicided and fully silicided structures.
One embodiment of the invention provides a method for forming a semiconductor structure. The method steps, in sequence, generally comprise forming a plurality of stack structures on a common substrate comprising at least one first stack structure and at least one second stack structure, each of the first stack structures and the second stack structures comprising a polysilicon layer and an oxide layer disposed on the polysilicon layer, whereby the at least one first stack structure is manufactured as a fully silicided (FUSI) stack and the at least one second stack structuer is manufactured as a partially silicided (PASI) stack.
The method further comprises exposing the polysilicon layer of the at least one second stack structure and depositing a first metal layer on the polysilicon layer of the at least one second stack structure and forming a first silicide layer on the polysilicon layer of the at least one second stack structure. The method still further comprises exposing the polysilicon layer of the at least one first stack structure and depositing a second metal layer on the polysilicon layer of the at least one first stack structure; and then forming a second silicide layer in the at least one first stack structure by causing the second metal layer to react with the polysilicon layer of the at least one first stack structure, wherein the second metal layer fully converts the polysilicon layer of the at least one first stack structure into the second silicide layer.
Another embodiment of the invention provides a semiconductor structure, generally comprising at least one fully silicided (FUSI) region, at least one partially silicided (PASI) region, and at least one resistor on a common substrate. The resistor comprises an unsilicided polysilicon region, and a first fully silicided region formed adjacent to a first surface of the unsilicided polysilicon region and a second fully silicided region formed adjacent to a second surface of the unsilicided polysilicon region, wherein each of the first fully silicided region and the second fully silicided region connects the resistor to a respective device.
Yet another embodiment of the invention provides a semiconductor structure comprising at least one resistor comprising an unsilicided polysilicon region and a first fully silicided region being formed adjacent to a first surface of the unsilicided polysilicon region and a second fully silicided region being formed adjacent to a second surface of the unsilicided polysilicon region, wherein each of the first fully silicided region and the second fully silicided region connects the resistor to a respective device.
So that the manner in which the above recited features, advantages and objects of the present invention are attained and can be understood in detail, a more particular description of the invention, briefly summarized above, may be had by reference to the embodiments thereof which are illustrated in the appended drawings.
It is to be noted, however, that the appended drawings illustrate only typical embodiments of this invention and are therefore not to be considered limiting of its scope, for the invention may admit to other equally effective embodiments.
The present invention is generally related to semiconductor devices and more specifically to forming partially silicided and fully silicided structures. Fabricating the partially silicided and fully silicided structures may involve creating one or more gate stacks. A polysilicon layer of a first gate stack may be exposed and a first metal layer may be deposited thereon to create a partially silicided structure. Thereafter, a polysilicon layer of a second gate stack may be exposed and a second metal layer may be deposited thereon to form a fully silicided structure. In some embodiments, the polysilicon layers of one or more gate stacks may not be exposed, and resistors may be formed with the unsilicided polysilicon layers.
In the following, reference is made to embodiments of the invention. However, it should be understood that the invention is not limited to specific described embodiments. Instead, any combination of the following features and elements, whether related to different embodiments or not, is contemplated to implement and practice the invention. Furthermore, in various embodiments the invention provides numerous advantages over the prior art. However, although embodiments of the invention may achieve advantages over other possible solutions and/or over the prior art, whether or not a particular advantage is achieved by a given embodiment is not limiting of the invention. Thus, the following aspects, features, embodiments and advantages are merely illustrative and are not considered elements or limitations of the appended claims except where explicitly recited in a claim(s). Likewise, reference to “the invention” shall not be construed as a generalization of any inventive subject matter disclosed herein and shall not be considered to be an element or limitation of the appended claims except where explicitly recited in a claim(s).
In one embodiment of the invention PASI gate devices 310 may be narrow channel devices. For example, in a particular embodiment, the PASI gate devices 310 may be one of an SRAM cell or a differential amplifier. Accordingly, the active regions 311 of the PASI gate devices 310 are shown having a relatively smaller geometry. Active regions 311 may be active silicon conductor regions of a transistor that are isolated by shallow trench isolation. For example, an active region 311 may include a source region, a drain region, and a channel region of a transistor.
As illustrated in
In some embodiments, it may be necessary to include one or more resistors in a circuit. For example, in system 300, a resistor 320 connects the gates of PASI gate transistors 310. The use of resistors may be particularly necessary in analog circuits. Embodiments of the invention also provide precision polysilicon resistors that may be formed during fabrication. The precision polysilicon resistor 320 may be superior to prior art resistors. For example, prior art resistors form a resistive element within a portion of a polysilicon line from which silicidation was blocked, and connect to the resistive element via adjacent partially silicided polysilicon conductors. The presence of adjacent partially silicided regions may introduce a variable component to the total resistance.
However, precision resistor 320 includes a polysilicon structure 321 connected to one or more other devices (for example, PASI gate transistors 310 in
System 300 may also include FUSI gate device 330. As illustrated in
System 300 also includes a PASI gate IO device 340. As illustrated PASI IO device 340 may include a PASI gate structure 342 formed over an active region 341. PASI gate IO device may interface with an IO device operating at a greater voltage than the devices in system 300. Therefore, a depletion region formed in the PASI gate structure 342 may diminish the effect of overvoltages that may result in breakdown in the gate dielectric layer.
As illustrated in
Fabrication of PASI and FUSI gate structures may begin by first forming gate stacks using one or more prior art methods.
As illustrated in
Source regions 431 and 432 may be doped with a predetermined amount of a suitable p-type or n-type dopant. Any suitable method for doping such as a diffusion based procedure and/or an ion implantation based procedure may be used to incorporate dopants into the substrate 433 to form the source regions 431 and drain regions 432.
A gate dielectric layer 440 may be formed on the substrate 433 using any conventional thermal growing process or by deposition. The gate dielectric layer may be composed of an oxide material including, but not limited to, SiO2, Al2O3, ZrO2, HfO2, Ta2O3, TiO2, silicates, or any combination of the above materials, with or without the addition of nitrogen. The gate dielectric layer is typically a relatively thin layer. For example, in some embodiments, the gate dielectric layer 440 is between 1 and 10 nanometers.
A gate stack may be formed on the dielectric layer 440, as illustrated in
In one embodiment of the invention, forming the FUSI and PASI gate structure may begin by depositing and patterning a layer of photoresist on the transistors 410 and 420. Patterning the photoresist layers may involve exposing the gate stacks that may be used to form PASI gate structures. For example,
The oxide layer 462 exposed by the patterning of the photoresist mask 510 may be removed using a suitable etching process. For example, in one embodiment, a wet etching process using an etchant such as hydrofluoric acid (HF) may be used to remove the oxide layer exposed by the photoresist mask 510. However, any alternative etchant, or alternative etching process, for example, a dry etching process may also be used to remove the oxide layer 462.
After the oxide layer 462 is removed, the photoresist layer 510 may be stripped and exposed surfaces may be cleaned using dilute HF to remove any particles left behind after the etching process. A layer of an electropositive material, for example, for example, a suitable metal may be deposited on the surface of the exposed surfaces. In one embodiment of the invention, a layer of cobalt may be deposited on the exposed surfaces.
Alternatively, the metal layer 710 may be formed selectively on exposed silicon surfaces. For example,
The deposited metal layer 710 may be made to react with the polysilicon layer 462 and the source and drain regions of transistors 410 and 420 in one or more annealing procedures. For example, in one embodiment, a first annealing procedure may be performed between around 450° C. and 550° C. In one embodiment of the invention, the first annealing procedure may be a rapid thermal anneal (RTA). The first anneal procedure may begin a silicidation process for forming a PASI gate structure at transistor 420. For example, the first anneal procedure may cause the metal layer 710 to react with the polysilicon layer 462 of transistor 420, thereby forming a silicide layer 910, as illustrated in
In one embodiment, if the metal layer 710 was not selectively deposited on the silicon surfaces, unreacted metal on the oxide layer 451 and the nitride spacers 470 may be removed using a selective wet etch comprising, for example, hydrochloric acid (HCl). In one embodiment, the HCl may comprise around 30% hydrogen peroxide (H2O2). In one embodiment of the invention, following removal of the excess cobalt using the wet chemical etch, a second anneal procedure may be performed. The second anneal procedure may result in increasing the volume of the silicide layer 910 to a desired depth. In one embodiment, the depth of the silicide layer after the second anneal procedure may be between around 5 nanometers and 15 nanometers. Furthermore, the second anneal procedure may result in the formation of silicide layers 920 on the source and drain regions of each of transistors 410 and 420, as illustrated in
Subsequent to the formation of the PASI gate structure at transistor 420, oxide cap 451 of transistor 410 may be removed. In one embodiment, oxide cap 451 may be removed using a suitable etchant, for example, buffered HF. Following removal of the oxide layer 451, exposed surfaces may be cleaned by an argon sputtering cleaning procedure. A second metal layer 1010 may then be deposited on the exposed surfaces using a Physical Vapor Deposition (PVD) process, as illustrated in
A low temperature anneal procedure may be performed to diffuse the metal layer 1010 into the polysilicon layer 452 to form a silicide material. In one embodiment, the anneal procedure may comprise a rapid thermal anneal (RTA) ramped procedure at around 10° C./second, followed by a soak period and a ramp down period. The soak period may last up to around 90 seconds at a temperature between around 350° C. to around 550° C. In some embodiments, a spike anneal procedure may be performed. In other words, the soak anneal may be avoided.
The silicide layers 910 and 920 may substantially block the diffusion of the metal layer 1010 into the source and drain regions of transistors 410 and 420 and the polysilicon layer 461 of transistor 420, thereby preventing formation of nickel silicide in these areas. The metal layer 1010, however, may diffuse completely into the polysilicon layer 451 of transistor 410, thereby creating a FUSI gate structure.
Following formation of the FUSI gate structure at transistor 410, the optional TiN layer and any excess metal may be removed using a wet etching process. The wet etching process may involve the use of any combination of sulfuric acid, hydrogen peroxide, and water as the etchant. The resulting transistor structures are illustrated in
While fabrication of two transistors 410 and 420 are described herein, one skilled in the art will recognize that any number of FUSI gate and PASI gate transistors may be constructed simultaneously while performing the method steps described above. By providing a simple method for simultaneously fabricating PASI and FUSI gate devices, embodiments of the invention greatly reduce the cost and complexity of fabrication.
In one embodiment of the invention, fabricating a resistor 320 may involve preventing silicidation of at least a part of one or more polysilicon lines. For example, referring to
By allowing formation of FUSI and PASI structures on the same substrate using method steps disclosed herein, embodiments of the invention may reduce the cost and complexity of fabrication of circuits requiring both PASI and FUSI structures. Furthermore, embodiments of the invention also facilitate formation of high precision resistors that may be superior to prior art resistors.
While the foregoing is directed to embodiments of the present invention, other and further embodiments of the invention may be devised without departing from the basic scope thereof, and the scope thereof is determined by the claims that follow.
