Patent Application
20240222274
A front-end-of-line (FEOL) layer of an integrated circuit (IC) die generally refers to a layer in which active or passive circuitry based on highly crystalline semiconductor materials are formed, e.g., front-end transistors of logic devices. A back-end-of-line (BEOL) layer of such a die refers to a layer above the FEOL layer, in which either further active or passive circuitry (e.g., back-end transistors) and/or conductive pathways for providing connectivity for the active or passive circuitry are formed. A die typically includes multiple BEOL layers where conductive pathways such as conductive traces and/or conductive vias are included. In general, FEOL and BEOL refer to different layers, or different fabrication processes used to manufacture different portions of IC devices in context of complementary metal oxide semiconductor (CMOS) processes (e.g., logic devices in the FEOL layer, peripheral circuitry and/or interconnects in the BEOL layer). A far BEOL (FBEOL) layer of an IC die is a layer above the one or more BEOL layers, the FBEOL layer typically including a top metal layer, a passivation layer, and conductive contacts for coupling the die to other components such as a package substrate, an interposer, a circuit board, or another die.
For the past several decades, the scaling of features in integrated circuits has been a driving force behind an ever-growing semiconductor industry. Scaling to smaller and smaller features enables increased densities of functional units on the limited real estate of semiconductor dies. For example, shrinking transistor size allows for the incorporation of an increased number of memory or logic devices on a die, lending to the fabrication of products with increased capacity. The drive for the ever-increasing capacity, however, is not without issue. The necessity to optimize the performance of each IC die and each IC package that includes one or more dies becomes increasingly significant. In particular, heterogenous/disaggregated packaging architectures aim to optimize performance by disaggregating single monolithic die into multiple dies (also referred to as “chiplets” or “tiles”) such as compute, graphics, system-on-chip (SoC), etc. These different dies could be manufactured by different foundries and/or according to different manufacturing technologies for better performance, optimized yield, cost, or accelerated ramp, and later assembled into a single package. However, dies manufactured by different foundries and/or according to different manufacturing technologies may differ in, e.g., metallurgy, topography, and passivation surfaces, which, in turn, result in different assembly design rules (DRs). Attaching such dies onto a single package substrate, interposer, or a mold complex presents significant challenges due to bumping and assembly DR differences, bonding yield, passivation mismatch, chip-to-package interactions, etc. These challenges are generally present for all disaggregated technologies, and if FBEOL processes for two dies are radically different, the challenges are exacerbated even further.
Embodiments will be readily understood by the following detailed description in conjunction with the accompanying drawings. To facilitate this description, like reference numerals designate like structural elements. Embodiments are illustrated by way of example, not by way of limitation, in the figures of the accompanying drawings.
Hybrid integration of BEOL layers for disaggregated technologies and associated IC dies, microelectronic assemblies, and related devices and methods, are disclosed herein. In particular, such hybrid integration is applicable to scenarios where an IC die with an FEOL layer and one or more BEOL layers, including FBEOL layers, manufactured by one foundry, is processed further by another foundry to add additional BEOL layers to make the die compatible with dies manufactured by that foundry or further foundries. In some embodiments, a resulting IC die may include an FEOL layer that includes a plurality of transistors, a first BEOL layer comprising first interconnects, a second BEOL layer comprising second interconnects, and a third BEOL layer comprising third interconnects, wherein the first BEOL layer is between the FEOL layer and the second BEOL layer, the second BEOL layer is between the first BEOL layer and the third BEOL layer, and an electrically conductive fill material of the second interconnects is different from an electrically conductive fill material of the first interconnects and from an electrically conductive fill material of the third interconnects. Various ones of the embodiments disclosed herein may help achieve reliable inclusion, in a single package, of multiple IC dies at a lower cost, with improved power efficiency, with higher bandwidth, and/or with greater design flexibility, relative to conventional approaches. Various ones of the microelectronic assemblies disclosed herein may exhibit better power delivery and signal speed while reducing the size of the package relative to conventional approaches. The microelectronic assemblies disclosed herein may be particularly advantageous for small and low-profile applications in computers, tablets, industrial robots, and consumer electronics (e.g., wearable devices).
In the following detailed description, reference is made to the accompanying drawings that form a part hereof wherein like numerals designate like parts throughout, and in which is shown, by way of illustration, embodiments that may be practiced. It is to be understood that other embodiments may be utilized, and structural or logical changes may be made without departing from the scope of the present disclosure. Therefore, the following detailed description is not to be taken in a limiting sense.
For convenience, the phrase “
Various operations may be described as multiple discrete actions or operations in turn, in a manner that is most helpful in understanding the claimed subject matter. However, the order of description should not be construed as to imply that these operations are necessarily order dependent. In particular, these operations may not be performed in the order of presentation. Operations described may be performed in a different order from the described embodiment. Various additional operations may be performed, and/or described operations may be omitted in additional embodiments.
For the purposes of the present disclosure, the phrase “A and/or B” means (A), (B), or (A and B). For the purposes of the present disclosure, the phrase “A, B, and/or C” means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C). When used to describe a range of dimensions, the phrase “between X and Y” represents a range that includes X and Y. When used to describe a location of an element, the phrase “between X and Y” represents a region that is spatially between element X and element Y. Although certain elements may be referred to in the singular herein, such elements may include multiple sub-elements. For example, “an insulating material” may include one or more insulating materials, while a “metal” may include one or more metals.
The description uses the phrases “in an embodiment” or “in embodiments,” which may each refer to one or more of the same or different embodiments. Furthermore, the terms “comprising,” “including,” “having,” and the like, as used with respect to embodiments of the present disclosure, are synonymous. As used herein, a “package” and an “IC package” are synonymous, as are a “die” and an “IC die.” As used herein, the term “insulating” means “electrically insulating,” unless otherwise specified. The disclosure may use perspective-based descriptions such as “above,” “below,” “top,” “bottom,” and “side”; such descriptions are used to facilitate the discussion and are not intended to restrict the application of disclosed embodiments. Unless otherwise specified, the use of the ordinal adjectives “first,” “second,” and “third,” etc., to describe a common object, merely indicate that different instances of like objects are being referred to and are not intended to imply that the objects so described must be in a given sequence, either temporally, spatially, in ranking or in any other manner.
In the following detailed description, various aspects of the illustrative implementations may be described using terms commonly employed by those skilled in the art to convey the substance of their work to others skilled in the art. For example, if used, the terms “oxide,” “carbide,” “nitride,” “sulfide,” etc. refer to compounds containing, respectively, oxygen, carbon, nitrogen, sulfur, etc., the term “high-k dielectric” refers to a material having a higher dielectric constant (k) than silicon oxide, while the term “low-k dielectric” refers to a material having a lower k than silicon oxide. In another example, as used herein, a “conductive contact” may refer to a portion of conductive material (e.g., metal) serving as an electrical interface between different components; conductive contacts may be recessed in, flush with, or extending away from a surface of a component, and may take any suitable form (e.g., a conductive pad or socket, or portion of a conductive line or via). The terms “substantially,” “close,” “approximately,” “near,” and “about,” generally refer to being within +/−20%, e.g., within +/−5% or within +/−2%, of a target value based on the context of a particular value as described herein or as known in the art. Similarly, terms indicating orientation of various elements, e.g., “coplanar,” “perpendicular,” “orthogonal,” “parallel,” or any other angle between the elements, generally refer to being within +/−20%, e.g., within +/−5% or within +/−2%, of a target value based on the context of a particular value as described herein or as known in the art.
The microelectronic assembly 100 may include a package substrate 102 coupled to a die 114-1 by die-to-package substrate (DTPS) interconnects 150-1. In particular, the top surface of the package substrate 102 may include a set of conductive contacts 146, and the bottom surface of the die 114-1 may include a set of conductive contacts 122; the conductive contacts 122 at the bottom surface of the die 114-1 may be electrically and mechanically coupled to the conductive contacts 146 at the top surface of the package substrate 102 by the DTPS interconnects 150-1. In the embodiment of
The package substrate 102 may include an insulating material (e.g., a dielectric material formed in multiple layers, as known in the art) and one or more conductive pathways through the dielectric material (e.g., including conductive traces and/or conductive vias, as shown). In some embodiments, the insulating material of the package substrate 102 may be a dielectric material, such as an organic dielectric material, a fire retardant grade 4 material (FR-4), bismaleimide triazine (BT) resin, polyimide materials, glass reinforced epoxy matrix materials, or low-k and ultra low-k dielectric (e.g., carbon-doped dielectrics, fluorine-doped dielectrics, porous dielectrics, and organic polymeric dielectrics). In particular, when the package substrate 102 is formed using standard printed circuit board (PCB) processes, the package substrate 102 may include FR-4, and the conductive pathways in the package substrate 102 may be formed by patterned sheets of copper separated by build-up layers of the FR-4. The conductive pathways in the package substrate 102 may be bordered by liner materials, such as adhesion liners and/or barrier liners, as suitable.
In some embodiments, one or more of the conductive pathways in the package substrate 102 may extend between a conductive contact 146 at the top surface of the package substrate 102 and a conductive contact 140 at the bottom surface of the package substrate 102. In some embodiments, one or more of the conductive pathways in the package substrate 102 may extend between a conductive contact 146 at the bottom of the recess 108 and a conductive contact 140 at the bottom surface of the package substrate 102. In some embodiments, one or more of the conductive pathways in the package substrate 102 may extend between different conductive contacts 146 at the top surface of the package substrate 102 (e.g., between a conductive contact 146 at the bottom of the recess 108 and a different conductive contact 146 at the top surface of the package substrate 102). In some embodiments, one or more of the conductive pathways in the package substrate 102 may extend between different conductive contacts 140 at the bottom surface of the package substrate 102.
The dies 114 disclosed herein may include an insulating material (e.g., a dielectric material formed in multiple layers, as known in the art) and multiple conductive pathways formed through the insulating material. In some embodiments, the insulating material of a die 114 may include a dielectric material, such as silicon dioxide, silicon nitride, oxynitride, polyimide materials, glass reinforced epoxy matrix materials, or a low-k or ultra low-k dielectric (e.g., carbon-doped dielectrics, fluorine-doped dielectrics, porous dielectrics, organic polymeric dielectrics, photo-imageable dielectrics, and/or benzocyclobutene-based polymers). In some embodiments, the insulating material of a die 114 may include a semiconductor material, such as silicon, germanium, or a Ill-V material (e.g., gallium nitride), and one or more additional materials. For example, an insulating material may include silicon oxide or silicon nitride. The conductive pathways in a die 114 may include conductive traces and/or conductive vias, and may connect any of the conductive contacts in the die 114 in any suitable manner (e.g., connecting multiple conductive contacts on a same surface or on different surfaces of the die 114). Example structures that may be included in the dies 114 disclosed herein are discussed below with reference to
In some embodiments, the die 114-1 may include conductive pathways to route power, ground, and/or signals to/from some of the other dies 114 included in the microelectronic assembly 100. For example, the die 114-1 may include through-substrate vias (TSVs, including a conductive material via, such as a metal via, isolated from the surrounding silicon or other semiconductor material by a barrier oxide) or other conductive pathways through which power, ground, and/or signals may be transmitted between the package substrate 102 and one or more dies 114 “on top” of the die 114-1 (e.g., in the embodiment of
In some embodiments, the die 114-1 may not route power and/or ground to the die 114-2; instead, the die 114-2 may couple directly to power and/or ground lines in the package substrate 102. By allowing the die 114-2 to couple directly to power and/or ground lines in the package substrate 102, such power and/or ground lines need not be routed through the die 114-1, allowing the die 114-1 to be made smaller or to include more active circuitry or signal pathways.
In some embodiments, the die 114-1 may only include conductive pathways, and may not contain active or passive circuitry. In other embodiments, the die 114-1 may include active or passive circuitry (e.g., transistors, diodes, resistors, inductors, and capacitors, among others). In some embodiments, the die 114-1 may include one or more device layers including transistors (e.g., as discussed below with reference to
Although
In some embodiments, the package substrate 102 may be a lower density medium and the die 114-1 may be a higher density medium. As used herein, the term “lower density” and “higher density” are relative terms indicating that the conductive pathways (e.g., including conductive lines and conductive vias) in a lower density medium are larger and/or have a greater pitch than the conductive pathways in a higher density medium. In some embodiments, a higher density medium may be manufactured using a modified semi-additive process or a semi-additive build-up process with advanced lithography (with small vertical interconnect features formed by advanced laser or lithography processes), while a lower density medium may be a PCB manufactured using a standard PCB process (e.g., a standard subtractive process using etch chemistry to remove areas of unwanted copper, and with coarse vertical interconnect features formed by a standard laser process).
The microelectronic assembly 100 of
The die 114-2 may extend over the die 114-1 by an overlap distance 191. In some embodiments, the overlap distance 191 may be between 0.5 millimeters and 5 millimeters (e.g., between 0.75 millimeters and 2 millimeters, or approximately 1 millimeter).
The microelectronic assembly 100 of
As discussed above, in the embodiment of
The microelectronic assembly 100 of
The microelectronic assembly 100 of
The microelectronic assembly 100 of
The microelectronic assembly 100 of
The microelectronic assembly 100 of
The DTPS interconnects 150 disclosed herein may take any suitable form. In some embodiments, a set of DTPS interconnects 150 may include solder (e.g., solder bumps or balls that are subject to a thermal reflow to form the DTPS interconnects 150). DTPS interconnects 150 that include solder may include any appropriate solder material, such as lead/tin, tin/bismuth, eutectic tin/silver, ternary tin/silver/copper, eutectic tin/copper, tin/nickel/copper, tin/bismuth/copper, tin/indium/copper, tin/zinc/indium/bismuth, or other alloys. In some embodiments, a set of DTPS interconnects 150 may include an anisotropic conductive material, such as an anisotropic conductive film or an anisotropic conductive paste. An anisotropic conductive material may include conductive materials dispersed in a non-conductive material. In some embodiments, an anisotropic conductive material may include microscopic conductive particles embedded in a binder or a thermoset adhesive film (e.g., a thermoset biphenyl-type epoxy resin, or an acrylic-based material). In some embodiments, the conductive particles may include a polymer and/or one or more metals (e.g., nickel or gold). For example, the conductive particles may include nickel-coated gold or silver-coated copper that is in turn coated with a polymer. In another example, the conductive particles may include nickel. When an anisotropic conductive material is uncompressed, there may be no conductive pathway from one side of the material to the other. However, when the anisotropic conductive material is adequately compressed (e.g., by conductive contacts on either side of the anisotropic conductive material), the conductive materials near the region of compression may contact each other so as to form a conductive pathway from one side of the film to the other in the region of compression.
The DTD interconnects 130 disclosed herein may take any suitable form. The DTD interconnects 130 may have a finer pitch than the DTPS interconnects 150 in a microelectronic assembly. In some embodiments, the dies 114 on either side of a set of DTD interconnects 130 may be unpackaged dies, and/or the DTD interconnects 130 may include small conductive bumps or pillars (e.g., copper bumps or pillars) attached to the conductive contacts 124 by solder. The DTD interconnects 130 may have too fine a pitch to couple to the package substrate 102 directly (e.g., to fine to serve as DTPS interconnects 150). In some embodiments, a set of DTD interconnects 130 may include solder. DTD interconnects 130 that include solder may include any appropriate solder material, such as any of the materials discussed above. In some embodiments, a set of DTD interconnects 130 may include an anisotropic conductive material, such as any of the materials discussed above. In some embodiments, the DTD interconnects 130 may be used as data transfer lanes, while the DTPS interconnects 150 may be used for power and ground lines, among others.
In some embodiments, some or all of the DTD interconnects 130 in a microelectronic assembly 100 may be metal-to-metal interconnects (e.g., copper-to-copper interconnects, or plated interconnects). In such embodiments, the conductive contacts 124 on either side of the DTD interconnect 130 may be bonded together (e.g., under elevated pressure and/or temperature) without the use of intervening solder or an anisotropic conductive material. In some embodiments, a thin cap of solder may be used in a metal-to-metal interconnect to accommodate planarity, and this solder may become an intermetallic compound during processing. In some metal-to-metal interconnects that utilize hybrid bonding, a dielectric material (e.g., silicon oxide, silicon nitride, silicon carbide, or an organic layer) may be present between the metals bonded together (e.g., between copper pads or posts that provide the associated conductive contacts 124). In some embodiments, one side of a DTD interconnect 130 may include a metal pillar (e.g., a copper pillar), and the other side of the DTD interconnect may include a metal contact (e.g., a copper contact) recessed in a dielectric. In some embodiments, a metal-to-metal interconnect (e.g., a copper-to-copper interconnect) may include a noble metal (e.g., gold) or a metal whose oxides are conductive (e.g., silver). In some embodiments, a metal-to-metal interconnect may include metal nanostructures (e.g., nanorods) that may have a reduced melting point. Metal-to-metal interconnects may be capable of reliably conducting a higher current than other types of interconnects; for example, some solder interconnects may form brittle intermetallic compounds when current flows, and the maximum current provided through such interconnects may be constrained to mitigate mechanical failure.
In some embodiments, some or all of the DTD interconnects 130 in a microelectronic assembly 100 may be solder interconnects that include a solder with a higher melting point than a solder included in some or all of the DTPS interconnects 150. For example, when the DTD interconnects 130 in a microelectronic assembly 100 are formed before the DTPS interconnects 150 are formed (e.g., as discussed below with reference to
In the microelectronic assemblies 100 disclosed herein, some or all of the DTPS interconnects 150 may have a larger pitch than some or all of the DTD interconnects 130. DTD interconnects 130 may have a smaller pitch than DTPS interconnects 150 due to the greater similarity of materials in the different dies 114 on either side of a set of DTD interconnects 130 than between the die 114 and the package substrate 102 on either side of a set of DTPS interconnects 150. In particular, the differences in the material composition of a die 114 and a package substrate 102 may result in differential expansion and contraction of the die 114 and the package substrate 102 due to heat generated during operation (as well as the heat applied during various manufacturing operations). To mitigate damage caused by this differential expansion and contraction (e.g., cracking, solder bridging, etc.), the DTPS interconnects 150 may be formed larger and farther apart than DTD interconnects 130, which may experience less thermal stress due to the greater material similarity of the pair of dies 114 on either side of the DTD interconnects. In some embodiments, the DTPS interconnects 150 disclosed herein may have a pitch between 80 microns and 300 microns, while the DTD interconnects 130 disclosed herein may have a pitch between 7 microns and 100 microns.
The elements of the microelectronic assembly 100 may have any suitable dimensions. Only a subset of the accompanying figures are labeled with reference numerals representing dimensions, but this is simply for clarity of illustration, and any of the microelectronic assemblies 100 disclosed herein may have components having the dimensions discussed herein. For example, in some embodiments, the thickness 164 of the package substrate 102 may be between 0.1 millimeters and 1.4 millimeters (e.g., between 0.1 millimeters and 0.35 millimeters, between 0.25 millimeters and 0.8 millimeters, or approximately 1 millimeter). In some embodiments, the recess 108 may have a depth 175 between 10 microns and 200 microns (e.g., between 10 microns and 30 microns, between 30 microns and 100 microns, between 60 microns and 80 microns, or approximately 75 microns). In some embodiments, the depth 175 may be equal to a certain number of layers of the dielectric material in the package substrate 102. For example, the depth 175 may be approximately equal to between one and five layers of the dielectric material in the package substrate 102 (e.g., two or three layers of the dielectric material). In some embodiments, the depth 175 may be equal to the thickness of a solder resist material (not shown) on the top surface of the package substrate 102.
In some embodiments, the distance 179 between the bottom surface of the die 114-1 and the proximate top surface of the package substrate 102 (at the bottom of the recess 108) may be less than the distance 177 between the bottom surface of the die 114-2 and the proximate top surface of the package substrate 102. In some embodiments, the distance 179 may be approximately the same as the distance 177. In some embodiments, the distance 177 between the bottom surface of the die 114-2 and the proximate top surface of the package substrate 102 may be greater than the distance 193 between the bottom surface of the die 114-2 and the proximate top surface of the die 114-1. In other embodiments, the distance 177 may be less than or equal to the distance 193.
In some embodiments, the top surface of the die 114-1 may extend higher than the top surface of the package substrate 102, as illustrated in
In the embodiment of
In some embodiments, the die 114-1 may be arranged as a bridge between multiple other dies 114, and may also have additional dies 114 disposed thereon. For example,
As noted above, any suitable number of the dies 114 in a microelectronic assembly 100 may be double-sided dies 114. For example,
As noted above, a package substrate 102 may include one or more recesses 108 in which dies 114 are at least partially disposed. For example,
The die 114-6 also includes conductive contacts 124 at its top surface; these conductive contacts 124 are coupled to conductive contacts 124 at the bottom surface of a die 114-7 by DTD interconnects 130-3. Further, the microelectronic assembly 100 of
In various ones of the microelectronic assemblies 100 disclosed herein, a single die 114 may bridge to other dies 114 from “below” (e.g., as discussed above with reference to
As noted above, in some embodiments, the package substrate 102 may not include any recesses 108. For example,
Any of the arrangements of dies 114 illustrated in any of the accompanying figures may be part of a repeating pattern in a microelectronic assembly 100. For example,
In some deployment scenarios, different ones of the dies 114 may be manufactured by different foundries and/or according to different manufacturing technologies for better performance, optimized yield, cost, or accelerated ramp, and later assembled into a single microelectronic assembly 100 according to any embodiments described above. In such scenarios, any one of the dies 114 may be fabricated using hybrid integration of BEOL layers for disaggregated technologies according to a method 200 of
Although the operations of the manufacturing method illustrated in
Turning to the method 200, at 202, a die may be received. A die 302, depicted in
The die 302 may further include a first BEOL layer 340-1 over the FEOL layer 334 and a second BEOL layer 340-2 over the first BEOL layer 340-2 (together, the first and second BEOL layers 340-1 and 340-2, as well as additional BEOL layers 340-3, 340-4, etc., shown in subsequent drawings, may be referred to as “BEOL layers 340”). The first BEOL layer 340-1 may include a plurality of first conductive pathways 342-1 in a first insulating material 344-1, while the second BEOL layer 340-2 may include a plurality of second conductive pathways 342-2 in a first insulating material 344-2 (together, the first and second conductive pathways 342-1 and 342-2, as well as additional conductive pathways 342-3, 342-4, etc., shown in subsequent drawings, may be referred to as “conductive pathways 342,” while the first and second insulating materials 344-1 and 344-2, as well as additional insulating materials 344-3, 344-4, etc., shown in subsequent drawings, may be referred to as “insulating materials 344”). Any of the conductive pathways 342 may include conductive traces and/or conductive vias, e.g., such as lines 1628a and/or vias 1628b described with reference to
The top BEOL layer of the die 302 received at 202, i.e., the second BEOL layer 340-2, may include various conductive features protruding from the top surface of the second insulating material 344-2. One example of such conductive features, shown in
The die 302 may be an example of a portion of any of the dies 114 of the microelectronic assembly 100, where the conductive pathways 342 may take form of any of the conductive pathways to route power, ground, and/or signals to various components of the die 302 (e.g., to the active or passive circuitry 336), to/from other dies, and/or to/from other components of the microelectronic assembly 100 (e.g., to/from the package substrate 102) as described above. For example, the conductive pathways 342 may include TSVs, including a conductive material via, such as a metal via, isolated from the surrounding silicon or other semiconductor material by a barrier oxide, or other conductive pathways through which power, ground, and/or signals may be transmitted in/through the die 302. The conductive pathways 342 may be formed of any appropriate conductive material, such as copper, silver, nickel, gold, aluminum, or other metals or alloys, for example. In some embodiments, the conductive pathways 342 in different BEOL layers 340 may be formed of different conductive materials; e.g., in some embodiments, the first conductive pathways 342-1 may be formed of copper, while the second conductive pathways 342-2 may be formed of aluminum. Similarly, the insulating materials 344 in different BEOL layers 340 may be same or different insulating materials, and may include any of the insulating materials typically used as interlayer dielectric (ILD) materials, such as low-k and ultra low-k dielectrics (e.g., carbon-doped dielectrics, fluorine-doped dielectrics, porous dielectrics, and organic polymeric dielectrics).
The conductive contacts 348 may be implemented similar to any of the conductive contacts of the microelectronic assembly 100, described above, such as the conductive contacts 122, 124, etc. For example, in some embodiments, the conductive contacts 348 may be implemented as conductive pads or sockets. Although
Once the die 302 received at 202 is cleaned, the method 200 may proceed with 204, in which an insulating material is deposited over the top surface of the die 302. A die 304, depicted in
At 206, the insulating material is deposited at 204 may be planarized. A die 306, depicted in
At 208, a passivation layer may be deposited over the planarized insulating material. A die 308, depicted in
After the flat surface is formed at the end of 208, the second BEOL layer 340-2 may be seen as including a first sub-layer 341-1 and a second sub-layer 341-2. The first sub-layer 341-1 is a portion of the second BEOL layer 340-2 that includes second conductive pathways 342-2 surrounded by the second insulating material 344-3, while the second sub-layer 341-2 is a portion of the second BEOL layer 340-2 that includes conductive features that were protruding from the surface of the die 302 (e.g., the conductive contacts 348 and conductive traces 352) surrounded by the insulating material 354.
From 208, the method 200 may proceed with 210, which includes forming one or more openings in the passivation layer 356 and the insulating material 354 to selectively expose (i.e., expose as needed) conductive features of the top surface of the die that was received at 202. A die 310, depicted in
The openings 358 formed at 210 may then be used to provide electrical connectivity between selective conductive features of the top surface of the die that was received at 202 (i.e., conductive features that were exposed by the openings 358 at 210) and additional components that may be provided over the top surface of the die 310. To that end, from 210, the method 200 may proceed with any one or more of processes 212, 214, and 216.
At 212, one or more additional BEOL layers may be formed over the top surface of the die resulting from the process 210. A die 312, depicted in
At 214, other active or passive circuitry (e.g., capacitors) may be integrated over the top surface of the die. A die 314, depicted in
Although not specifically shown in the present drawings, in some embodiments, the method 200 may proceed to 214 directly from 210. In such embodiments, the fourth BEOL layer 340-4 with the structure 362 would be formed directly over the openings 358 formed at 210 and at least some of the fourth conductive pathways 342-4 would extend into the openings 358 to electrically connect to some conductive features of the top surface of the die that was received at 202, e.g., to route power, ground, and/or signals to/from these conductive features. However, it may be advantageous to include at least one intermediate BEOL layer (e.g., the third BEOL layer 340-3) between the fourth BEOL layer 340-4 with the structure 362 and the second sub-layer 341-2 of the second BEOL layer 340-2. For example, in some implementations, it may be advantageous in terms of decreasing the congestion of conductive pathways to/from the conductive features of the top surface of the die that was received at 202 and the active or passive circuitry (e.g., the structure 364) provided at 214, which may advantageously reduce power noise effects in the die.
At 216, new top conductive contacts may be formed over the top surface of the die. A die 316, depicted in
A die 318, depicted in
In general, the insulating materials 344 of the BEOL layers 340 starting with the third BEOL layer 340-3 may include any of the insulating materials described for the BEOL layers 340-1 and 340-2; the passivation layers 360, 364, 366 may include any of the materials described for the passivation layers 350 and 354; and the conductive pathways 342 of the BEOL layers 340 starting with the third BEOL layer 340-3 may include any of the conductive materials described for the BEOL layers 340-1 and 340-2. However, the dies 312, 314, 316, 318, and 320 will also exhibit several additional features that are characteristic of the use of the method 200.
One such feature is that, similar to the insulating material 254, the insulating materials 344 of the BEOL layers 340 starting with the third BEOL layer 340-3 may have different (e.g., at least about 2% different or at least about 5% different) stochiometry, density, porosity, compressive vs. tensile stress, or other material characteristics compared to the insulating materials 344-1 and 344-2 even though the same namesake insulating materials may be used.
Another characteristic feature is that, similar to the passivation layer 356, the passivation layers 360, 364, 366 may have different (e.g., at least about 2% different or at least about 5% different) stochiometry, density, porosity, compressive vs. tensile stress, or other material characteristics compared to the passivation layer 350 even though the same namesake insulating materials may be used.
Yet another characteristic feature is that, similar to the conductive pathways 342-1, the conductive pathways 342 of the BEOL layers 340 starting with the third BEOL layer 340-3 be formed of a different metal than the conductive pathways 342-2. Thus, in some implementations of the method 200, a resulting die may include a BEOL layer 340 with conductive pathways 342 of one metal be sandwiched between BEOL layers 340 with conductive pathways 342 of another metal. For example, in some embodiments, the first conductive pathways 342-1 and the third conductive pathways 342-3 may be formed of copper, while the second conductive pathways 342-2 may be formed of aluminum. In this context, additional active or passive circuitry such as the one represented by the structure 362 would normally be implemented below (i.e., closer to the base 332 than) the layer of conductive pathways formed of aluminum, but in the die 314 or the die 316 it would be above (i.e., further away from the base 332 than) the layer of conductive pathways formed of aluminum.
Furthermore, an inset 380, shown in
Still another characteristic feature of the use of the method 200 is that the old conductive contacts, i.e., the conductive contacts 348 that were present on the die 302 received at 202, may be buried below the surface of the dies 312, 314, 316, 318, and 320, covered by the additional materials provided at 212, 214, and 216. A related feature is that the conductive contacts 348 that were present on the die 302 received at 202 may be directly electrically connected to conductive pathways both below and above the second sub-layer 341-2 of the second BEOL layer 340-2. This is drastically different form conventional dies, where conductive contacts are electrically connected to conductive pathways on one side, but to interconnects such as DTD or DTPS interconnects on the other.
The IC dies fabricated using hybrid integration of BEOL layers for disaggregated technologies as disclosed herein, and the microelectronic assemblies 100 with such dies as disclosed herein may be included in any suitable electronic component.
The IC device 1600 may include one or more device layers 1604 disposed on the die substrate 1602. The device layer 1604 may include features of one or more transistors 1640 (e.g., metal oxide semiconductor field-effect transistors (MOSFETs)) formed on the die substrate 1602. The device layer 1604 may include, for example, one or more source and/or drain (S/D) regions 1620, a gate 1622 to control current flow in the transistors 1640 between the S/D regions 1620, and one or more S/D contacts 1624 to route electrical signals to/from the S/D regions 1620. The transistors 1640 may include additional features not depicted for the sake of clarity, such as device isolation regions, gate contacts, and the like. The transistors 1640 are not limited to the type and configuration depicted in
Each transistor 1640 may include a gate 1622 formed of at least two layers, a gate dielectric and a gate electrode. The gate dielectric may include one layer or a stack of layers. The one or more layers may include silicon oxide, silicon dioxide, silicon carbide, and/or a high-k dielectric material. The high-k dielectric material may include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Examples of high-k materials that may be used in the gate dielectric include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. In some embodiments, an annealing process may be carried out on the gate dielectric to improve its quality when a high-k material is used.
The gate electrode may be formed on the gate dielectric and may include at least one p-type work function metal or n-type work function metal, depending on whether the transistor 1640 is to be a p-type metal oxide semiconductor (PMOS) or an n-type metal oxide semiconductor (NMOS) transistor. In some implementations, the gate electrode may consist of a stack of two or more metal layers, where one or more metal layers are work function metal layers and at least one metal layer is a fill metal layer. Further metal layers may be included for other purposes, such as a barrier layer. For a PMOS transistor, metals that may be used for the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, conductive metal oxides (e.g., ruthenium oxide), and any of the metals discussed below with reference to an NMOS transistor (e.g., for work function tuning). For an NMOS transistor, metals that may be used for the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, carbides of these metals (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide), and any of the metals discussed above with reference to a PMOS transistor (e.g., for work function tuning).
In some embodiments, when viewed as a cross-section of the transistor 1640 along the source-channel-drain direction, the gate electrode may consist of a U-shaped structure that includes a bottom portion substantially parallel to the surface of the die substrate 1602 and two sidewall portions that are substantially perpendicular to the top surface of the die substrate 1602. In other embodiments, at least one of the metal layers that form the gate electrode may simply be a planar layer that is substantially parallel to the top surface of the die substrate 1602 and does not include sidewall portions substantially perpendicular to the top surface of the die substrate 1602. In other embodiments, the gate electrode may consist of a combination of U-shaped structures and planar, non-U-shaped structures. For example, the gate electrode may consist of one or more U-shaped metal layers formed atop one or more planar, non-U-shaped layers.
In some embodiments, a pair of sidewall spacers may be formed on opposing sides of the gate stack to bracket the gate stack. The sidewall spacers may be formed from materials such as silicon nitride, silicon oxide, silicon carbide, silicon nitride doped with carbon, and silicon oxynitride. Processes for forming sidewall spacers are well known in the art and generally include deposition and etching process steps. In some embodiments, a plurality of spacer pairs may be used; for instance, two pairs, three pairs, or four pairs of sidewall spacers may be formed on opposing sides of the gate stack.
The S/D regions 1620 may be formed within the die substrate 1602 adjacent to the gate 1622 of each transistor 1640. The S/D regions 1620 may be formed using an implantation/diffusion process or an etching/deposition process, for example. In the former process, dopants such as boron, aluminum, antimony, phosphorous, or arsenic may be ion-implanted into the die substrate 1602 to form the S/D regions 1620. An annealing process that activates the dopants and causes them to diffuse farther into the die substrate 1602 may follow the ion-implantation process. In the latter process, the die substrate 1602 may first be etched to form recesses at the locations of the S/D regions 1620. An epitaxial deposition process may then be carried out to fill the recesses with material that is used to fabricate the S/D regions 1620. In some implementations, the S/D regions 1620 may be fabricated using a silicon alloy such as silicon germanium or silicon carbide. In some embodiments, the epitaxially deposited silicon alloy may be doped in situ with dopants such as boron, arsenic, or phosphorous. In some embodiments, the S/D regions 1620 may be formed using one or more alternate semiconductor materials such as germanium or a group Ill-V material or alloy. In further embodiments, one or more layers of metal and/or metal alloys may be used to form the S/D regions 1620.
Electrical signals, such as power and/or input/output (I/O) signals, may be routed to and/or from the devices (e.g., transistors 1640) of the device layer 1604 through one or more interconnect layers disposed on the device layer 1604 (illustrated in
The interconnect structures 1628 may be arranged within the interconnect layers 1606-1610 to route electrical signals according to a wide variety of designs; in particular, the arrangement is not limited to the particular configuration of interconnect structures 1628 depicted in
In some embodiments, the interconnect structures 1628 may include lines 1628a and/or vias 1628b filled with an electrically conductive material such as a metal. The lines 1628a may be arranged to route electrical signals in a direction of a plane that is substantially parallel with a surface of the die substrate 1602 upon which the device layer 1604 is formed. For example, the lines 1628a may route electrical signals in a direction in and out of the page from the perspective of
The interconnect layers 1606-1610 may include a dielectric material 1626 disposed between the interconnect structures 1628, as shown in
A first interconnect layer 1606 (referred to as Metal 1 or “M1”) may be formed directly on the device layer 1604. In some embodiments, the first interconnect layer 1606 may include lines 1628a and/or vias 1628b, as shown. The lines 1628a of the first interconnect layer 1606 may be coupled with contacts (e.g., the S/D contacts 1624) of the device layer 1604.
A second interconnect layer 1608 (referred to as Metal 2 or “M2”) may be formed directly on the first interconnect layer 1606. In some embodiments, the second interconnect layer 1608 may include vias 1628b to couple the lines 1628a of the second interconnect layer 1608 with the lines 1628a of the first interconnect layer 1606. Although the lines 1628a and the vias 1628b are structurally delineated with a line within each interconnect layer (e.g., within the second interconnect layer 1608) for the sake of clarity, the lines 1628a and the vias 1628b may be structurally and/or materially contiguous (e.g., simultaneously filled during a dual Damascene process) in some embodiments.
A third interconnect layer 1610 (referred to as Metal 3 or “M3”) (and additional interconnect layers, as desired) may be formed in succession on the second interconnect layer 1608 according to similar techniques and configurations described in connection with the second interconnect layer 1608 or the first interconnect layer 1606. In some embodiments, the interconnect layers that are “higher up” in the metallization stack 1619 in the IC device 1600 (i.e., farther away from the device layer 1604) may be thicker.
The IC device 1600 may include a solder resist material 1634 (e.g., polyimide or similar material) and one or more conductive contacts 1636 formed on the interconnect layers 1606-1610. In
In some embodiments in which the IC device 1600 is a double-sided die (e.g., like the die 114-1), the IC device 1600 may include another metallization stack (not shown) on the opposite side of the device layer(s) 1604. This metallization stack may include multiple interconnect layers as discussed above with reference to the interconnect layers 1606-1610, to provide conductive pathways (e.g., including conductive lines and vias) between the device layer(s) 1604 and additional conductive contacts (not shown) on the opposite side of the IC device 1600 from the conductive contacts 1636. These additional conductive contacts may serve as the conductive contacts 122 or 124, as appropriate.
In other embodiments in which the IC device 1600 is a double-sided die (e.g., like the die 114-1), the IC device 1600 may include one or more TSVs through the die substrate 1602; these TSVs may make contact with the device layer(s) 1604, and may provide conductive pathways between the device layer(s) 1604 and additional conductive contacts (not shown) on the opposite side of the IC device 1600 from the conductive contacts 1636. These additional conductive contacts may serve as the conductive contacts 122 or 124, as appropriate.
In some embodiments, the circuit board 1702 may be a PCB including multiple metal layers separated from one another by layers of dielectric material and interconnected by electrically conductive vias. Any one or more of the metal layers may be formed in a desired circuit pattern to route electrical signals (optionally in conjunction with other metal layers) between the components coupled to the circuit board 1702. In other embodiments, the circuit board 1702 may be a non-PCB substrate. In some embodiments the circuit board 1702 may be, for example, the circuit board 133.
The IC device assembly 1700 illustrated in
The package-on-interposer structure 1736 may include an IC package 1720 coupled to an interposer 1704 by coupling components 1718. The coupling components 1718 may take any suitable form for the application, such as the forms discussed above with reference to the coupling components 1716. Although a single IC package 1720 is shown in
In some embodiments, the interposer 1704 may be formed as a PCB, including multiple metal layers separated from one another by layers of dielectric material and interconnected by electrically conductive vias. In some embodiments, the interposer 1704 may be formed of an epoxy resin, a fiberglass-reinforced epoxy resin, an epoxy resin with inorganic fillers, a ceramic material, or a polymer material such as polyimide. In some embodiments, the interposer 1704 may be formed of alternate rigid or flexible materials that may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other group Ill-V and group IV materials. The interposer 1704 may include metal interconnects 1708 and vias 1710, including but not limited to TSVs 1706. The interposer 1704 may further include embedded devices 1714, including both passive and active devices. Such devices may include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices. More complex devices such as RF devices, power amplifiers, power management devices, antennas, arrays, sensors, and microelectromechanical systems (MEMS) devices may also be formed on the interposer 1704. The package-on-interposer structure 1736 may take the form of any of the package-on-interposer structures known in the art.
The IC device assembly 1700 may include an IC package 1724 coupled to the first face 1740 of the circuit board 1702 by coupling components 1722. The coupling components 1722 may take the form of any of the embodiments discussed above with reference to the coupling components 1716, and the IC package 1724 may take the form of any of the embodiments discussed above with reference to the IC package 1720.
The IC device assembly 1700 illustrated in
Additionally, in various embodiments, the electrical device 1800 may not include one or more of the components illustrated in
The electrical device 1800 may include a processing device 1802 (e.g., one or more processing devices). As used herein, the term “processing device” or “processor” may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory. The processing device 1802 may include one or more digital signal processors (DSPs), application-specific integrated circuits (ASICs), central processing units (CPUs), graphics processing units (GPUs), cryptoprocessors (specialized processors that execute cryptographic algorithms within hardware), server processors, or any other suitable processing devices. The electrical device 1800 may include a memory 1804, which may itself include one or more memory devices such as volatile memory (e.g., dynamic RAM (DRAM)), nonvolatile memory (e.g., read-only memory (ROM)), flash memory, solid state memory, and/or a hard drive. In some embodiments, the memory 1804 may include memory that shares a die with the processing device 1802. This memory may be used as cache memory and may include embedded dynamic RAM or spin transfer torque magnetic RAM (STT-MRAM).
In some embodiments, the electrical device 1800 may include a communication chip 1812 (e.g., one or more communication chips). For example, the communication chip 1812 may be configured for managing wireless communications for the transfer of data to and from the electrical device 1800. The term “wireless” and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a nonsolid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not.
The communication chip 1812 may implement any of a number of wireless standards or protocols, including but not limited to Institute for Electrical and Electronic Engineers (IEEE) standards including Wi-Fi (IEEE 802.11 family), IEEE 802.16 standards (e.g., IEEE 802.16-2005 Amendment), Long-Term Evolution (LTE) project along with any amendments, updates, and/or revisions (e.g., advanced LTE project, ultra-mobile broadband (UMB) project (also referred to as “3GPP2”), etc.). IEEE 802.16 compatible Broadband Wireless Access (BWA) networks are generally referred to as WiMAX networks, an acronym that stands for Worldwide Interoperability for Microwave Access, which is a certification mark for products that pass conformity and interoperability tests for the IEEE 802.16 standards. The communication chip 1812 may operate in accordance with a Global System for Mobile Communication (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE network. The communication chip 1812 may operate in accordance with Enhanced Data for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). The communication chip 1812 may operate in accordance with Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution-Data Optimized (EV-DO), and derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The communication chip 1812 may operate in accordance with other wireless protocols in other embodiments. The electrical device 1800 may include an antenna 1822 to facilitate wireless communications and/or to receive other wireless communications (such as AM or FM radio transmissions).
In some embodiments, the communication chip 1812 may manage wired communications, such as electrical, optical, or any other suitable communication protocols (e.g., the Ethernet). As noted above, the communication chip 1812 may include multiple communication chips. For instance, a first communication chip 1812 may be dedicated to shorter-range wireless communications such as Wi-Fi or Bluetooth, and a second communication chip 1812 may be dedicated to longer-range wireless communications such as global positioning system (GPS), EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, or others. In some embodiments, a first communication chip 1812 may be dedicated to wireless communications, and a second communication chip 1812 may be dedicated to wired communications.
The electrical device 1800 may include battery/power circuitry 1814. The battery/power circuitry 1814 may include one or more energy storage devices (e.g., batteries or capacitors) and/or circuitry for coupling components of the electrical device 1800 to an energy source separate from the electrical device 1800 (e.g., AC line power).
The electrical device 1800 may include a display device 1806 (or corresponding interface circuitry, as discussed above). The display device 1806 may include any visual indicators, such as a heads-up display, a computer monitor, a projector, a touchscreen display, a liquid crystal display (LCD), a light-emitting diode display, or a flat panel display.
The electrical device 1800 may include an audio output device 1808 (or corresponding interface circuitry, as discussed above). The audio output device 1808 may include any device that generates an audible indicator, such as speakers, headsets, or earbuds.
The electrical device 1800 may include an audio input device 1824 (or corresponding interface circuitry, as discussed above). The audio input device 1824 may include any device that generates a signal representative of a sound, such as microphones, microphone arrays, or digital instruments (e.g., instruments having a musical instrument digital interface (MIDI) output).
The electrical device 1800 may include a GPS device 1818 (or corresponding interface circuitry, as discussed above). The GPS device 1818 may be in communication with a satellite-based system and may receive a location of the electrical device 1800, as known in the art.
The electrical device 1800 may include an other output device 1810 (or corresponding interface circuitry, as discussed above). Examples of the other output device 1810 may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or an additional storage device.
The electrical device 1800 may include an other input device 1820 (or corresponding interface circuitry, as discussed above). Examples of the other input device 1820 may include an accelerometer, a gyroscope, a compass, an image capture device, a keyboard, a cursor control device such as a mouse, a stylus, a touchpad, a bar code reader, a Quick Response (QR) code reader, any sensor, or a radio frequency identification (RFID) reader.
The electrical device 1800 may have any desired form factor, such as a handheld or mobile electrical device (e.g., a cell phone, a smart phone, a mobile internet device, a music player, a tablet computer, a laptop computer, a netbook computer, an ultrabook computer, a personal digital assistant (PDA), an ultra-mobile personal computer, etc.), a desktop electrical device, a server or other networked computing component, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a vehicle control unit, a digital camera, a digital video recorder, or a wearable electrical device. In some embodiments, the electrical device 1800 may be any other electronic device that processes data.
The following paragraphs provide various examples of the embodiments disclosed herein.
Example 1 provides an IC die that includes: a base; a FEOL layer over the base, the FEOL layer including active or passive circuitry (e.g., transistors, diodes, resistors, inductors, and capacitors, among others); a first BEOL layer including first conductive pathways (e.g., conductive traces and/or conductive vias); a second BEOL layer including second conductive pathways; and a third BEOL layer including third conductive pathways, where the first BEOL layer is between the FEOL layer and the second BEOL layer, the second BEOL layer is between the first BEOL layer and the third BEOL layer, and an electrically conductive fill material of the second conductive pathways is different from an electrically conductive fill material of the first conductive pathways and from an electrically conductive fill material of the third conductive pathways.
Example 2 provides the IC die according to example 1, where the electrically conductive fill material of the second conductive pathways includes aluminum, and where at least one of the electrically conductive fill material of the first conductive pathways or the electrically conductive fill material of the third conductive pathways includes copper.
Example 3 provides the IC die according to any one of examples 1-2, where the second BEOL layer includes a first sub-layer and a second sub-layer, the first sub-layer is between the FEOL layer and the second sub-layer and includes a first subset of the second conductive pathways separated from one another by a first insulator material, the second sub-layer is between the first sub-layer and the third BEOL layer and includes a second subset of the second conductive pathways separated from one another by a second insulator material, and the second insulator material and the first insulator material have different material compositions.
Example 4 provides the IC die according to example 3, where a portion of the second insulator material is above the second subset of the second conductive pathways, and at least one of the third conductive pathways extends through the portion of the second insulator material that is above the second subset of the second conductive pathways and contacts at least one of the second subset of the second conductive pathways.
Example 5 provides the IC die according to example 4, further including an intermediate layer over the second subset of second conductive pathways, where the at least one of the third conductive pathways extends through the intermediate layer.
Example 6 provides the IC die according to example 5, the intermediate layer is between the second subset of the second conductive pathways and the portion of the second insulator material that is above the second subset of the second conductive pathways.
Example 7 provides the IC die according to any one of examples 5-6, where the intermediate layer is further at an interface between the first insulator material and the second insulator material.
Example 8 provides the IC die according to any one of examples 5-7, where the third conductive pathways are separated from one another by a third insulator material, the intermediate layer is a first intermediate layer, and the IC die further includes a second intermediate layer at an interface between the second insulator material and the third insulator material.
Example 9 provides the IC die according to example 8, where the at least one of the third conductive pathways extends through the second intermediate layer.
Example 10 provides the IC die according to any one of examples 1-9, further including one or more capacitors in the third BEOL layer.
Example 11 provides the IC die according to any one of examples 1-10, where at least some of the first conductive pathways include a liner and an electrically conductive fill material, at least some of the third conductive pathways include a liner and an electrically conductive fill material, and a material composition of the liner of the first conductive pathways is different from a material composition of the liner of the third conductive pathways.
Example 12 provides the IC die according to example 11, where a thickness of the liner of the first conductive pathways is different from a thickness of the liner of the third conductive pathways, e.g., at least about 5% different, at least about 10% different, or at least 5-50% different.
Example 13 provides the IC die according to examples 11 or 12, where a material composition of the electrically conductive fill material of the first conductive pathways is different from a material composition of the electrically conductive fill material of the third conductive pathways. For example, the electrically conductive fill material of the first conductive pathways may include copper (Cu), while the electrically conductive fill material of the third conductive pathways may include tungsten (W), aluminum (Al), ruthenium (Ru), cobalt (Co), or AlCu (e.g., in proportions of between 1:1 to 1:100).
Example 14 provides the IC die according to any one of examples 1-13, where the second BEOL layer further includes a conductive pad.
Example 15 provides the IC die according to example 14, where the conductive pad has a first face and a second face, the first face is closer to the base than the second face, one of the second conductive pathways is electrically connected to the first face of the conductive pad, and one of the third conductive pathways is electrically connected to the second face of the conductive pad.
Example 16 provides an IC die that includes a device layer, including active or passive circuitry (e.g., transistors, diodes, resistors, inductors, and capacitors, among others); a first metallization layer over the device layer, the first metallization layer including a first insulator material having a first face and a second face opposite the first face, and further including first conductive pathways (e.g., conductive traces and/or conductive vias) in the first insulator material, where the first face is closer to the device layer than the second face; a layer including conductive contacts at the second face of the metallization layer; and a second metallization layer including second conductive pathways (e.g., conductive traces and/or conductive vias), where the layer is between the first metallization layer and the second metallization layer.
Example 17 provides the IC die according to example 16, where the conductive contacts include conductive pads.
Example 18 provides the IC die according to examples 16 or 17, where at least one of the conductive contacts is electrically connected to one of the first conductive pathways on one side of the at least one of the conductive contacts and is electrically connected to one of the second conductive pathways on another side of the at least one of the conductive contacts.
Example 19 provides the IC die according to any one of examples 16-18, where at least one of the conductive contacts is electrically connected to one of the first conductive pathways on one side of the at least one of the conductive contacts and is not electrically connected to any further pathways above the second face of the first metallization layer.
Example 20 provides an IC die that includes a device layer, including active or passive circuitry (e.g., transistors, diodes, resistors, inductors, and capacitors, among others); a first metallization layer over the device layer, the first metallization layer including a first insulator material and first conductive pathways (e.g., conductive traces and/or conductive vias) in the first insulator material; a second metallization layer over the device layer, the second metallization layer including a second insulator material and second conductive pathways (e.g., conductive traces and/or conductive vias) in the second insulator material; and conductive contacts buried in a layer of a third insulator material between the first metallization layer and the second metallization layer.
Example 21 provides the IC die according to example 20, where at least one of the conductive contacts is electrically connected to one of the first conductive pathways on one side of the at least one of the conductive contacts and is electrically connected to one of the second conductive pathways on another side of the at least one of the conductive contacts.
Example 22 provides an IC package that includes an IC die including an IC die according to any one of examples 1-21; and a further IC component, coupled to the IC die.
Example 23 provides the IC package according to example 22, where the further IC component includes a package substrate.
Example 24 provides the IC package according to example 22, where the further IC component includes an interposer.
Example 25 provides the IC package according to example 22, where the further IC component includes a further IC die.
Example 26 provides a computing device that includes a carrier substrate and an IC die coupled to the carrier substrate, where the IC die is an IC die according to any one of examples 1-21, or the IC die is included in the IC package according to any one of examples 22-25.
Example 27 provides the computing device according to example 26, where the computing device is a wearable or handheld computing device.
Example 28 provides the computing device according to examples 26 or 27, where the computing device further includes one or more communication chips.
Example 29 provides the computing device according to any one of examples 26-28, where the computing device further includes an antenna.
Example 30 provides the computing device according to any one of examples 26-29, where the carrier substrate is a motherboard.
Example 31 provides the IC die according to any one of examples 1-21, where the IC die includes or is a part of a central processing unit.
Example 32 provides the IC die according to any one of examples 1-31, where the IC die includes or is a part of a memory device.
Example 33 provides the IC die according to any one of examples 1-32, where the IC die includes or is a part of a logic circuit.
Example 34 provides the IC die according to any one of examples 1-33, where the IC die includes or is a part of input/output circuitry.
Example 35 provides the IC die according to any one of examples 1-34, where the IC die includes or is a part of a field programmable gate array transceiver.
Example 36 provides the IC die according to any one of examples 1-35, where the IC die includes or is a part of a field programmable gate array logic.
Example 37 provides the IC die according to any one of examples 1-36, where the IC die includes or is a part of a power delivery circuitry.
Example 38 provides the IC die according to any one of examples 1-37, where the IC die includes or is a part of a Ill-V amplifier.
Example 39 provides the IC die according to any one of examples 1-38, where the IC die includes or is a part of Peripheral Component Interconnect Express circuitry or Double Data Rate transfer circuitry.
