Patent Application
20250046621
This description relates to forming integrated circuit (IC) packages with immersion tin on a flank of leads.
There are different integrated circuit (IC) package types available on the market that include conductive leads on the underside of the IC package for solder joints. Because the leads are not easily viewed or exposed, it is difficult to determine whether the IC package has been successfully soldered on to a printed circuit board (PCB). A wettable flank design exposes the leads at the sidewalls of the IC package which enables optical inspection of the soldering. However, the exposed leads are prone to oxidation and corrosion, making sidewall solder wetting difficult and reducing the shelf-life of the IC package.
A first example is related to a method for forming integrated circuit (IC) packages. The method includes mounting tape on a mold compound of a strip of flat no-leads IC packages. The method also includes sawing the mold compound of the strip of flat no-leads IC packages to form singulated IC packages mounted on the tape. The method further includes immersing the singulated IC packages in a bath of immersion tin to form immersion tin plating on a flank of leads of the singulated IC packages.
A second example relates to an IC package. The IC package includes a die mounted on a flat no-leads interconnect and a mold compound encapsulating the die on a top side of the flat no-leads interconnect. A flank of leads of the flat no-leads interconnect has an immersion tin plating that is greater than 2 micrometers thick.
This description relates to forming integrated circuit (IC) packages. Many IC packages include an interconnect (alternatively referred to as a leadframe) onto which one or more dies containing semiconductor devices are mounted and electrically attached. The interconnect(s) and die(s) are encapsulated within a mold compound forming a housing around the interconnect(s) and die(s). The interconnect(s) include a plurality of electrical contacts or leads that are exposed to an external environment to enable the device(s) within the housing to be electrically coupled with one or more other electrical components external to the housing.
Interconnect(s) with wettable flanks for IC packages, such as quad-flat no-leads (QFN) and dual-flat no-leads (DFN), do not have leads protruding from the housing. Instead, wettable flanks refer to non-protruding leads or contact lands of an interconnect. The wettable flanks are manufactured in a manner that promotes wetting of solder to the leads when mounted to a PCB. Wettable flanks enable the formation of a solder fillet that is able to be visually inspected (e.g., via automated optical inspection (AOI)) to verify an acceptable solder joint was formed between the lead and the PCB. Wetting is achieved by coating or plating the conductive material, such as copper, of the interconnect with a solderable metal that is different than the conductive material and offers increased wettability for solder (e.g., exhibits increased solderability). Example metals that have high degrees of solderability include nickel, palladium, tin, and gold.
In some examples, flat no-leads IC packages are fabricated in strips. During a singulation process, individual IC packages are cut from the strips by cutting through the interconnect to expose the internal copper material of the interconnect at the sidewall of the individual IC packages. At such locations, the exposed copper surface of the interconnect is a wettable flank that can be visually inspected but is subject to corrosion.
In the devices and methods described herein, the wettable flank is plated with an immersion tin plating that mitigates corrosion and protects the leads of the interconnects. The immersion tin plating is applied in an immersion tin bath that results in an immersion tin plating with a thickness greater than 2 micrometers on the wettable flank. The thickness of the immersion tin plating increases the shelf-life and reliability of the flat no-leads IC packages.
The components described with respect to one unsingulated flat no-leads IC packages, such as the first unsingulated flat no-leads IC package 102, are present in other unsingulated flat no-leads IC packages, such as the second unsingulated flat no-leads IC package 104 and the third unsingulated flat no-leads IC package 106, of the strip 100 and operate in a similar manner. For clarity, reference numbers identify components with respect to one unsingulated flat no-leads IC package. The strip 100 is an array of unsingulated flat no-leads IC packages that extend in a longitudinal direction and are coupled to each other by the mold compound 108. While a single row of flat no-leads IC packages extending in a longitudinal direction is described for clarity, in other examples, the strip 100 includes a plurality of rows flat no-leads IC packages.
The flat no-leads IC packages 102, 104, 106 are formed with interconnects of a conductive material and are associated with corresponding leads 110 formed of the conductive material. For example, the leads 110 of the flat no-leads interconnect are formed with copper. A first side 112 of the leads 110 is approximately flush with the mold compound 108 at a first surface 114 of the strip 100. The first surface 114 of the strip 100 refers to the surface that faces a PCB when a corresponding no-leads IC packages of the strip 100 is mounted (e.g., soldered) to the PCB. Stated differently, the first side of the leads 110 does not extend beyond the first surface 114 of the strip 100 in a lateral direction approximately orthogonal to the longitudinal direction.
The first side 112 of the leads 110 is coated with solderable metal layer 116 that extends past the first surface 114 of the strip 100 in the lateral direction. The solderable metal layer 116 provides a protective coating that prevents oxidation at the first side 112 of the leads 110. The solderable metal layer 116 is formed of a solderable metal material. Examples of the solderable metal material include various forms of nickel, palladium, tin, gold, etc. In the illustrated example, the leads 110 are formed of the conductive material, here copper (Cu), and the solderable metal layer 116 is formed of a solderable material, here matte tin (Sn). The solderable metal layer 116 is formed by applying the solderable metal material to the first side 112 of the leads 110 in a deposition process, such as electroplating that utilizes an electric current. The solderable metal layer 116 does not extend in the longitudinal direction over the mold compound 108.
The singulation process utilizes a severing tool 308. For example, the severing tool 308 is a saw that includes a saw blade 310 configured to scribe, saw or dice through a height of the strip 100 in the lateral direction. The saw blade 310 travels a path from the first surface 114 to the second surface 204 through the strip 100 to the tape 202 without severing the tape 202. Because the singulation process does not sever the tape 202, the first singulated flat no-leads IC package 302, the second singulated flat no-leads IC package 304, and the third singulated flat no-leads IC package 306 remain supported by the strip 100 due to adhesion to the tape 202. In other examples, the severing tool 308 is laser-based or plasma-based.
The first singulated flat no-leads IC package 302, the second singulated flat no-leads IC package 304, and the third singulated flat no-leads IC package 306 are spaced apart from one another by trenches 312. The trenches 312 are voids that extend toward the second surface 204. By virtue of the singulation, the trenches 312 expose the copper leads 110 at sidewall surfaces 314 forming wettable flanks. Therefore, the bottom and the flank of the leads 110 are exposed.
The depth of the trenches 312 is defined in the lateral direction and varies depending on whether a solderable metal layer 116 is present on the first surface 114. For example, where the solderable metal layer 116 is present, the depth of the trench 312 extends from the third surface 318 to the second surface 204 of the strip 100. Where the solderable metal layer 116 is not present, the depth of the trench 312 extends from the first surface 114 to the second surface 204. Accordingly, the depth of the trenches 312 varies.
In some examples, the width of the trenches 312, defined in the longitudinal direction, is based on a predetermined separation distance between adjacent singulated flat no-leads IC packages. For example, the predetermined distance is set to greater than ten micrometers. In another example, the width of the trenches 312 is based on a profile of the severing tool 308 and/or the saw blade 310. In some examples, the width of the trenches 312 is variable having a first width at a first depth and a second width at a second depth. The first width and the second width satisfy the predetermined distance. Continuing the example from above, the first width may be greater or less than the second width, but both the first width and the second width are greater than ten micrometers.
The trenches 312 define sidewall surfaces 314 of the singulated flat no-leads IC packages 302, 304, 306. The sidewall surfaces 314 are approximately orthogonal to the first surface 114 and the second surface 204. The singulated flat no-leads IC packages 302, 304, 306 have corresponding leads 110 and solderable metal layers 116. As a result of the singulation process, a second side 316 of the leads 110 is exposed at the sidewall surfaces 314 of the singulated flat no-leads IC packages 302, 304, 306 thereby forming wettable flanks. In one example, the second side 316 of the leads 110 is approximately flush with the sidewall surfaces 314. In the illustrated example, the exposed second side 316 extends approximately orthogonally from the first side 112 of the leads 110. The second side 316 of the leads 110 extends from the first side 112 to a third side 320 of the leads 110. The third side 320 is opposite the first side 112 and proximate to the second surface 204. As one example, the solderable metal layer 116 is approximately twelve micrometers thick extending from the first side 112 to a third surface 318 in the lateral direction.
In some examples, the immersion tin bath 402 includes a shock generator and/or a vibrator. The shock generator is configured to apply a shock to the immersion tin bath 402 to release air bubbles in the immersion plating material. The vibrator is configured to apply vibration to the immersion tin bath 402 and or the strip 100 to loosen byproducts of the chemical reaction.
At 604, a first rinsing cycle is performed to remove the cleaning agent from the strip 100. The first rinsing cycle includes a number of rinsing operations. For example, the strip 100 undergoes a first rinse operation, a second rinse operation, and a third rinse operation. In one example, the rinsing operations are performed for one to ten minutes at approximately 20 degrees Celsius.
At 606, an etching process is performed to remove oxidation or defects by etching the exposed conductive material, here the copper interconnects, in particular, the second side of the leads 110. For example, the etching process includes applying an etching agent to the second side 316 of the leads 110. The etching agent removes burs in the second side 316 of the leads 110 caused by the singulation process or oxidation resulting from the conductive material at the second side 316 being exposed to the environment. The etching agent is, for example, STANNA-Q PROTECT. In one example, the etching process removes approximately 6 micrometers of the second side 316 of the leads 110. As one example, the etching process is performed for one to eleven minutes at 15 to 35 degrees Celsius.
At 608, a second rinsing cycle is performed to remove the etching agent. In some examples, the rinsing cycles are standardized. For example, the strip 100 undergoes a first rinse operation, a second rinse operation, and a third rinse operation performed for one to ten minutes at approximately 20 degrees Celsius during the second rinsing cycle similar to the first rinsing cycle.
At 610, in an activation process, the strip 100 is dipped in an activation chemical to prepare the second side 316 of the leads 110 for the immersion tin bath. The activation chemical is, for example, STANNA-Q DIP.
At 612, immersion of the strip 100 in an immersion bath of the immersion tin bath 402 is performed. In particular, the second side 316 of the leads 110 is submerged in the immersion tin bath. For example, at a first time in the immersion tin bath 402, the second side 316 of the leads 110 makes contact with the immersion tin bath at a depth corresponding to the first side 112 of the leads 110. At a second time after the first time in the immersion tin bath 402, the second side 316 of the leads 110 makes contact with immersion tin bath at a depth corresponding to the third side 320 of the leads 110. The immersion tin bath is, for example, STANNA-Q2. As one example, the immersion of the strip 100 is performed for 150 minutes to 4 hours at a temperature of 50 to 90 degrees Celsius.
In one example, the immersion tin bath 402 includes shocking the immersion tin bath in response to immersing the strip 100 in the immersion tin bath. Additionally or alternatively, the immersion tin bath 402 includes vibrating the immersion tin bath when the strip 100 is submerged.
At 614, a third rinsing cycle is performed. For example, the strip 100 undergoes a first rinse operation, a second rinse operation, and a third rinse operation performed for one to ten minutes at approximately 20 degrees Celsius during the third rinsing cycle. The rinsing cycles are performed before and after the immersion tin bath.
At 616, the strip 100 is dipped in first dip chemical to prepare the strip 100 for a second dip chemical in a first post-dip process. The first dip chemical is, for example, IONIX SF 8. As one example, the first post-dip process is performed for 30 seconds to 2 minutes at 40 to 60 degrees Celsius.
At 618, a fourth rinsing cycle is performed. For example, the strip 100 undergoes a first rinse operation, a second rinse operation, and a third rinse operation performed for one to ten minutes at approximately 20 degrees Celsius during the fourth rinsing cycle.
At 620, the strip 100 is dipped in the second dip chemical to prepare the strip 100 for a third dip chemical in a second post-dip process. The second dip chemical is, for example, PROTECTOSTAN PLUS 2. As one example, the second post-dip process is performed for 15 seconds to 1 minute at approximately 20 degrees Celsius.
At 622, a fifth rinsing cycle is performed. For example, the strip 100 undergoes a first rinse operation, a second rinse operation, and a third rinse operation performed for one to ten minutes at approximately 20 degrees Celsius during the fifth rinsing cycle.
At 624, the strip 100 is dipped in a third dip chemical that forms an anti-tarnish layer on the immersion tin plating 502 in a third post-dip process. In one example, the first dip chemical is the same as the third dip chemical. The third dip chemical is, for example, IONIX SF 8. The anti-tarnish layer protects the immersion tin plating 502. As one example, the third post-dip process is performed for 15 seconds to 1 minute at 20 to 60 degrees Celsius.
At 626, a sixth rinsing cycle is performed. For example, the strip 100 undergoes a first rinse operation, a second rinse operation, and a third rinse operation performed for one to ten minutes at approximately 20 degrees Celsius during the sixth rinsing cycle.
At 628, a hot rinse is performed to rinse the strip 100. For example, the hot rinse is performed for one to ten minutes at approximately 60 degrees Celsius. At 630, air is applied to the strip 100 and at 632, a drying process is performed.
A solderable metal layer 712 is applied to a first side of the leads 710. The solderable metal layer 712 is employable to implement the solderable metal layer 116 of
At 804, a first side of the leads is coated with a solderable metal material, such as matte tin, to form the solderable material layer (e.g., the solderable metal layer 116 of
At 806, an anneal process is performed to heat the solderable material layer of the strip to approximately 150 degrees Celsius for about one hour. The anneal process reduces whiskering by releasing residual stress of the solderable material layer.
At 808, the strip 100 is applied to tape. At 810, a singulation process is performed that separates the flat no-leads IC packages from a strip, such as the strip 100 of
At 812, the second side of the leads is coated in an immersion plating material with an immersion tin bath 402 described with respect to
At 814, a strip test is performed on the singulated flat no-leads IC package. For example, the singulated flat no-leads IC packages, such as the first singulated flat no-leads IC package 302, the second singulated flat no-leads IC package 304, and the third singulated flat no-leads IC package 306 are tested in parallel.
At 816, a curing process is performed to release the singulated flat no-leads IC packages from the tape. As one example, the tape is an ultraviolet (UV) curable tape that when exposed to UV radiation in the curing process. At 818, a test and reel process is performed. Responsive to the curing, the adhesive of the tape is rendered ineffective. Accordingly, after the curing process, the singulated flat no-leads IC packages are removed from the tape and are packaged.
At 902, a cleaning process is performed. In the cleaning process, a cleaning agent is applied to the strip. For example, the cleaning process includes applying the cleaning agent to the wettable flanks formed by the exposed leads. As one example, the cleaning agent etches exposed copper of the copper interconnects that form the exposed leads.
At 904, a first rinsing cycle is performed after the etching to remove the cleaning agent from the strip.
At 906, a protectant is applied to the wettable flanks to protect exposed copper of the leads at a second side of an IC package from oxidation or defects.
At 908, a second rinsing cycle is performed to remove the protectant from the second side of the leads. At 910, the strip undergoes a preparation dip and is dipped in an activation chemical to prepare the second side of the leads for the immersion tin bath, such as the immersion tin bath 402 of
At 912, the strip is immersed in an immersion tin bath. In particular, the immersion includes dipping the singulated IC packages in the bath of immersion tin such that the etched exposed copper is submerged in the immersion tin. The second side of the leads is submerged in the immersion tin bath to form an immersion tin plating (e.g., immersion tin plating 502 of
The plating material is reduced over time due to an oxidation-reduction reaction between the interconnect material and the plating material until the plating material is unable to protect the interconnect material. The thicker the plating material, the longer the plating material protects the interconnect material thereby increasing the shelf-life of the corresponding flat no-leads IC package. The devices and methods described herein provide thicker immersion plating on the wettable flank of the flat no-leads IC package, which increases the shelf-life and reliability of the flat no-leads IC package.
At 914, a third rinsing cycle is performed.
At 916, the strip undergoes a first dip process and is dipped in a first dip chemical to prepare the strip for a second dip chemical in a first post-dip process. At 918, a fourth rinsing cycle is performed. At 920, the strip undergoes a second post dip process and is dipped in the second dip chemical to prepare the strip for a third dip chemical. At 922, a fifth rinsing cycle is performed.
At 924, the strip undergoes a third dip process and is dipped in third dip chemical that forms an anti-tarnish layer on the immersion tin plating. At 926, a sixth rinsing cycle is performed. At 928, a hot rinse is performed to rinse the strip. At 930, air is applied to the strip and at 932, a drying process is performed.
In this description, unless otherwise stated, “about,” “approximately” or “substantially” preceding a parameter means being within +/−10 percent of that parameter. Modifications are possible in the described embodiments, and other embodiments are possible, within the scope of the claims.
