Patent Application
20230253288
The integrated circuit industry is continually striving to produce ever faster, smaller, and thinner integrated circuit devices and packages for use in various electronic products, including, but not limited to, computer servers and portable products, such as portable computers, electronic tablets, cellular phones, digital cameras, and the like.
As these goals are achieved, the integrated circuit devices become smaller. Accordingly, the density of power consumption of electronic components within the integrated circuit devices has increased, which, in turn, increases the average junction temperature of the integrated circuit device. If the temperature of the integrated circuit device becomes too high, the integrated circuits may be damaged or destroyed. Thus, heat dissipation devices are used to remove heat from the integrated circuit devices in an integrated circuit package. In one example, heat spreading and dissipation devices may be thermally attached to integrated circuit devices for heat removal. The heat spreading and dissipation devices, in turn, dissipate the heat into the surrounding atmosphere. In another example, a liquid cooling device, such as a heat exchanger or a heat pipe, may be thermally attached to integrated circuit devices for heat removal. However, as power densities and power envelopes increase to reach peak performance, these methods are becoming ineffective in removing sufficient amounts of heat.
One emerging heat removal technique is two-phase immersion cooling. This technique includes immersing an integrated circuit assembly into a liquid cooling bath containing a low boiling point liquid which vaporizes and, thus, cools the integrated circuit assembly through latent heat transfer, as it generates heat. Although it is a promising technology, two-phase immersion cooling has various challenges to effective operation, as will be understood to those skilled in the art.
The subject matter of the present disclosure is particularly pointed out and distinctly claimed in the concluding portion of the specification. The foregoing and other features of the present disclosure will become more fully apparent from the following description and appended claims, taken in conjunction with the accompanying drawings. It is understood that the accompanying drawings depict only several embodiments in accordance with the present disclosure and are, therefore, not to be considered limiting of its scope. The disclosure will be described with additional specificity and detail through use of the accompanying drawings, such that the advantages of the present disclosure can be more readily ascertained, in which:
In the following detailed description, reference is made to the accompanying drawings that show, by way of illustration, specific embodiments in which the claimed subject matter may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the subject matter. It is to be understood that the various embodiments, although different, are not necessarily mutually exclusive. For example, a particular feature, structure, or characteristic described herein, in connection with one embodiment, may be implemented within other embodiments without departing from the spirit and scope of the claimed subject matter. References within this specification to “one embodiment” or “an embodiment” mean that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one implementation encompassed within the present description. Therefore, the use of the phrase “one embodiment” or “in an embodiment” does not necessarily refer to the same embodiment. In addition, it is to be understood that the location or arrangement of individual elements within each disclosed embodiment may be modified without departing from the spirit and scope of the claimed subject matter. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the subject matter is defined only by the appended claims, appropriately interpreted, along with the full range of equivalents to which the appended claims are entitled. In the drawings, like numerals refer to the same or similar elements or functionality throughout the several views, and that elements depicted therein are not necessarily to scale with one another, rather individual elements may be enlarged or reduced in order to more easily comprehend the elements in the context of the present description.
The terms “over,” “to,” “between,” and “on” as used herein may refer to a relative position of one layer with respect to other layers. One layer “over” or “on” another layer or bonded “to” another layer may be directly in contact with the other layer or may have one or more intervening layers. One layer “between” layers may be directly in contact with the layers or may have one or more intervening layers.
The term “package” generally refers to a self-contained carrier of one or more dice, where the dice are attached to the package substrate, and may be encapsulated for protection, with integrated or wire-bonded interconnects between the dice and leads, pins or bumps located on the external portions of the package substrate. The package may contain a single die, or multiple dice, providing a specific function. The package is usually mounted on a printed circuit board for interconnection with other packaged integrated circuits and discrete components, forming a larger circuit.
Here, the term “cored” generally refers to a substrate of an integrated circuit package built upon a board, card or wafer of a non-flexible stiff material. Typically, a small printed circuit board is used as a core, upon which integrated circuit device and discrete passive components may be soldered. Typically, the core has vias extending from one side to the other, allowing circuitry on one side of the core to be coupled directly to circuitry on the opposite side of the core. The core may also serve as a platform for building up layers of conductors and dielectric materials.
Here, the term “coreless” generally refers to a substrate of an integrated circuit package having no core. The lack of a core allows for higher-density package architectures, as the through-vias have relatively large dimensions and pitch compared to high-density interconnects.
Here, the term “land side,” if used herein, generally refers to the side of the substrate of the integrated circuit package closest to the plane of attachment to a printed circuit board, motherboard, or other package. This is in contrast to the term “die side,” which is the side of the substrate of the integrated circuit package to which the die or dice are attached.
Here, the term “dielectric” generally refers to any number of non-electrically conductive materials that make up the structure of a package substrate. For purposes of this disclosure, dielectric material may be incorporated into an integrated circuit package as layers of laminate film or as a resin molded over integrated circuit dice mounted on the substrate.
Here, the term “metallization” generally refers to metal layers formed over and through the dielectric material of the package substrate. The metal layers are generally patterned to form metal structures such as traces and bond pads. The metallization of a package substrate may be confined to a single layer or in multiple layers separated by layers of dielectric.
Here, the term “ceramic” generally refers to non-metallic, non-organic materials, e.g., particles for cold-spray deposition, and can include diamond.
Here, the term “bond pad” generally refers to metallization structures that terminate integrated traces and vias in integrated circuit packages and dice. The term “solder pad” may be occasionally substituted for “bond pad” and carries the same meaning.
Here, the term “solder bump” generally refers to a solder layer formed on a bond pad. The solder layer typically has a round shape, hence the term “solder bump.”
Here, the term “sidewall” or “edge” when describing an integrated circuit die generally refers to the surfaces of the die with the smallest dimension, which are also generally the surfaces neither coupled to a substrate nor opposite the substrate. These surfaces can generally be thought of as forming the perimeter of the die relative to other objects on or regions of a substrate.
Here, the term “substrate” generally refers to a planar platform including dielectric and metallization structures. The substrate mechanically supports and electrically couples one or more integrated circuit dice on a single platform, with encapsulation of the one or more integrated circuit dice by a moldable dielectric material. The substrate may be an interposer.
The substrate generally includes solder bumps as bonding interconnects on both sides. One side of the substrate, generally referred to as the “die side,” includes solder bumps for chip or die bonding. The opposite side of the substrate, generally referred to as the “land side,” includes copper pads for socketing or solder bumps for bonding the package to a printed circuit board.
Here, the term “assembly” generally refers to a grouping of parts into a single functional unit. The parts may be separate and are mechanically assembled into a functional unit, where the parts may be removable. In another instance, the parts may be permanently bonded together. In some instances, the parts are integrated together.
Throughout the specification, and in the claims, the term “connected” means a direct connection, such as electrical, mechanical, or magnetic connection between the things that are connected, without any intermediary devices.
The term “coupled” means a direct or indirect connection, such as a direct electrical, mechanical, magnetic or fluidic connection between the things that are connected or an indirect connection, through one or more passive or active intermediary devices.
The term “circuit” or “module” may refer to one or more passive and/or active components that are arranged to cooperate with one another to provide a desired function. The term “signal” may refer to at least one current signal, voltage signal, magnetic signal, or data/clock signal. The meaning of “a,” “an,” and “the” include plural references. The meaning of “in” includes “in” and “on.”
The vertical orientation is in the z-direction and it is understood that recitations of “top,” “bottom,” “above,” and “below” refer to relative positions in the z-dimension with the usual meaning. However, it is understood that embodiments are not necessarily limited to the orientations or configurations illustrated in the figure.
The terms “substantially,” “close,” “approximately,” “near,” and “about,” generally refer to being within +/−10% of a target value (unless specifically specified). Unless otherwise specified the use of the ordinal adjectives “first,” “second,” and “third,” etc., to describe a common object, merely indicate that different instances of like objects to which are being referred and are not intended to imply that the objects so described must be in a given sequence, either temporally, spatially, in ranking or in any other manner.
For the purposes of the present disclosure, phrases “A and/or B” and “A or B” mean (A), (B), or (A and B). For the purposes of the present disclosure, the phrase “A, B, and/or C” means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B and C).
Views labeled “cross-sectional,” “profile,” and “plan” correspond to orthogonal planes within a cartesian coordinate system. Thus, cross-sectional and profile views are taken in the x-z plane, and plan views are taken in the x-y plane. Typically, profile views in the x-z plane are cross-sectional views. Where appropriate, drawings are labeled with axes to indicate the orientation of the figure.
Embodiments of the present description relate to the use of porous materials to enhance boiling and otherwise improve heat transfer from integrated circuit devices. The porous materials need not be metallic, but are generally preferred to be thermally conductive. In some embodiments, an integrated circuit package includes an integrated circuit die coupled to a substrate, and a porous material on the die, or a thermal interface material on the die, and extending beyond one or more sidewalls or edges of the die and further over the substrate. In some embodiments, an integrated circuit system includes a substrate with a power supply and an integrated circuit die, as well as a porous material on the die that extends over the substrate beyond a footprint of the die. In some embodiments, one or more integrated circuit dice may be coupled to a substrate and a porous material may be formed on and beyond the one or more integrated circuit dice over the substrate.
Electronic substrate 110 may further include conductive routes 118 or “metallization” (shown in dashed lines) extending through electronic substrate 110. As will be understood to those skilled in the art, conductive routes 118 may be a combination of conductive traces (not shown) and conductive vias (not shown) extending through the plurality of dielectric material layers (not shown). These conductive traces and conductive vias are well known in the art and, for purposes of clarity, are not shown in
Integrated circuit package 200 may be electrically attached to electronic substrate 110 in a configuration generally known as a flip-chip or controlled collapse chip connection (“C4”) configuration, according to some embodiments. Integrated circuit package 200 may include a package substrate 210 with a first surface 212 and an opposing second surface 214, and an integrated circuit die 220 electrically attached proximate second surface 214 of package substrate 210. In some embodiments, package substrate 210 is an interposer attached to electronic substrate 110 with the plurality of package-to-substrate interconnects 116. In some embodiments, package-to-substrate interconnects 116 extends between bond pads (not shown) proximate a first surface 112 of electronic substrate 110 and bond pads (not shown) proximate first surface 212 of package substrate 210.
Package substrate 210 may include any of the materials and/or structure as discussed previously with regard to electronic substrate 110. Package substrate 210 may further include conductive routes 218 or “metallization” (shown in dashed lines) extending through package substrate 210, which may include any of the materials and/or structures as discussed previously with regard to conductive routes 118 of electronic substrate 110. The bond pads (not shown) proximate first surface 212 of package substrate 210 may be in electrical contact with conductive routes 218, and conductive routes 218 may extend through package substrate 210 and be electrically connected to bond pads (not shown) proximate second surface 214 of package substrate 210. As will be understood to those skilled in the art, package substrate 210 may be a cored substrate or a coreless substrate.
Integrated circuit die 220 may be any appropriate device, including, but not limited to, a microprocessor, a chipset, a graphics device, a wireless device, a memory device, an application specific integrated circuit, a transceiver device, an input/output device, combinations thereof, stacks thereof, or the like. As shown in
In some embodiments, integrated circuit die 220 electrically attaches to package substrate 210 with a plurality of die-to-substrate interconnects 232. In some embodiments, die-to-substrate interconnects 232 extend between bond pads (not shown) on first surface 212 of package substrate 210 and bond pads (not shown) on first surface 222 of integrated circuit die 220. Die-to-substrate interconnects 232 may be any appropriate electrically conductive material or structure, including, but not limited to, solder balls, metal bumps or pillars, metal filled epoxies, or a combination thereof. In some embodiments, die-to-substrate interconnects 232 are solder balls formed from tin, lead/tin alloys (for example, 63% tin/37% lead solder), and high tin content alloys (e.g. 90% or more tin—such as tin/bismuth, eutectic tin/silver, ternary tin/silver/copper, eutectic tin/copper, and similar alloys). In some embodiments, die-to-substrate interconnects 232 are copper bumps or pillars. In some embodiments, die-to-substrate interconnects 232 are metal bumps or pillars coated with a solder material.
Die-to-substrate interconnects 232 may be in electrical communication with integrated circuitry (not shown) within integrated circuit die 220 and may be in electrical contact with conductive routes 218. Conductive routes 218 may extend through package substrate 210 and be electrically connected to package-to-substrate interconnects 116. As will be understood to those skilled in the art, package substrate 210 may be an interposer and reroute a fine pitch (center-to-center distance) of die-to-substrate interconnects 232 to a relatively wider pitch of package-to-substrate interconnects 116. Package-to-substrate interconnects 116 may be any appropriate electrically conductive material, including, but not limited to, metal-filled epoxies and solders, such as tin, lead/tin alloys (for example, 63% tin/37% lead solder), and high tin content alloys (e.g., 90% or more tin, such as tin/bismuth, eutectic tin/silver, ternary tin/silver/copper, eutectic tin/copper, and similar alloys). Although
As further shown in
Porous material 260 may be made of any appropriate thermally conductive material, including, but not limited to, at least one metal material and alloys of more than one metal, or highly doped glass or highly conductive ceramic material, such as aluminum nitride. In some embodiments, porous material 260 is or includes a ceramic or metal particles, carbon nanotubes, a metallic foam, a sintered metal pad, a metal mesh, and the like, which may further include diamond, copper, nickel, aluminum, alloys thereof, laminated metals including coated materials (such as nickel coated copper), and the like. Thermal interface material 254 may be any appropriate, thermally conductive material, including, but not limited to, a solder, a liquid metal, a mixture of liquid metal and polymer, a thermal grease, a thermal gap pad, a polymer, an epoxy filled with high thermal conductivity fillers, such as metal particles or silicon particles, and the like.
As illustrated in
Attachment adhesive 252 may be any appropriate material, including, but not limited to, silicones (such as polydimethylsiloxane), epoxies, and the like. It is understood that orthogonal portions 268 not only secure porous material 260 to package substrate 210, but may also help to maintain a desired distance (e.g., bond line thickness) between first surface 264 of porous material 260 and second surface 224 of integrated circuit die 220.
Prior to the attachment of porous material 260, an electrically-insulating underfill material 242 may be disposed between integrated circuit die 220 and package substrate 210, which substantially encapsulates die-to-substrate interconnects 232. Underfill material 242 may be used to reduce mechanical stress issues that can arise from thermal expansion mismatch between package substrate 210 and integrated circuit die 220. Underfill material 242 may be an epoxy material, including, but not limited to epoxy, cyanoester, silicone, siloxane and phenolic based resins, that has sufficiently low viscosity to be wicked between integrated circuit die 220 and package substrate 210 by capillary action when introduced by an underfill material dispenser (not shown), which will be understood to those skilled in the art. Underfill material 242 may be subsequently cured (hardened), such as by heat or radiation.
As shown in
In some embodiments, areas of thermal resistance are eliminated in order to improve the performance of the two-phase immersion cooling system. It is understood that getting dielectric low-boiling point liquid 120 as close to the heat source (e.g., integrated circuit die 220) is key for heat dissipation efficiency. To this end, in some embodiments, porous material 260 is directly on integrated circuit die 220. In some embodiments, thermal interface material 254 is used to help relax interface stress and to improve the thermal contact between integrated circuit die 220 and porous material 260. As shown in
In some embodiments, metal or ceramic particles, including diamond, are deposited, such as by cold-spray deposition, to form porous material 260. The thickness, or z-height, of porous material 260 can be varied to best suit the conditions of a particular application. Porous material 260 can be made thinner to, e.g., minimize the distance and material between integrated circuit die 220 and the coolant, dielectric low-boiling point liquid 120, but difficulties may be encountered as porous material 260 becomes too thin. In some embodiments, the thickness of porous material 260 is as low as 500 μm. Porous material 260 can be made thicker to, e.g., meet structural requirements, but effectiveness may decrease as porous material 260 becomes too thick. In some embodiments, the thickness of porous material 260 is as high as 3 mm. For example, the thickness of porous martial 260 above integrated circuit die 220 is in the range of 500 μm to 3 mm, in some embodiments. In some embodiments, the thickness of porous martial 260 above integrated circuit die 220 is in the range of 500 μm to 1 mm. In some embodiments, the thickness of porous martial 260 above integrated circuit die 220 is in the range of 2 mm to 3 mm. Other thicknesses may be used.
In some embodiments, the porosity of porous material 260 is varied to meet system requirements or to enhance certain capabilities, e.g., heat spreading. In some embodiments, the porosity is increased, e.g., by using metal meshes with larger openings, such that porous material 260 has a porosity as high as 50%. In other embodiments, the porosity is decreased, e.g., by using finer, tighter meshes or, in a porous material formed from particles, by using mixtures of particle sizes such that the void fraction of the porous material is reduced, as will be described later herein. In some embodiments, the porosity of porous material is not more than 50%. In some embodiments, the porosity of porous material is in the range of 40% to 50%. In some embodiments, the porosity of porous material is in the range of 30% to 45%. In some embodiments, the porosity of porous material is in the range of 25% to 40%. Other porosity values may be used. As used herein, the term porosity (or void fraction) is defined according to its standard use as the fraction of volume of voids over total volume.
In some embodiments, the porosity of porous material 260 is varied with z-height to meet system requirements or to enhance certain capabilities, e.g., heat spreading. In some embodiments, the porosity increases with z-height above integrated circuit dice 220, such that there is more space for vapor bubbles 122 as dielectric low-boiling point liquid 120 vaporizes on porous material 260. A portion of porous material 260 nearer, e.g., adjacent, integrated circuit dice 220 may have a lower porosity, that is, a higher density of material and a lower void fraction, than a portion further from integrated circuit dice 220. In some embodiments, the porosity of a material portion immediately adjacent integrated circuit die 220 (e.g., on integrated circuit die 220 or on thermal interface material 254) is in the range of 25% to 35% and the porosity of a material portion distal from integrated circuit die 220 (e.g., at second surface 266) is in the range of 40% to 50%. In some embodiments, the porosity of a material portion immediately adjacent integrated circuit die 220 (e.g., on integrated circuit die 220 or on thermal interface material 254) is in the range of 15% to 30% and the porosity of a material portion distal from integrated circuit die 220 (e.g., at second surface 266) is in the range of 35% to 50%. In some embodiments, the porosity of a material portion immediately adjacent integrated circuit die 220 (e.g., on integrated circuit die 220 or on thermal interface material 254) is in the range of 10% to 20% and the porosity of a material portion distal from integrated circuit die 220 (e.g., at second surface 266) is in the range of 40% to 50%. Other porosities may be used.
In some embodiments, porous material 260 is pre-formed in sizes, shapes, etc. to meet the needs of various embodiments, e.g., certain chip sizes or quantities. In some embodiments, effort and expense early in manufacturing can save subsequent effort and expense, e.g., later in assembly, and vice versa. For example, pre-forming, when desired, can obviate the need in some embodiments for support structures that have certain advantages in other embodiments.
In some embodiments, the use of, e.g., frames 330 allows for easier and less costly manufacturing or for important methods of manufacture or assembly not possible (or less convenient) otherwise. In some embodiments, frame 330 is made of a metal, including but not limited to a stainless steel and a similar alloy, which can provide mechanical stiffness for the package.
In some embodiments, the forming of porous material 260 is such that the porosity of porous material 260 varies with z-height above integrated circuit dice 220, as discussed herein. For example, the porosity can be made to increase with z-height above integrated circuit dice 220, such that the portion of porous material 260 adjacent integrated circuit dice 220 may have a lower porosity than a portion further from integrated circuit dice 220. Such forming may be done, e.g., by sintering metal meshes together such that the first, lowest layer of mesh nearest integrated circuit dice 220 has smaller openings and so a relatively lower porosity and the uppermost mesh distal integrated circuit dice 220 has larger openings and so a relatively higher porosity.
In some embodiments, the forming of porous material 260 is done, e.g., by cold-spray deposition of metal or ceramic particles, including diamond, using particles of substantially the same size, and the porosity is higher, approaching 50%. For example, porous material 260 could be made to have a higher porosity by cold-spray deposition of particles substantially of a single size, e.g., of a single group of particles with an average cross-sectional width of about 30 μm, where the porosity is substantially set by the predominate size and shape of the particles.
Similarly, in some embodiments, the forming by cold-spray deposition uses mixtures of particles of various sizes to give a lower porosity. Porous materials 260 with a lower porosity may be formed by cold-spray deposition of particles of varied sizes, e.g., of at least two groups of particles, one with an average cross-sectional width of about 20 μm and another with an average cross-sectional width of about 30 μm. In some embodiments, the porosity of porous material 260 is between 30 to 40%. Porous materials 260 with a lower porosity still may be formed using mixtures of particles of more varied sizes, e.g., of more groups of particles or groups with sizes chosen to fill in the voids otherwise left by larger particles. In some embodiments, porous material 260 is formed by cold-spray deposition of metal or diamond particles of average cross-sectional width of about 5 μm, 20 μm, and 30 μm, so as to have a porosity of around 20%. In this way, the porosity (or void fraction) of porous material 260 can be controlled and manipulated.
In some embodiments, the forming of porous material 260 is such that the porosity of porous material 260 may vary with z-height above integrated circuit dice 220. For example, the porosity can be made to increase with z-height above integrated circuit dice 220, such that the portion of porous material 260 adjacent integrated circuit dice 220 may have a lower porosity than a portion further from integrated circuit dice 220. Such forming may be done, e.g., by cold-spray deposition of metal or ceramic particles, including diamond. The portion of porous material 260 adjacent integrated circuit dice 220 with a lower porosity may be formed by cold-spray deposition of particles of varied sizes, e.g., of at least two groups of particles, one with an average cross-sectional width of about 20 μm and another with an average cross-sectional width of about 30 μm. The portion of porous material 260 distal integrated circuit dice 220 could be made to have a higher porosity by cold-spray deposition of particles substantially of a single size, e.g., of a single group of particles with an average cross-sectional width of about 30 μm. Similarly, other gradients or other portions of varying porosity of porous material 260 could be formed by using other mixtures of particles. Less porous layers could be formed using mixtures of particles such that smaller-sized particles could be used to partially fill voids left between larger-sized particles. In some embodiments, a lower-porosity, adjacent portion could be formed by cold-spray deposition of metal or diamond particles of more than two sizes, e.g., 5 μm, 20 μm, and 30 μm, so as to be less porous, and a higher-porosity, distal portion of porous material 260 could be formed by cold-spray deposition of metal or diamond particles of 30 μm (or 20 μm and 30 μm). In some embodiments, porous materials 260 have porosities of around 20%. In this way, the porosity of particular portions of porous material 260 can be controlled and manipulated. Less-porous layers or other portions could be formed by filling in somewhat with smaller particles the spaces between larger particles.
In some embodiments, porous material 260 is formed by cold spraying, growth, deposition, printing, or the like, such that the material composition of porous material 260 is varied with z-height above integrated circuit dice 220. The 3D buildup, growth, printing, cold-spray coating, or other deposition may be done such that some layers or other portions include different materials, or have different concentrations of materials, than other layers or other portions. For example, in some embodiments, the forming of porous material 260 can provide for a highest concentration of carbon nanotubes in the portion of porous material 260 immediately above integrated circuit die 220, and one or more lower concentrations of carbon nanotubes in one or more other portions of porous material 260 as the z-height above integrated circuit die 220 increases. Two layers of different concentrations may be one above the other, or other and more gradients of various concentrations can be arranged as suits a particular embodiment.
The embodiments of
In some embodiments, further areas of thermal coupling are enhanced in order to improve the boiling and so the thermal performance. As shown in
As with the embodiments of
Porous materials can be formed to various sizes to extend beyond integrated circuit die sidewalls or edges and to allow for, e.g., different integrated circuit die sizes, quantities, and configurations. In some embodiments, metal particles are sintered onto a spreader insert and then attached to a received integrated circuit die. Some porous materials are formed (e.g., with various printing, 3D buildup, growth, coating, deposition, or other methods) directly on a received integrated circuit die. Such processes allow for formation of various extents, even well beyond the edges of a single integrated circuit die to optionally include multiple dice.
In embodiments that include optional operation 1130, a cold-spray coating method may be used to form a porous material by depositing a mixture of copper and synthetic diamond particles onto and over an integrated circuit die and onto a substrate the die is coupled to. In some embodiments, cold-spray coating methods are used to deposit a mixture of particles onto a spreader insert and then another mixture onto a received integrated circuit die coupled to a substrate. In other embodiments, a 3D buildup process may be used to grow a porous material onto and over an integrated circuit die and onto a substrate the die is coupled to.
As shown in optional operation 1140, some embodiments may employ varied porosities in different portions of the porous material to, e.g., enhance boiling. In some embodiments, portions of the porous material formed nearest an integrated circuit die have less porosity and portions further from the integrated circuit die are more porous. In some embodiments, the porous material is formed by sintering metal meshes together and attaching them to an integrated circuit die and over a substrate, such that the lowest mesh adjacent the integrated circuit die is very fine and tight and not very porous, and the top mesh furthest from the integrated circuit die is more porous, having larger openings relative to the metal of the mesh. In some embodiments, a porous material is formed on an integrated circuit die and over a substrate, and a metal foam is formed on an integrated circuit die with the foam adjacent the die having relatively fewer and smaller voids than the foam furthest from the die, which has more and or larger voids and so is more porous. In some embodiments, shown in optional operation 1150, a porous material is formed on an integrated circuit die and over a substrate, and the porous material includes particles of various sizes such that a top layer of the porous material is more porous than a bottom layer of the porous material adjacent the integrated circuit die. In this embodiment, the porosities are set by the one or more sizes of the particles making up the porous material, as the top layer of the porous material is formed substantially from particles with average cross-sectional widths of 30 μm and a bottom layer of the porous material (adjacent the integrated circuit die) is formed from a mixture of particles with average cross-sectional widths of 20 μm and 30 μm. In some embodiments, a porous material with porosity of 50% forms a top layer and a porous material with porosity of 35% forms a bottom layer. The use of the relatively smaller particles in the bottom layer of the porous material will allow for the voids nearest the integrated circuit die to be filled in somewhat more than those in the top layer making for a lower porosity in the bottom layer of the porous material adjacent the integrated circuit die and a higher porosity in the top layer of the porous material. In some embodiments, the porous material in the top layer is formed with a mixture of particles with average cross-sectional widths of 20 μm and 30 μm and the porous material adjacent the integrated circuit die is formed with a mixture having even smaller particles, e.g., with average cross-sectional widths of 20 μm and 30 μm but also 1 μm and 5 μm, such that the voids nearest the integrated circuit die are generally filled in more and so are smaller than those distal the integrated circuit die. In some embodiments, a porous material with porosity of 40% forms a top layer and a porous material with porosity of 20% forms a bottom layer. In some embodiments, porous materials are made to have porosities of around 10%. In a yet further embodiment, the porous material of varying porosities is formed on the integrated circuit die and over its substrate using a cold-spray coating method of depositing the various particle mixtures.
The communication chip enables wireless communications for the transfer of data to and from the computing device. The term “wireless” and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non-solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not. The communication chip may implement any of a number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The computing device may include a plurality of communication chips. For instance, a first communication chip may be dedicated to shorter range wireless communications such as Wi-Fi and Bluetooth and a second communication chip may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.
The term “processor” may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.
The entire computing device 1200 or at least one of the integrated circuit components within computing device 1200 may be immersed in a two-phase immersion cooling system, e.g., a fluid containment structure containing a dielectric low-boiling point liquid. In some embodiments, the integrated circuit component includes an integrated circuit package having a porous material on a thermal interface material and one or more integrated circuit dice. In some embodiments, the porous material is formed or directly attached on the integrated circuit die(s) without the use of thermal interface material.
In various implementations, the computing device may be a laptop, a netbook, a notebook, an ultrabook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra-mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder. In further implementations, the computing device may be any other electronic device that processes data.
It is understood that the subject matter of the present description is not necessarily limited to specific applications illustrated in
The following examples pertain to further embodiments, and specifics in the examples may be used anywhere in one or more embodiments.
In one or more first embodiments, an apparatus comprises an integrated circuit die coupled to a first region of a surface of a package substrate, and a porous material directly on the integrated circuit die or directly on a thermal interface material on the integrated circuit die, wherein the porous material extends beyond a sidewall surface of the integrated circuit die and over a second region of the surface of the package substrate.
In one or more second embodiments, further to the first embodiments, the porous material comprises at least one of ceramic particles or metal particles.
In one or more third embodiments, further to the first or second embodiments, a porosity of the porous material increases as a z-height increases above the integrated circuit die.
In one or more fourth embodiments, further to the first through third embodiments, the porous material comprises a first portion adjacent a top surface of the integrated circuit die and a second portion distal from the top surface of the integrated circuit die, the second portion comprising a greater porosity than the first portion, and the second portion comprising particles of a first size and the first portion comprising particles of the first size and a second size.
In one or more fifth embodiments, further to the first through fourth embodiments, the porous material comprises carbon nanotubes.
In one or more sixth embodiments, further to the first through fifth embodiments, a concentration of the carbon nanotubes in the porous material decreases as a z-height increases above the integrated circuit die.
In one or more seventh embodiments, further to the first through sixth embodiments, a second integrated circuit die is coupled to a third region of the surface of the package substrate, and a spreader insert is directly on the second integrated circuit die or directly on a thermal interface material on the second integrated circuit die, wherein the porous material is directly on the spreader insert.
In one or more eighth embodiments, further to the first through seventh embodiments, the spreader insert comprises one or more of copper, diamond, carbon nanotubes, or a vapor chamber.
In one or more ninth embodiments, further to the first through eighth embodiments, the porous material comprises a first portion substantially parallel with the package substrate and one or more second portions substantially orthogonal with, and connected to, the package substrate, wherein the integrated circuit die is enclosed by the porous material and the package substrate.
In one or more tenth embodiments, further to the first through ninth embodiments, the porous material extends substantially parallel to the package substrate and is mounted on a frame connected to the package substrate, wherein the integrated circuit die is enclosed by the package substrate, the porous material, and the frame.
In one or more eleventh embodiments, further to the first through tenth embodiments, the porous material is on the sidewall surface of the integrated circuit die and the second region of the surface of the substrate package.
In one or more twelfth embodiments, further to the first through eleventh embodiments, a second integrated circuit die is coupled to a third region of the surface of the package substrate, wherein the porous material is on the sidewall surface of the second integrated circuit die and the porous material fills that portion of the second region of the surface of the substrate package between the first integrated circuit die and the second integrated circuit die.
In one or more thirteenth embodiments, further to the first through twelfth embodiments, the porous material has a porosity of not more than 50%.
In one or more fourteenth embodiments, further to the first through thirteenth embodiments, the porous material comprises particles with average cross-sectional widths of not less than 20 μm and not more than 30 μm.
In one or more fifteenth embodiments, further to the first through fourteenth embodiments, a power supply is coupled to the package substrate.
In one or more sixteenth embodiments, a system comprises a power supply, an integrated circuit die coupled to a package substrate, and a porous material on the integrated circuit die or on a thermal interface material on the integrated circuit die, wherein the porous material is over a footprint of the integrated circuit die and extends beyond the footprint of the integrated circuit die in one or more directions parallel to the package substrate.
In one or more seventeenth embodiments, further to the sixteenth embodiments, a second integrated circuit die with a second footprint is coupled to the package substrate, and a spreader insert is on the second integrated circuit die or on a thermal interface material on the second integrated circuit die, wherein the porous material is on the spreader insert, and wherein the spreader insert comprises one or more of copper, diamond, carbon nanotubes, or a vapor chamber.
In one or more eighteenth embodiments, further to the sixteenth through seventeenth embodiments, the porous material comprises at least one of ceramic or metal particles.
In one or more nineteenth embodiments, further to the sixteenth through eighteenth embodiments, a fluid containment structure contains a dielectric low-boiling point liquid, wherein the porous material and the integrated circuit die are submerged in the dielectric low-boiling point liquid.
In one or more twentieth embodiments, a method comprises receiving an integrated circuit die coupled to a first region of a surface of a package substrate, and forming a porous material directly on the integrated circuit die or directly on a thermal interface material on the integrated circuit die, wherein the porous material extends beyond a sidewall of the integrated circuit die and over a second region of the surface of the package substrate.
In one or more twenty-first embodiments, further to the twentieth embodiments, said forming the porous material comprises forming the porous material directly on a spreader insert coupled to a second integrated circuit die on a second region of the surface of the package substrate.
In one or more twenty-second embodiments, further to the twentieth through twenty-first embodiments, a porosity of the porous material varies with z-height above the integrated circuit die.
In one or more twenty-third embodiments, further to the twentieth through twenty-second embodiments, the porous material comprises particles and the varying of the porosity of the porous material is controlled by varying one or more particle sizes of the one or more porous material particles.
In one or more twenty-fourth embodiments, further to the twentieth through twenty-third embodiments, said forming the porous material comprises cold-spray coating the porous material onto the integrated circuit die and the package substrate.
Having thus described in detail embodiments of the present invention, it is understood that the invention defined by the appended claims is not to be limited by particular details set forth in the above description, as many apparent variations thereof are possible without departing from the spirit or scope thereof.
