Patent Application
20070194453
The present invention relates generally to semiconductor devices, and more particularly relates to architectures for reducing the effects of interconnect parasitics in an integrated circuit device.
As a consequence of the recent trend to push the lateral integration of systems on a chip (SoC), modern advanced application-specific integrated circuit (ASIC) design has focused largely on interconnects. This is due primarily to the fact that interconnects have become a dominant factor in determining circuit performance and reliability in deep submicron designs. Signal integrity problems, such as, for example, crosstalk noise, current x resistance (IR)-drop and coupling-induced delay variation are becoming increasingly more significant due at least in part to the larger parasitics associated with an increasing number of interconnects and an increased circuit density in a given integrated circuit device. At the same time, the complexity of implementing large systems on a chip is becoming increasingly burdensome on designers.
There have been various attempts aimed at reducing the effect of interconnect parasitics in an integrated circuit. From a circuit level standpoint, known methodologies for addressing signal integrity problems locally include inserting one or more buffers in a given signal path, driver sizing, wire spacing and wiring sizing optimizations, etc. However, most circuit level solutions typically consume significant routing resources and usually result in a substantial increase in the number of iterations in the physical design loop, thereby undesirably increasing the design cycle of the integrated circuit and delaying time to market.
Integrated circuit chip level solutions for reducing the effects of interconnect parasitics include planar integration of functional blocks and better placements of these functional blocks in the chip in order to optimize the distance of global routing. Known package level solutions attempting to minimize the effects of interconnect parasitics in an integrated circuit typically involve reducing the overall length of interconnects in the integrated circuit by employing die stacking methodologies to implement system in a package (SiP) designs. Both chip level and package level solutions, however, generally involve planar integration of functional blocks within the same chip, and therefore do not address signal integrity problems associated with global on-chip interconnects in advancing design technologies. Consequently, with chip level and package level solutions, a designer must be careful when sending global signals and/or clock signals to respective corners of the chip simultaneously.
Accordingly, there exists a need for an improved integrated circuit architecture for reducing the effects of interconnect parasitics, which does not suffer from one or more of the problems exhibited by conventional integrated circuit architectures.
The present invention meets the above-noted need by providing an improved integrated circuit architecture for reducing the effects of interconnect parasitics in an integrated circuit device and thereby improving circuit performance and reliability, particularly in deep submicron SoC designs. To accomplish this, in accordance with an illustrative embodiment of the invention, components or other circuits are distributed into at least two semiconductor chips, each semiconductor chip being used to handle different functional tasks. For example, a first chip, which may be referred to as a core chip, includes core components or other core circuits which will work cooperatively together as a system for handling core-related functional tasks. Similarly, a second chip, which may be referred to as an input/output (IO) chip, includes IO components or other IO circuits which will work cooperatively together for handling IO-related functional tasks. In this manner, the separate functional tasks can be independently optimized for improving overall integrated circuit performance.
In accordance with one aspect of the invention, an integrated circuit includes a first semiconductor chip including one or more circuits thereon performing substantially core logic functions, the first semiconductor chip including multiple signal pads for providing electrical connection to the one or more circuits. The integrated circuit further includes at least a second semiconductor chip including one or more circuits thereon performing substantially input/output interface functions, the second semiconductor chip including multiple signal pads for providing electrical connection to the one or more circuits on the second semiconductor chip. The signal pads on the second semiconductor chip are substantially aligned with and electrically connected to corresponding signal pads on the first semiconductor chip. The first and second semiconductor chips are mutually functionally dependent on one another, such that at least a portion of at least one of the one or more circuits on the first semiconductor chip utilizes at least a portion of at least one of the one or more circuits on the second semiconductor chip, and vice versa. The first and second semiconductor chips are formed using first and second semiconductor fabrication processes, respectively.
These and other features and advantages of the present invention will become apparent from the following detailed description of illustrative embodiments thereof, which is to be read in connection with the accompanying drawings.
The present invention will be described herein in the context of an illustrative SoC integrated circuit architecture. It should be understood, however, that the present invention is not limited to this or any other particular integrated circuit architecture and/or application. Rather, the invention is more generally applicable to techniques for providing an improved integrated circuit architecture for reducing the effects of interconnect parasitics in an integrated circuit device and thereby improve circuit performance and reliability, particularly in deep submicron SoC designs.
During packaging of the integrated circuit device 100, the second chip 104 may be attached to a package substrate 108, using, for example, a solder bond or an epoxy bond between a lower surface of the second chip 104 and an upper surface of the package substrate 108, although alternative die attachment means for fixedly attaching the second chip 104 to the package substrate 108 are contemplated by the invention, as will be understood by those skilled in the art. The package substrate 108 may be formed of various known substantially rigid materials, including, but not limited to, ceramic, plastic, laminate, etc. Package substrate 108 preferably comprises a leadframe including a plurality of pins 110, or an alternative connection structure (e.g., ball grid array (BGA)), for providing external electrical connection to the integrated circuit device 100. Bond wires 112, or an alternative connection arrangement, may be used to connect the pins 110 in the leadframe or BGA to corresponding bond pads 114 formed on the upper surface of the second chip 104, such as by using a standard wire bonding process. The first chip 102 is preferably not connected to the leadframe or BGA, and therefore need not include bond pads.
A primary aspect of the integrated circuit architecture of the invention is that components or other circuits of a given system design are beneficially distributed into two or more semiconductor chips, as shown, with each chip comprising one or more circuit components or other that are functionally related to one another. For example, the system design may include a plurality of circuit components for performing primarily input/output (IO) functions, such as, but not limited to, analog-to-digital (AD) conversion, digital-to-analog (DA) conversion, serial-to-parallel conversion, parallel-to-serial conversion, IO buffering, clock generation, reference voltage generation, etc. These circuit components may be placed on an IO chip (e.g., second chip 104) including a plurality of bond pads providing external connection to the IO chip. Likewise, the system design may also include a plurality of circuit components for performing primarily core logic functions, such as, but not limited to, digital signal processing (DSP), timing control, algorithmic logic (AND, OR, NOT functions), etc. These circuit components may be placed on a core logic chip (e.g., first chip 102).
Since the system design is distributed into two or more semiconductor chips, each of which may be fabricated using different process technologies, the chips can be independently optimized according to the type of related functional circuit components or other circuits included thereon. For instance, IO circuit components are generally analog in nature and consume significantly more power compared to core logic circuitry. Consequently, power and ground connections employed on the IO chip may be formed wider compared to power and ground connections employed on the core logic chip so as to reduce IR drops and other signal integrity problems. This also enables the Preferably, power supply connections to the IO chip and to the core logic chip are separate. In fact, the core logic circuitry typically uses a supply voltage which is lower than the supply voltage used for the IO chip. In one embodiment of the invention, the core logic chip voltage supply is preferably about 1.0 volt and the IO chip voltage supply is about 3.3 volts, although the invention is not limited to any particular levels for the respective voltage supplies. By separating the power and ground supplies for the two chips, substrate noise often generated by digital logic circuitry on the core logic chip can be more easily isolated so as to avoid undesirably affecting analog circuitry on the IO chip. Core logic circuitry also scales more easily with processing technology, and thus the size of the core logic chip, which preferably only includes core logic circuitry, can be more easily optimized for size compared to the IO chip.
Unlike in SiP integrated circuit architectures employing stacked die arrangements, wherein each die comprises a self-contained, independently functioning system, the first and second chips 102, 104 in the exemplary integrated circuit device 100 do not function independently but rather are mutually functionally dependent on one another. Specifically, at least a portion of one or more of the circuit components on the first chip 102 utilizes at least a portion of one or more of the circuit components on the second chip 104, and vice versa, such that one chip does not fully function without the other chip. Thus, the two chips 102, 104 work cooperatively as a system.
Since the integrated circuit device 100 preferably employs a substantially vertical connection arrangement between the two chips 102, 104, interconnect routing between IO functional components and core logic functional components of the overall system design can be significantly reduced. Accordingly, the problems associated with such interconnect routing, including, but not limited to, crosstalk, routing congestion, etc., will also be advantageously reduced.
The IO functional blocks (e.g., 202, 204, 206, 208) included on the IO chip 200 are preferably common IO building blocks shared by various core logic circuit designs. Thus, the IO chip 200, in accordance with an aspect of the invention, can beneficially serve as a platform for handling generic IO interface functions common to a given system design. The IO chip can be reused for various system designs. By replacing the core logic chip connected to a given IO chip with one of a plurality of other semiconductor chips having a functionality different than that of the core logic chip, a different overall functionality can be achieved in the integrated circuit. This integrated circuit architecture thus enables circuit designers to concentrate their efforts on the core logic portion of the system design rather than on the IO interface portion of the system, thereby advantageously reducing cost, reducing design resources, and facilitating a shorter time-to-market compared to standard design practices.
Another benefit of the integrated circuit architecture of the present invention is that state-of-the-art foundry services are costly and not all circuits in the system benefit from such advanced processing. For example, digital logic circuitry, as may be included on the core logic chip, typically scales far more easily with advances in processing technology than the IO chip which comprises primarily analog circuitry. Consequently, using the techniques of the present invention set forth herein, the core logic chip may be fabricated using one process technology and the IO chip can be fabricated using another, less expensive process technology.
An encapsulant material 416 preferably encloses the first and second semiconductor chips and covers at least a portion of the die-attachment substrate 402, such that the plurality of electrical contacts 404 remains at least partially uncovered for electrical connection thereto. The encapsulant material 416 is preferably an epoxy overcoat or plastic molding, although other suitable means for encapsulating the chips are similarly contemplated (e.g., ceramic), as will be known by those skilled in the art. In the figure, the encapsulant material has been cut away so that the interior of the integrated circuit package can be viewed. In production, however, the encapsulant would completely cover the chips 408, 410.
At least a portion of the methodologies of the present invention may be implemented in an integrated circuit. In forming integrated circuits, a plurality of identical die is typically fabricated in a repeated pattern on a surface of a semiconductor wafer. Each die includes a device described herein, and may include other structures and/or circuits. The individual die are cut or diced from the wafer, then packaged as an integrated circuit. One skilled in the art would know how to dice wafers and package die to produce integrated circuits. Integrated circuits so manufactured are considered part of this invention.
Although illustrative embodiments of the present invention have been described herein with reference to the accompanying drawings, it is to be understood that the invention is not limited to those precise embodiments, and that various other changes and modifications may be made therein by one skilled in the art without departing from the scope of the appended claims.
