Integrated circuit device gate structures having charge storing nano crystals in a metal oxide dielectric layer and methods of forming the same

Abstract

Methods of forming a gate structure for an integrated circuit memory device include forming a metal oxide dielectric layer on an integrated circuit substrate. Ions of a selected element from group 4 of the periodic table and having a thermal diffusivity of less than about 0.5 centimeters per second (cm2/s) are injected into the dielectric layer to form a charge storing region in the dielectric layer with a tunnel dielectric layer under the charge storing region and a capping dielectric layer above the charge storing region. The substrate including the metal oxide dielectric layer is thermally treated to form a plurality of discrete charge storing nano crystals in the charge storing region. A gate electrode layer is formed on the dielectric layer.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other features and advantages of the present invention will become more apparent by describing in detail exemplary embodiments thereof with reference to the attached drawings in which:

FIG. 1 is a schematic cross-sectional view illustrating erase and program operations in a conventional floating gate memory cell.

FIG. 2 is a schematic cross-sectional view illustrating a leakage path for a conventional continuous floating gate memory cell.

FIGS. 3A through 3D are cross-sectional views illustrating methods of forming a gate structure for an integrated circuit device according to some embodiments of the present invention.

FIGS. 4A and 4B are diagrams illustrating heat treatments for forming a charge storing region including discrete charge storing nano crystals according to some embodiments of the present invention.

FIG. 5 is a cross-sectional view illustrating a charge trapping double layer structure according to some embodiments of the present invention.

FIG. 6 is a cross-sectional view illustrating a flash memory device including a gate structure according to some embodiments of the present invention.

FIGS. 7A through 7C are energy band diagrams for a flash memory device according to some embodiments of the present invention.

FIGS. 8 through 11 are cross-sectional views illustrating flash memory devices including gate structures according to further embodiments of the present invention.

FIG. 12A is a capacitance-voltage (C-V) hysteresis curve for a flash memory device according to some embodiments of the present invention.

FIGS. 12B and 12C are capacitance-voltage (C-V) hysteresis curves for a flash memory device without a metal oxide capping layer.

FIGS. 13A through 13E are capacitance-voltage (C-V) hysteresis curves for a flash memory device thermally treated at different temperatures according to some embodiments of the present invention.

FIG. 14 is a schematic cross-sectional view illustrating a leakage path for a discrete charge storing nano crystal floating gate.

FIG. 15 is a diagram illustrating simulated implantation results according to some embodiments of the present invention.

FIG. 16 is a flowchart illustrating operations for forming a gate structure for an integrated circuit device according to some embodiments of the present invention.

FIG. 17 is a cross-sectional view illustrating a charge trapping double layer structure according to other embodiments of the present invention.

FIG. 18 is a cross-sectional view illustrating a charge trapping single layer structure according to further embodiments of the present invention.

FIGS. 19A through 19C are energy band diagrams for a flash memory device according to other embodiments of the present invention.

FIG. 20 is a TEM photograph illustrating a cross-sectional view of a charge trap double layer structure according to some embodiments of the present invention.

FIG. 21 is a capacitance-voltage (C-V) hysteresis curve for a flash memory device according to other embodiments of the present invention.

FIG. 22 is a graphical illustration of leakage current characteristics according to some embodiments of the present invention.

FIGS. 23A and 23B are capacitance-voltage (C-V) hysteresis curves for a flash memory device according to further embodiments of the present invention.

FIG. 24 is a table of cross-sectional views of charge trap structures and methods of forming the same according to some embodiments of the present invention.

Claims

1. A method of forming a gate structure for an integrated circuit memory device, comprising: forming a metal oxide dielectric layer on an integrated circuit substrate;injecting ions of a selected element from group 4 of the periodic table and having a thermal diffusivity of less than about 0.5 centimeters per second (cm2/s) into the dielectric layer to form a charge storing region in the dielectric layer with a tunnel dielectric layer under the charge storing region and a capping dielectric layer above the charge storing region;thermally treating the substrate including the metal oxide dielectric layer to form a plurality of discrete charge storing nano crystals in the charge storing region; andforming a gate electrode layer on the dielectric layer.

2. The method of claim 1, wherein the metal oxide dielectric layer comprises an oxide and/or oxynitride of aluminum, hafnium, titanium, zirconium, scandium, yttrium and/or lanthanum having a dielectric constant of over 7 and wherein the selected element comprises germanium (Ge).

3. The method of claim 1, wherein injecting ions comprises injecting the ions at an injection energy of less than about 10000 electron volts (eV).

4. The method of claim 3 wherein injecting ions comprises injecting the ions at an injection energy of greater than 5000 electron volts (eV).

5. The method of claim 4, wherein a thickness of the metal oxide dielectric layer formed on the substrate is less than about 30 nm.

6. The method of claim 1, wherein injecting ions is preceded by thermally treating the substrate including the metal oxide dielectric layer.

7. The method of claim 6, wherein injecting ions is preceded by thermally treating the substrate including the metal oxide dielectric layer at a temperature over a crystallization temperature of the metal oxide dielectric layer.

8. The method of claim 7, wherein injecting ions is preceded by thermally treating the substrate including the metal oxide dielectric layer at a temperature of at least about 950° C. in a nitrogen atmosphere.

9. The method of claim 7, wherein thermally treating the substrate after injecting ions comprises rapid thermal annealing the substrate including the metal oxide dielectric layer about 700° C. to about 900° C. for about 5 minutes to about 30 minutes.

10. The method of claim 9, wherein rapid thermal annealing is followed by a second rapid thermal annealing at about 900° C. to about 1050° C. for about 5 minutes to about 30 minutes.

11. The method of claim 1, wherein thermally treating the substrate after injecting ions comprises rapid thermal annealing the substrate including the metal oxide dielectric layer at about 900° C. to about 950° C. for about 5 minutes to about 30 minutes.

12. The method of claim 1, wherein a thickness of the metal oxide dielectric layer is less than about 30 nanometers (nm).

13. The method of claim 12, wherein a thickness of the tunnel dielectric layer is less than about 9 nm.

14. The method of claim 1, wherein injecting ions comprises injecting the ions at a mean injection depth selected based on a thickness of the metal oxide dielectric layer and with a delta projection range of no more than about 7 nanometers (nm).

15. The method of claim 14, wherein injecting ions comprises injecting the ions with a delta projection range of from about 20 angstroms (Å) to about 60 Å.

16. The method of claim 1, wherein the metal oxide dielectric layer has an energy band gap of at least about 5 electron volts (eV).

17. The method of claim 1, wherein injecting ions comprises injecting the ions at an ion injection energy of greater than 7000 electron volts (eV) and less than about 10000 eV and at an ion projection dose from about 1×1014/cm2 to about 2×1016/cm2.

18. The method of claim 1, wherein the nano crystals have a diameter from about 1 nm to about 7 nm and a spacing between ones of the nano crystals is between about 1 nm and about 7 nm.

19. The method of claim 1, wherein injecting ions comprises: injecting ions of the selected element at a first ion injection energy to form a first charge storing layer on the tunnel dielectric layer; andinjecting ions of the selected element at a second ion injection energy, less than the first ion injection energy, to form a second charge storing layer on the first charge storing layer with a region therebetween substantially free of implanted ions.

20. The method of claim 1 wherein injecting ions includes injecting ions at a plurality of different height locations relative to the substrate in the metal oxide dielectric layer and wherein thermally treating the substrate provides a multi-layer structure of overlapping ones of the discrete charge storing nano crystals.

21. The method of claim 1, wherein forming the metal oxide dielectric layer is preceded by forming a common gate on a gate dielectric layer on the substrate and wherein forming the metal oxide dielectric layer and implanting ions are carried out on sidewalls of the common gate electrode and on a channel portion of the substrate proximate respective sides of the common gate and wherein forming the gate electrode layer comprises forming sidewall gates on the second dielectric layer proximate the respective sides of the common gate and extending over the channel portion.

22. The method of claim 1, wherein forming the metal oxide dielectric layer is preceded by forming a channel region including a recess region and a step region adjacent the recess region extending between a source and a drain region in the substrate and wherein forming the metal oxide dielectric layer, implanting ions and forming the gate electrode are carried out on the channel region including the recess region and the step region.

23. The method of claim 21, wherein the recess region has a rounded portion.

24. The method of claim 1, wherein the integrated circuit device comprises a non-volatile memory device or a dynamic random access memory (DRAM).

25. The method of claim 23, wherein the integrated circuit device comprises a flash memory and wherein the charge storing region comprises a floating gate of a cell of the flash memory.

26. The method of claim 1, wherein the metal oxide dielectric layer comprises a first dielectric layer and wherein the method further comprises, between injecting ions and thermally treating the substrate, forming a second dielectric layer on the metal oxide dielectric layer, the second dielectric layer comprising a metal oxide.

27. The method of claim 26, wherein the second dielectric layer has a thickness of less than about 10 nm.

28. The method of claim 26, wherein the first and second dielectric layer comprise a same material.

29. The method of claim 26, wherein the first and second dielectric layer comprise an oxide and/or oxynitride of aluminum, hafnium, titanium, zirconium, scandium, yttrium and/or lanthanum and wherein the selected element comprises germanium (Ge).

30. The method of claim 26, wherein injecting ions comprises injecting the ions at an injection energy of less than about 10000 electron volts (eV).

31. The method of claim 30 wherein injecting ions comprises injecting the ions at an injection energy of greater than 7000 electron volts (eV).

32. The method of claim 31, wherein a thickness of the metal oxide dielectric layer formed on the substrate is less than about 20 nm.

33. The method of claim 26, wherein injecting ions is preceded by thermally treating the substrate including the first dielectric layer.

34. The method of claim 33, wherein injecting ions is preceded by thermally treating the substrate including the first dielectric layer at a temperature over a crystallization temperature of the first dielectric layer.

35. The method of claim 26, wherein injecting ions comprises injecting the ions at a selected mean injection depth and with a delta projection range of no more than about 7 nanometers (nm).

36. The method of claim 26, wherein injecting ions comprises injecting the ions at an ion injection energy of greater than 7000 electron volts (eV) and at an ion projection dose from about 1×1014/cm2 to about 2×1016/cm2.

37. The method of claim 36, wherein the ion injection energy is no more than about 10000 eV.

38. The method of claim 26, wherein forming the second dielectric layer comprises forming the second dielectric layer by atomic layer deposition (ALD) and/or plasma enhanced chemical vapor deposition (PECVD).

39. The method of claim 26, wherein forming the first dielectric layer is preceded by forming a common gate on a gate dielectric layer on the substrate and wherein forming the first dielectric layer, implanting ions and forming the second dielectric layer are carried out on sidewalls of the common gate electrode and on a channel portion of the substrate proximate respective sides of the common gate and wherein forming the gate electrode layer comprises forming sidewall gates on the second dielectric layer proximate the respective sides of the common gate and extending over the channel portion.

40. The method of claim 26, wherein forming the first dielectric layer is preceded by forming a channel region including a recess region and a step region adjacent the recess region extending between a source and a drain region in the substrate and wherein forming the first dielectric layer, implanting ions and forming the second dielectric layer and gate electrode are carried out on the channel region including the recess region and the step region.

41. The method of claim 40, wherein the recess region has a rounded portion.

42. The method of claim 26, wherein the integrated circuit device comprises a non-volatile memory device or a dynamic random access memory (DRAM).

43. The method of claim 42, wherein the integrated circuit device comprises a flash memory and wherein the charge storing region comprises a floating gate of a cell of the flash memory.

44. A method of forming a gate structure for an integrated circuit memory device, comprising: forming a metal oxide dielectric layer on an integrated circuit substrate;thermally treating the substrate including the metal oxide dielectric layer at a temperature over a crystallization temperature of the metal oxide dielectric layer;injecting ions of germanium (Ge) into the thermally treated first dielectric layer at an ion injection energy of less than about 10000 electron volts (eV) and at an ion projection dose from about 1×1014/cm2 to about 2×1016/cm2 to form a charge storing region in the metal oxide dielectric layer with a tunnel dielectric layer under the charge storing region and a capping dielectric layer above the charge storing region;rapid thermal annealing the substrate including the first dielectric layer and the second dielectric layer at about 700° C. to about 900° C. for about 5 minutes to about 30 minutes to form a plurality of discrete charge storing nano crystals in the charge storing region; andforming a gate electrode layer on the second dielectric layer.

45. The method of claim 44, wherein the metal oxide dielectric layer comprises a first dielectric layer and wherein the method further comprises, between injecting ions and rapid thermal annealing, forming a second dielectric layer on the metal oxide dielectric layer, the second dielectric layer comprising a metal oxide, and wherein the second dielectric layer has a thickness of less than about 10 nm.

46. A gate structure for an integrated circuit device, comprising: an integrated circuit substrate;a metal oxide dielectric layer on the substrate, the metal oxide dielectric layer including a tunnel dielectric layer on the substrate, a charge storing layer including a plurality of discrete nano-crystals of a selected element from group 4 of the periodic table and having a thermal diffusivity of less than about 0.5 centimeters per second (cm2/s) on the tunnel dielectric layer and a capping dielectric layer on the charge storing layer; anda gate electrode layer on the capping dielectric layer.

47. The gate structure of claim 46, wherein the metal oxide dielectric layer comprises a first dielectric layer and wherein the gate structure further comprises a second dielectric layer interposed between the capping dielectric layer and the gate electrode layer, the second dielectric layer comprising a metal oxide and having a thickness of less than about 10 nm.

48. The gate structure of claim 47, wherein the first dielectric layer has a thickness of no more than about 20 nm.

49. The gate structure of claim 47, wherein the first and second dielectric layers comprise an oxide and/or oxynitride of aluminum, hafnium, titanium, zirconium, scandium, yttrium and/or lanthanum.

50. The gate structure of claim 46, wherein the tunnel dielectric layer has a thickness of no more than about 9 mm.

51. The gate structure of claim 46, wherein the nano crystals have a diameter from about 1 nm to about 7 nm and a spacing between ones of the nano crystals is between about 1 nm and about 7 nm.

52. The gate structure of claim 46 wherein the charge storing region includes a multi-layer structure of overlapping ones of the discrete charge storing nano crystals.

53. The gate structure of claim 46, wherein the integrated circuit device comprises a non-volatile memory device or a dynamic random access memory (DRAM).

54. The gate structure of claim 46, wherein the integrated circuit device comprises a flash memory device and wherein the charge storing region comprises a floating gate of a cell of the flash memory device.

55. A memory cell including the gate structure of claim 46, the memory cell further comprising a common gate on a gate dielectric layer on the substrate and wherein the metal oxide dielectric layer extends along sidewalls of the common gate electrode and on a channel portion of the substrate proximate respective sides of the common gate and wherein the memory cell further includes sidewall gates on the metal oxide dielectric layer proximate the respective sides of the common gate and extending over the channel portion.

56. A memory cell including the gate structure of claim 46, the memory cell further comprising a channel region including a recess region and a step region adjacent the recess region extending between a source and a drain region in the substrate and wherein the metal oxide dielectric layer extends along the channel region including the recess region and the step region.

57. The memory cell of claim 56, wherein the recess region has a rounded portion.