Claims
- 1. A thin film hybrid substrate system containing integrated capacitors, inductors, and/or interconnects, comprising:
(a) a thin film hybrid substrate; (b) a lower electrode and interconnect layer formed on said thin film hybrid substrate, said layer further comprising a lower adhesive layer and an upper conducting layer having a sum total thickness less than or equal to 1.5 microns. (c) a dielectric layer deposited on top of the said patterned lower electrode and interconnect layer; and (d) an upper electrode layer formed on said dielectric layer; wherein
said upper conducting layer is approximately 0.25-1.40 microns thick.
- 2. The thin film hybrid substrate system of claim 1, wherein said lower adhesive layer is approximately 0.03 to 0.05 microns thick.
- 3. The thin film hybrid substrate system of claim 1, wherein said lower adhesive layer comprises chrome.
- 4. The thin film hybrid substrate system of claim 1, wherein said lower adhesive layer comprises titanium.
- 5. The thin film hybrid substrate system of claim 1, wherein said lower adhesive layer comprises titanium-tungsten.
- 6. The thin film hybrid substrate system of claim 1, wherein said upper conducting layer comprises silver.
- 7. The thin film hybrid substrate system of claim 1, wherein said upper conducting layer comprises aluminum.
- 8. The thin film hybrid substrate system of claim 1, wherein said upper conducting layer comprises gold.
- 9. The thin film hybrid substrate system of claim 1, wherein said upper conducting layer comprises copper.
- 10. The thin film hybrid substrate system of claim 1, wherein said lower electrode and interconnect layer further comprises silver.
- 11. The thin film hybrid substrate system of claim 1, wherein said lower electrode and interconnect layer further comprises aluminum.
- 12. The thin film hybrid substrate system of claim 1, wherein said lower electrode and interconnect layer further comprises gold.
- 13. The thin film hybrid substrate system of claim 1, wherein said lower electrode and interconnect layer further comprises copper.
- 14. The thin film hybrid substrate system of claim 1, wherein said lower electrode and interconnect layer is selected from the group consisting of tantalum (Ta), tungsten, titanium, nickel, molybdenum, platinum, palladium, and chromium.
- 15. The thin film hybrid substrate system of claim 1, wherein said dielectric layer is selectively patterned.
- 16. The thin film hybrid substrate system of claim 1, wherein said dielectric layer further comprises silicon nitride.
- 17. The thin film hybrid substrate system of claim 1, wherein said dielectric layer further comprises silicon dioxide.
- 18. The thin film hybrid substrate system of claim 1, wherein said dielectric layer further comprises silicon oxynitride.
- 19. The thin film hybrid substrate system of claim 1, wherein said dielectric layer further comprises aluminum oxide.
- 20. The thin film hybrid substrate system of claim 1, wherein said dielectric layer further comprises tantalum pentoxide.
- 21. The thin film hybrid substrate system of claim 1, wherein said dielectric layer further comprises a ferroelectric material.
- 22. The thin film hybrid substrate system of claim 21, wherein said ferroelectric material is BaTiO3.
- 23. The thin film hybrid substrate system of claim 21, wherein said ferroelectric material is SrTiO3.
- 24. The thin film hybrid substrate system of claim 21, wherein said ferroelectric material is PbZrO3.
- 25. The thin film hybrid substrate system of claim 21, wherein said ferroelectric material is PbTiO3.
- 26. The thin film hybrid substrate system of claim 21, wherein said ferroelectric material is LiNbO3.
- 27. The thin film hybrid substrate system of claim 21, wherein said ferroelectric material is Bi14Ti3O12.
- 28. The thin film hybrid substrate system of claim 1, wherein said dielectric layer further comprises polyimide.
- 29. The thin film hybrid substrate system of claim 1, wherein said dielectric layer further comprises benzocyclobutene.
- 30. The thin film hybrid substrate system of claim 1, wherein said substrate material is selected from the group consisting of alumina, beryllium oxide, fused silica, aluminum nitride, sapphire, ferrite, diamond, LTCC, and glass.
- 31. A thin film capacitor/inductor/interconnect method comprising:
(1) thinly metalizing a substrate with a lower electrode and interconnect layer formed on said thin film hybrid substrate, said layer further comprising a lower adhesive layer and an upper conducting layer having a sum total thickness of less than or equal to 1.5 microns; (2) applying/imaging photoresist and etching to form metal patterns on said substrate for lower capacitor electrodes and interconnect; (3) applying a thin dielectric layer to said metal patterns; (4) applying/imaging photoresist and etching to form contact holes in said dielectric layer and optionally selectively patterning said dielectric layer; (5) metalizing said substrate to make contact with said lower capacitor electrodes and interconnect; (6) applying/imaging photoresist and etching to form patterns for upper capacitor electrodes, inductors, and/or interconnect conductors; (7) optionally forming resistor elements by applying/imaging photoresist and etching a resistor layer on said substrate; wherein
said upper conducting layer is approximately 0.25-1.40 microns thick.
- 32. The thin film hybrid substrate method of claim 31, wherein said lower adhesive layer is approximately 0.03 to 0.05 microns thick.
- 33. The thin film hybrid substrate method of claim 31, wherein said lower adhesive layer comprises chrome.
- 34. The thin film hybrid substrate method of claim 31, wherein said lower adhesive layer comprises titanium.
- 35. The thin film hybrid substrate method of claim 31, wherein said lower adhesive layer comprises titanium-tungsten.
- 36. The thin film hybrid substrate method of claim 31, wherein said upper conducting layer comprises silver.
- 37. The thin film hybrid substrate method of claim 31, wherein said upper conducting layer comprises aluminum.
- 38. The thin film hybrid substrate method of claim 31, wherein said upper conducting layer comprises gold.
- 39. The thin film hybrid substrate method of claim 31, wherein said upper conducting layer comprises copper.
- 40. The thin film hybrid substrate method of claim 31, wherein said lower electrode and interconnect layer further comprises silver.
- 41. The thin film hybrid substrate method of claim 31, wherein said lower electrode and interconnect layer further comprises aluminum.
- 42. The thin film hybrid substrate method of claim 31, wherein said lower electrode and interconnect layer further comprises gold.
- 43. The thin film hybrid substrate method of claim 31, wherein said lower electrode and interconnect layer further comprises copper.
- 44. The thin film hybrid substrate method of claim 31, wherein said lower electrode and interconnect layer is selected from the group consisting of tantalum, tungsten, titanium, nickel, molybdenum, platinum, palladium, and chromium.
- 45. The thin film hybrid substrate method of claim 31, wherein said dielectric layer is selectively patterned.
- 46. The thin film hybrid substrate method of claim 31, wherein said dielectric layer further comprises silicon nitride.
- 47. The thin film hybrid substrate method of claim 31, wherein said dielectric layer further comprises silicon dioxide.
- 48. The thin film hybrid substrate method of claim 31, wherein said dielectric layer further comprises silicon oxynitride.
- 49. The thin film hybrid substrate method of claim 31, wherein said dielectric layer further comprises aluminum oxide.
- 50. The thin film hybrid substrate method of claim 31, wherein said dielectric layer further comprises tantalum pentoxide.
- 51. The thin film hybrid substrate method of claim 31, wherein said dielectric layer further comprises a ferroelectric material.
- 52. The thin film hybrid substrate method of claim 51, wherein said ferroelectric material is BaTiO3.
- 53. The thin film hybrid substrate method of claim 51, wherein said ferroelectric material is SrTiO3.
- 54. The thin film hybrid substrate method of claim 51, wherein said ferroelectric material is PbZrO3.
- 55. The thin film hybrid substrate method of claim 51, wherein said ferroelectric material is PbTiO3.
- 56. The thin film hybrid substrate method of claim 51, wherein said ferroelectric material is LiNbO3.
- 57. The thin film hybrid substrate method of claim 51, wherein said ferroelectric material is Bi14Ti3O12.
- 58. The thin film hybrid substrate method of claim 31, wherein said dielectric layer further comprises polyimide.
- 59. The thin film hybrid substrate method of claim 31, wherein said dielectric layer further comprises benzocyclobutene.
- 60. The thin film hybrid substrate method of claim 31, wherein said substrate material is selected from the group consisting of alumina, beryllium oxide, fused silica, aluminum nitride, sapphire, ferrite, diamond, LTCC, and glass.
- 61. The capacitor/inductor/interconnect product of the thin film fabrication method comprising:
(1) thinly metalizing a substrate with a lower electrode and interconnect layer formed on said thin film hybrid substrate, said layer further comprising a lower adhesive layer and an upper conducting layer having a sum total thickness of less than or equal to 1.5 microns; (2) applying/imaging photoresist and etching to form metal patterns on said substrate for lower capacitor electrodes and interconnect; (3) applying a thin dielectric layer to said metal patterns; (4) applying/imaging photoresist and etching to form contact holes in said dielectric layer and optionally selectively patterning said dielectric layer; (5) metalizing said substrate to make contact with said lower capacitor electrodes and interconnect; (6) applying/imaging photoresist and etching to form patterns for upper capacitor electrodes, inductors, and/or interconnect conductors; (7) optionally forming resistor elements by applying/imaging photoresist and etching a resistor layer on said substrate; wherein
said upper conducting layer is approximately 0.25-1.40 microns thick.
- 62. The capacitor/inductor/interconnect product of claim 61, wherein said lower adhesive layer is approximately 0.03 to 0.05 microns thick.
- 63. The capacitor/inductor/interconnect product of claim 61, wherein said lower adhesive layer comprises chrome.
- 64. The capacitor/inductor/interconnect product of claim 61, wherein said lower adhesive layer comprises titanium.
- 65. The capacitor/inductor/interconnect product of claim 61, wherein said lower adhesive layer comprises titanium-tungsten.
- 66. The capacitor/inductor/interconnect product of claim 61, wherein said upper conducting layer comprises silver.
- 67. The capacitor/inductor/interconnect product of claim 61, wherein said upper conducting layer comprises aluminum.
- 68. The capacitor/inductor/interconnect product of claim 61, wherein said upper conducting layer comprises gold.
- 69. The capacitor/inductor/interconnect product of claim 61, wherein said upper conducting layer comprises copper.
- 70. The capacitor/inductor/interconnect product of claim 61, wherein said lower electrode and interconnect layer further comprises silver.
- 71. The capacitor/inductor/interconnect product of claim 61, wherein said lower electrode and interconnect layer further comprises aluminum.
- 72. The capacitor/inductor/interconnect product of claim 61, wherein said lower electrode and interconnect layer further comprises gold.
- 73. The capacitor/inductor/interconnect product of claim 61, wherein said lower electrode and interconnect layer further comprises copper.
- 74. The capacitor/inductor/interconnect product of claim 61, wherein said lower electrode and interconnect layer is selected from the group consisting of tantalum, tungsten, titanium, nickel, molybdenum, platinum, palladium, and chromium.
- 75. The capacitor/inductor/interconnect product of claim 61, wherein said dielectric layer is selectively patterned.
- 76. The capacitor/inductor/interconnect product of claim 61, wherein said dielectric layer further comprises silicon nitride.
- 77. The capacitor/inductor/interconnect product of claim 61, wherein said dielectric layer further comprises silicon dioxide.
- 78. The capacitor/inductor/interconnect product of claim 61, wherein said dielectric layer further comprises silicon oxynitride.
- 79. The capacitor/inductor/interconnect product of claim 61, wherein said dielectric layer further comprises aluminum oxide.
- 80. The capacitor/inductor/interconnect product of claim 61, wherein said dielectric layer further comprises tantalum pentoxide.
- 81. The capacitor/inductor/interconnect product of claim 61, wherein said dielectric layer further comprises a ferroelectric material.
- 82. The capacitor/inductor/interconnect product of claim 81, wherein said ferroelectric material is BaTiO3.
- 83. The capacitor/inductor/interconnect product of claim 81, wherein said ferroelectric material is SrTiO3.
- 84. The capacitor/inductor/interconnect product of claim 81, wherein said ferroelectric material is PbZrO3.
- 85. The capacitor/inductor/interconnect product of claim 81, wherein said ferroelectric material is PbTiO3.
- 86. The capacitor/inductor/interconnect product of claim 81, wherein said ferroelectric material is LiNbO3.
- 87. The capacitor/inductor/interconnect product of claim 81, wherein said ferroelectric material is Bi14Ti3O12.
- 88. The capacitor/inductor/interconnect product of claim 61, wherein said dielectric layer further comprises polyimide.
- 89. The capacitor/inductor/interconnect product of claim 61, wherein said dielectric layer further comprises benzocyclobutene.
- 90. The capacitor/inductor/interconnect product of claim 61, wherein said substrate material is selected from the group consisting of alumina, beryllium oxide, fused silica, aluminum nitride, sapphire, ferrite, diamond, LTCC, and glass.
- 91. A power supply bypass/decoupling/filter network system fabricated using array elements comprising integrated capacitors, inductors, and/or interconnects formed on a thin film hybrid substrate system comprising:
(a) a thin film hybrid substrate; (b) a lower electrode and interconnect layer formed on said thin film hybrid substrate, said layer further comprising a lower adhesive layer and an upper conducting layer having a sum total thickness less than or equal to 1.5 microns. (c) a dielectric layer deposited on top of the said patterned lower electrode and interconnect layer; and (d) an upper electrode layer formed on said dielectric layer; wherein
said upper conducting layer is approximately 0.25-1.40 microns thick.
- 92. A phased antenna array system fabricated using array elements comprising integrated capacitors, inductors, and/or interconnects formed on a thin film hybrid substrate system comprising:
(a) a thin film hybrid substrate; (b) a lower electrode and interconnect layer formed on said thin film hybrid substrate, said layer further comprising a lower adhesive layer and an upper conducting layer having a sum total thickness less than or equal to 1.5 microns. (c) a dielectric layer deposited on top of the said patterned lower electrode and interconnect layer; and (d) an upper electrode layer formed on said dielectric layer; wherein
said upper conducting layer is approximately 0.25-1.40 microns thick.
- 93. The phased antenna array system of claim 92, wherein said array elements further comprise an inductor/capacitor bypass/decoupling/filter network fabricated using said integrated capacitors, inductors, and/or interconnects of claim 91.
- 94. The phased antenna array system of claim 92, wherein said array elements are active.
- 95. The phased antenna array system of claim 94, wherein said array elements further comprise an inductor/capacitor bypass/decoupling/filter network fabricated using said integrated capacitors, inductors, and/or interconnects of claim 91.
- 96. The phased antenna array system of claim 92, wherein said array elements are passive.
- 97. The phased antenna array system of claim 96, wherein said array elements further comprise an inductor/capacitor bypass/decoupling/filter network fabricated using said integrated capacitors, inductors, and/or interconnects of claim 91.
CROSS REFERENCE TO RELATED APPLICATIONS
[0001] This patent application is a continuation-in-part Patent Application for “INTEGRATED THIN FILM CAPACITOR/INTERCONNECT SYSTEM AND METHOD”, Ser. No. 09/960,796, docket USI-2001-002, filed Sep. 21, 2001. Applicants incorporate this parent application by reference and claim benefit pursuant to 35 U.S.C. § 120 for this previously filed patent application.
[0002] Applicant claims benefit pursuant to 35 U.S.C. § 119 and hereby incorporates by reference Provisional Patent Application for “INTEGRATED THIN FILM CAPACITOR/INTERCONNECT SYSTEM AND METHOD”, S/No. 60/234,135, docket USI-001PP, filed Sep. 21, 2000, and submitted to the USPTO with Express Mail Label EM267139965US.
Continuation in Parts (1)
|
Number |
Date |
Country |
Parent |
09960796 |
Sep 2001 |
US |
Child |
10686128 |
Oct 2003 |
US |