Patent Application
20090310320
Disclosed embodiments relate to semiconductive apparatus, packages, and processes of making them.
In order to understand the manner in which embodiments are obtained, a more particular description of various embodiments briefly described above will be rendered by reference to the appended drawings. These drawings depict embodiments that are not necessarily drawn to scale and are not to be considered to be limiting in scope. Some embodiments will be described and explained with additional specificity and detail through the use of the accompanying drawings in which:
a is a cross-section elevation of a semiconductive integrated circuit package according to an embodiment;
b is a cross-section elevation of a semiconductive integrated circuit package after further processing of the package depicted in
c is a cross-section elevation of a semiconductive integrated circuit package after further processing of the package depicted in
d is a cross-section elevation of a semiconductive integrated circuit package after further processing of the package depicted in
e is a cross-section elevation of a semiconductive integrated circuit package after further processing of the package depicted in
f is a cross-section elevation of a semiconductive integrated circuit package after further processing of the package depicted in
a is a detail cross-section elevation depicted in
b is a detail cross-section elevation depicted in
A low-profile solder grid array is formed on a mounting substrate by allowing a solder paste to reflow into low-profile solder bumps. The low-profile solder grid array is mounted to a board by contacting each low-profile solder bump to a low-profile solder paste on the board. The low-profile solder paste is then reflowed to bond with the low-profile solder bump.
Reference will now be made to the drawings wherein like structures may be provided with like suffix reference designations. In order to show the structures of various embodiments most clearly, the drawings included herein are diagrammatic representations of integrated circuit structures. Thus, the actual appearance of the fabricated structures, for example in a photomicrograph, may appear different while still incorporating the claimed structures of the illustrated embodiments. Moreover, the drawings show only the structures necessary to understand the illustrated embodiments. Additional structures known in the art have not been included to maintain the clarity of the drawings.
a is a cross-section elevation of a semiconductive integrated circuit package 100 according to an embodiment. A flip-chip package 110 includes a semiconductive integrated circuit 112 (hereinafter “chip”), an underfill material 114, a plurality of solder balls, one of which is indicated by reference numeral 116, and a mounting substrate 118. The chip 112 is electrically connected to the mounting substrate 118 by the plurality of solder balls 116. In an embodiment, the mounting substrate 118 is configured with a plurality of bond pads, one of which is indicated by reference numeral 120. The bond pads 120 may have a surface finish 122 such as a metal that is more noble than the metal of the bond pad 120. For an example embodiment, the bond pads 120 are copper metal and the surface finish 122 is gold metal. In an example embodiment, the bond pads 120 are copper metal and the surface finish 122 is platinum-group metal. In an example embodiment, the bond pads 120 are copper metal and the surface finish 122 is nickel-palladium-gold alloy. During processing, a mask 124 is superimposed over the mounting substrate 118 to expose the bond pads 120. A solder paste 126 is patterned onto the bond pads 120 by use of a squeegee 128 by way of non-limiting example. In any event the solder paste 126 is imposed onto the bond pads 120 to form a solder paste array 130. In an embodiment, the solder paste 126 is derived from lead free metal powders of tin (Sn). In an embodiment, the solder paste 126 is a tin-silver (Sn—Ag) composition. In an embodiment, the solder paste 126 is a tin-silver-copper (Sn—Ag—Cu) composition such as SAC305 (which is Sn96.5/Ag3.0/Cu0.5). In an embodiment, the solder paste 126 is a Sn—Ag—Cu composition such as SAC405 (which is Sn3.8Ag0.7Cu). In an embodiment a tin-antimony (Sn—Sb) solder paste 126 is used. In an embodiment, the spolder patst 126 is an eutectic powder tin-lead (Sn—Pb).
In an embodiment, the solder paste 126 has an average metal particle diameter in a range from about 5 μm to about 45 μm.
b is a cross-section elevation of a semiconductive integrated circuit package 101 after further processing of the package 100 depicted in
In an embodiment, the structures represented by numeral 130 are electrical connectors such as metal studs. Although the aspect ratio (Z-dimension divided by X-dimension) is less than one, the structures 130 may be called contact studs. In this embodiment, the structure represented by numeral 122 may be a wetting layer for the stud 120. For example, the wetting layer 122 may be a solder paste embodiment and the stud 130 is a copper stud. Hereinafter, the structure 130 will be referred to as a solder paste array 130 unless explicitly taught otherwise.
In an embodiment, individual occurrences in the solder paste array 130 may have varying diameters depending upon location. For example bond pads 120 near the periphery of the mounting substrate 118 may have a first diameter 160 that is larger than bond pads nearer the center thereof that have a second diameter 162. This variation in bond pad size and the corresponding low-profile solder bump may allow for useful stress resistance at the periphery where thermal stresses and physical shocks may be experienced with greater intensity.
c is a cross-section elevation of a semiconductive integrated circuit package 102 after further processing of the package 101 depicted in
d is a cross-section elevation of a semiconductive integrated circuit package 103 after further processing of the package 102 depicted in
In an embodiment, the aspect ratio is based upon the 0.6 mm pitch embodiment, where the pitch is 1.5 times the width 234 of the bond pad 120. Consequently, where each low-profile solder bump 131 has an aspect ratio of 170 μm divided by 0.4 mm, or an aspect ratio of about 0.425. In an embodiment, where each low-profile solder bump 131 has an aspect ratio of 200 μm divided by 0.4 mm, or an aspect ratio of about 0.5. In an embodiment where the bond pad 120 has a diameter of 300 μm and the pitch is 0.6 mm, the aspect ratio with a 200 μm bump standoff is 0.67.
In an embodiment, the aspect ratio is based upon the 0.5 mm pitch embodiment, where the pitch 236 is 1.5 times the width 234 of the bond pad 120. Consequently, where each low-profile solder bump 131 has an aspect ratio of 100 μm divided by 333 mm, or an aspect ratio of about 0.3. In an embodiment where the bond pad 120 has a diameter of 200 μm and the pitch is 0.5 mm, the aspect ratio with a 100 μm bump standoff is 0.5.
Other pitches may be applied to the illustrated embodiments. In an embodiment, the pitch 236 is 1.33 times the width 234 of the bond pad 120. In an embodiment, the pitch 236 is 1.25 times the width 234 of the bond pad 120. In an embodiment, the pitch 236 is equal to the width 234 of the bond pad 120. In an embodiment, the pitch 236 is 1.67 times the width 234 of the bond pad 120. In an embodiment, the pitch 236 is double the width 234 of the bond pad 120.
e is a cross-section elevation of a semiconductive integrated circuit package 104 after further processing of the package 103 depicted in
The board 138 also includes a solder paste array. Four occurrences of a board solder paste array 144 are illustrated. In a process embodiment, the reflowed low-profile solder bump array 131 is being mated to corresponding occurrences of the board solder paste array 144. In a process embodiment, a process of assembling the a solder grid array 131 of the microelectronic device package 110 is demonstrated such that the low-profile solder bumps 131 are being mated to a board solder paste array 144 that is disposed on the printed wiring board substrate 138. The assembly of a plurality of reflowed low-profile solder bumps 131 to a board solder paste array 144 may be accomplished in this illustrated embodiment.
f is a cross-section elevation of a semiconductive integrated circuit package 105 after further processing of the package 104 depicted in
a is a detail 300 of the cross-section elevation depicted in
a also depicts the board solder paste 144 in direct contact with the low-profile solder bump 131. The combined board solder paste 144 and low-profile solder bump 131 exhibit a package bump height 346 and a package bump width 348. The package bump width 348 is defined as the characteristic width 348 or diameter of the bond pads 120 and 140. An aspect ratio for each package bump is given as package bump height 346 divided by package bump width 348.
b is a detail 300 of the cross-section elevation depicted in
In an embodiment, the board bump 145 has a chemical composition that is distinct from the low-profile solder bump 131. As a result of reflow of the board solder paste 144, useful wetting contact is made between the board bump 145 and the low-profile solder bump 131 without significant mass transfer.
In an embodiment, the low-profile solder bump 131 has been diluted by incursion of reflowed materials of the board bump 145. As a result of reflow of the board solder paste 144, components of the board solder paste 144 dissolve into the low-profile solder bump 131 based upon solder-phase thermodynamics. Consequently, the solder chemistry of the low-profile solder bump 131 is significantly different from the solder chemistry of the solder paste 130. Similarly, the solder chemistry of the board bump 145 is significantly different from the solder chemistry of the board solder paste 144. And further, the solder chemistry of the low-profile solder bump 131 and the board bump 145 are the same.
In an embodiment, the low-profile solder bump 131 has been only partially infiltrated by reflowed materials of the board bump 145. As a result of reflow of the board solder paste 144, components of the board solder paste 144 dissolve into the low-profile solder bump 131 based upon solder-phase thermodynamics. The degree of dissolution thereof, however, is limited such that the low-profile solder bump 131 near the residual surface finish 123 is significantly unaffected by the materials of the board bump 145. Similarly, the degree of dissolution of the materials of the board bump 145 into the low-profile solder bump 131 is limited such that the board bump 145 has a chemistry similar to the board solder paste 144 near the residual surface finish 143. In this embodiment, a transition zone 354 is illustrated as a dashed line between the low-profile solder bump 131 and the board bump 145. The extent of the transition zone represents a regional dilution of the low-profile solder bump 131 and the board bump 145. The low-profile solder bump 131 and the board bump 145 may be varied based upon specific reflow conditions and solder chemistries of the low-profile solder bump 131 and the board bump 145.
A package-to-bond pad width standoff ratio is defined as the cumulative height 346 of the bumps 131 and 145 divided by the bond pad width 348. This ratio hereinafter is referred to as the standoff ratio.
In an embodiment based upon a 0.6 mm pitch embodiment where the pitch is 1.5 times the width of the bond pad 120, the standoff ratio is about 0.425. In a 0.425 standoff ratio embodiment, the cumulative height is 170 μm. In an embodiment based upon a 0.6 mm pitch embodiment where the pitch is 1.5 times the width of the bond pad 120, the standoff ratio is about 0.5. In a 0.400 standoff ratio embodiment, the cumulative height is 200 μm. In an embodiment based upon a 0.6 mm pitch embodiment where the pitch is 1.5 times the width of the bond pad 120, the standoff ratio is about 0.3.
In an embodiment based upon a 0.5 mm pitch embodiment where the pitch is 1.5 times the width of the bond pad 120, the standoff ratio about 0.3. In a 0.3 standoff ratio embodiment, the cumulative height is 100 μm.
In an embodiment, the standoff ratio is achieved without solder bumps. In an embodiment, the height 346 of the structure is achieved with a conductive stud that is in direct contact to each of the bond pads 120 and 140. In an embodiment, the height 346 is achieved by a conductive stud that is electrically connected by a solder film. In
Whether the standoff ratio is achieved with solder pastes or with studs, the electrical structures achieved by these processes may be referred to as standoff contacts.
At 410, the process includes forming a solder paste array on a microelectronic device mounting substrate. A non-limiting example is depicted in
At 420, the process includes reflowing the solder paste array to form a low-profile solder bump. A non-limiting example is depicted in
At 430, the process includes mating the low-profile solder bump array to a board solder paste array on a printed wiring board. A non-limiting example is depicted in
At 440, the process includes reflowing the board solder paste array against the low-profile solder bump array to form a low standoff-ratio package with low-profile standoff contacts. A non-limiting example is depicted at
The integrated circuit 510 is electrically coupled to the system bus 520 and includes any circuit, or combination of circuits according to an embodiment. In an embodiment, the integrated circuit 510 includes a processor 512 that can be of any type. As used herein, the processor 512 may mean any type of circuit such as, but not limited to, a microprocessor, a microcontroller, a graphics processor, a digital signal processor, or another processor. Other types of circuits that can be included in the integrated circuit 510 are a custom circuit or an ASIC, such as a communications circuit 514 for use in wireless devices such as cellular telephones, pagers, portable computers, two-way radios, and similar electronic systems. In an embodiment, the processor 510 includes on-die memory 516 such as SRAM. In an embodiment, the processor 510 includes on-die memory 516 such as eDRAM.
In an embodiment, the electronic system 500 also includes an external memory 840 that in turn may include one or more memory elements suitable to the particular application, such as a main memory 542 in the form of RAM, one or more hard drives 544, and/or one or more drives that handle removable media 546, such as diskettes, compact disks (CDs), digital video disks (DVDs), flash memory keys, and other removable media known in the art.
In an embodiment, the electronic system 500 also includes a display device 550, an audio output 560. In an embodiment, the electronic system 500 includes a controller 570, such as a keyboard, mouse, trackball, game controller, microphone, voice-recognition device, or any other device that inputs information into the electronic system 500.
As shown herein, the integrated circuit 510 can be implemented in a number of different embodiments, including an electronic package, an electronic system, a computer system, one or more methods of fabricating an integrated circuit, and one or more methods of fabricating an electronic assembly that includes the integrated circuit and the low-profile standoff array integrated circuit die package as set forth herein in the various embodiments and their art-recognized equivalents. The elements, materials, geometries, dimensions, and sequence of operations can all be varied to suit particular packaging requirements.
The Abstract is provided to comply with 37 C.F.R. §1.72(b) requiring an abstract that will allow the reader to quickly ascertain the nature and gist of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.
In the foregoing Detailed Description, various features are grouped together in a single embodiment for the purpose of streamlining the disclosure. This method of disclosure is not to be interpreted as reflecting an intention that the claimed embodiments of the invention require more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive subject matter lies in less than all features of a single disclosed embodiment. Thus the following claims are hereby incorporated into the Detailed Description, with each claim standing on its own as a separate preferred embodiment.
It will be readily understood to those skilled in the art that various other changes in the details, material, and arrangements of the parts and method stages which have been described and illustrated in order to explain the nature of this invention may be made without departing from the principles and scope of the invention as expressed in the subjoined claims.
