Claims
- 1. An improvement in a semiconductor memory having a dummy bit line, DMY1, having memory cells, having a sense time when said memory cells will be read, and simulating the worst case within said memory for reading a logical one, comprising:
- means for providing a plurality of selectable capacitors; and
- programmable means for selectively coupling said capacitors to said dummy bit line DMY1 so that sense time within said semiconductor memory is programmably varied, said dummy bit line, DMY1, being coupled to said semiconductor memory to determine said sense time when memory cells within said semiconductor memory will be read,
- wherein said programmable means comprises a plurality of links, said links having a programmably determined conductivity, one of said programmable links being coupled to each one of said capacitors to selectively couple said corresponding capacitor to said dummy bit line, DMY1.
- 2. An improvement in a semiconductor memory of the type having a dummy bit lines simulating worst cases for reading a logical one and for reading a logical zero, the improvement comprising:
- means for adjusting a rate of voltage change in a logical one dummy bit line;
- means for dampening noise in a logical zero dummy bit line; and
- means for controlling a read time cycle of the semiconductor memory in response to a comparison between the logical one dummy bit line and the logical zero dummy bit line.
- 3. The improvement of claim 2, wherein the means for adjusting comprises:
- means for providing a plurality of selectable capacitors; and
- programmable means for selectively coupling said capacitors to said logical one dummy bit line.
- 4. The improvement of claim 2, wherein the means for dampening comprises:
- means for providing a plurality of selectable capacitors; and
- programmable means for selectively coupling said capacitors to said logical zero dummy bit line.
RELATED CASES
This application is a division of application Ser. No. 08/721,342 filed Sep. 26,1996 which application is now; U.S. Pat. No. 5,732,035, which application is a continuation-in-part of U.S. patent application, Ser. No. 07/538,185, filed Jun. 14, 1990, now abandoned, entitled Improved Semiconductor Read-Only VLSI Memory, which is incorporated herein by reference.
US Referenced Citations (1)
Number |
Name |
Date |
Kind |
4658382 |
Tran et al. |
Apr 1987 |
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Divisions (1)
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Number |
Date |
Country |
Parent |
721342 |
Sep 1996 |
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Continuation in Parts (1)
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Number |
Date |
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Parent |
538185 |
Jun 1990 |
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