Memory module

Abstract

A memory module having an array of memory devices, mounted thereon, that operate synchronously with a clock signal, wherein provisions are made to be able to fine-tune the clock phase in accordance with its use conditions. The memory module, having an array of memory devices mounted thereon that operate synchronously with the clock signal, includes; a phase-locked loop circuit which produces an output clock signal adjusted so that the phase of a feedback signal obtained by passing the output clock signal through a feedback loop matches the phase of an input clock signal; and a switching unit which selectively changes a load in the feedback loop in accordance with an external signal.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

The features and advantages of the present invention will be apparent from the following description with reference to the accompanying drawings, in which:

FIG. 1 is a diagram showing the general configuration of a DIMM;

FIG. 2 is a circuit diagram showing how a clock is distributed within the DIMM;

FIG. 3 is a diagram showing the internal configuration of a PLL-based clock driver;

FIGS. 4A and 4B are diagrams for explaining different internal configurations for the DIMM;

FIG. 5 is a diagram for explaining a different method of mounting the DIMM in a host apparatus;

FIGS. 5A, 5B, 6C, 6D, and 6E are timing charts showing the relationships among an input clock CLK to the DIMM, an input clock RCK to SDRAM, and output data DQS from the DIMM;

FIGS. 7A and 7B are diagrams for explaining how memory data are received by a controller;

FIG. 8 is a diagram showing the circuit configuration of a DIMM according to one embodiment of the present invention;

FIG. 9 is a diagram for explaining a DIMM according to another embodiment of the present invention; and

FIG. 10 is a diagram for explaining the effect that can be achieved by making a reference voltage variable.

Claims

1. A memory module having an array of memory devices mounted thereon that operate synchronously with a clock signal, comprising: a phase-locked loop circuit which produces an output clock signal adjusted so that the phase of a feedback signal obtained by passing said output clock signal through a feedback loop matches the phase of an input clock signal; anda switching unit which selectively changes a load in said feedback loop in accordance with an external signal.

2. A memory module as claimed in claim 1, wherein said switching unit changes a capacitance value in said feedback loop.

3. A memory module as claimed in claim 1, wherein said switching unit changes a resistance value in said feedback loop.

4. A memory module as claimed in claim 1, wherein said switching unit changes a capacitance value and a resistance value in said feedback loop.

5. A memory module as claimed in claim 1, wherein said switching unit selectively changes said load in said feedback loop in accordance with a value that is set in a register by a controller.

6. A memory module as claimed in claim 5, wherein said register is mounted on said memory module.

7. A memory module as claimed in claim 1, wherein said clock signal is implemented as a differential signal, and said load in said feedback loop is formed by a resistor and a capacitor connected in parallel between two lines.

8. A memory module having an array of memory devices mounted thereon that operate synchronously with a clock signal, comprising; a phase-locked loop circuit which produces an output clock signal adjusted so that the phase of a feedback signal obtained by passing said output clock signal through a feedback loop matches the phase of an input clock signal; anda unit which, in accordance with an external signal, changes a reference level based on which a phase comparator circuit in said phase-locked loop circuit judges the value of said feedback signal.