Claims
- 1. A method of connecting a solder contact to a metal layer on a semiconductor substrate, said method comprising the steps of:
- a) depositing a layer of a refractory metal on a top surface of said metal layer, said refractory metal layer selected from the group consisting of titanium, hafnium and zirconium and having a thickness of about 300-1500 .ANG.;
- b) depositing a layer of nickel on said refractory metal layer, said nickel layer having a thickness of about 400-1000 .ANG.;
- c) depositing a layer of copper on said nickel layer, said copper layer having a thickness of about 2000 to 20000 .ANG.; and
- d) applying a solder layer onto said copper layer.
- 2. The method of claim 1 wherein the step of depositing a layer of nickel overlaps a portion of the step of depositing a layer of refractory metal such that a portion of each of the refractory metal layer and of the nickel layer is comprised of commingled refractory metal and nickel.
- 3. The method of claim 1 wherein the step of depositing a layer of copper overlaps a portion of the step of depositing a layer of nickel such that a portion of each of the nickel layer and of the copper layer is comprised of commingled nickel and copper.
- 4. The method of claim 1 wherein said deposition in steps (a), (b), and (c) comprises evaporation.
- 5. The method of claim 1 wherein said application in step (d) comprises evaporation.
- 6. The method of claim 1 further comprising depositing a layer of gold having a thickness of about 700-1100 .ANG. on said copper layer, wherein said solder layer is then deposited on said gold layer overlying said copper layer.
- 7. The method of claim 1 wherein said layers in steps (a) , (b), and (c) are defined by a liftoff photo process.
- 8. The method of claim 7 wherein said liftoff photo process comprises a modified image reversal process.
- 9. The method of claim 1 wherein said layers in steps (a), (b), and (c) are defined by reactive ion etching.
- 10. A method of producing a semiconductor device, said method comprising the steps of:
- a) applying a metal layer on a top surface of a semiconductor chip;
- b) applying an insulation layer on said metal layer, such that said insulation layer includes an opening therein to said metal layer;
- c) depositing a layer of a refractory metal on said insulation layer such that said refractory metal layer occupies said opening in said insulation layer and contacts said metal layer, said refractory metal selected from the group consisting of titanium, hafnium and zirconium and having a thickness of about 300-1500 .ANG.;
- d) depositing a layer of nickel on said refractory metal layer, said nickel layer having a thickness of about 400 to 1000 .ANG.;
- e) depositing a layer of copper on said nickel layer, said copper layer having a thickness of about 2000-20000 .ANG.; and
- f) applying a solder layer on said copper layer.
- 11. The method of claim 10 wherein the step of depositing a layer of nickel overlaps a portion of the step of depositing a layer of refractory metal such that a portion of each of the refractory metal layer and of the nickel layer is comprised of commingled refractory metal and nickel.
- 12. The method of claim 10 wherein the step of depositing a layer of copper overlaps a portion of the step of depositing a layer of nickel such that a portion of each of the nickel layer and of the copper layer is comprised of commingled nickel and copper.
- 13. The method of claim 10 wherein said application in steps (a) and (b) comprises sputter deposition.
- 14. The method of claim 10 wherein said deposition in steps (c), (d), and (e) comprises evaporation.
- 15. The method of claim 10 wherein said application in step (f) comprises evaporation.
- 16. The method of claim 10 wherein said opening in said insulation layer is formed by selectively etching said insulation layer overlying said metal layer without etching said metal layer.
- 17. The method of claim 10 further comprising depositing a layer of gold having a thickness of about 700-1100 .ANG. on said copper layer, wherein said solder layer is then deposited on said gold layer overlying said copper layer.
- 18. A method of preventing degradation at an interface formed between sequentially deposited layers of a refractory metal and copper in a semiconductor device, said method comprising the steps of:
- a) depositing said layer of a refractory metal onto a metal layer in the semiconductor device, the refractory metal being selected from the group consisting of titanium, hafnium and zirconium;
- b) depositing a layer of nickel having a thickness of about 400-1000 .ANG. onto the layer of a refractory metal, wherein the deposition of the layer of nickel begins prior to the completion of the deposition of the layer of refractory metal; and
- c) depositing a layer of copper onto the layer of nickel, wherein the deposition of the copper begins prior to the completion of the deposition of the layer of nickel.
- 19. The method of claim 18 wherein said degradation comprises chlorine corrosion.
- 20. The method of claim 18 wherein said refractory metal is Ti.
Parent Case Info
This application is a continuation of U.S. Pat. No. 08/433,276 filed May 2, 1995, now abandoned, which was a division of U.S. Pat. No. 08/182,310 filed Jan. 14, 1994, now issued as U.S. Pat. No. 5,457,345, which itself was a continuation of 07/881,097 filed May 11, 1992, now abandoned.
US Referenced Citations (14)
Foreign Referenced Citations (4)
| Number |
Date |
Country |
| 29 30 779 |
Feb 1980 |
DEX |
| 56-37624 |
Apr 1981 |
JPX |
| 58-15254 |
Jan 1983 |
JPX |
| 60-119749 |
Jun 1985 |
JPX |
Non-Patent Literature Citations (3)
| Entry |
| Wolf, et al., Silicon Processing, Lattice Press, 1986, vol. 1, pp. 535-536. |
| Ghandhi, S.K., VLSI Fabrication Principles, 1983, John Wiley & Sons, pp. 437-438, 1983. |
| L.F. Miller, IBM Technical Disclosure Bulletin, vol. 16, No. 1, p. 39 (Jun. 1973). |
Divisions (1)
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Number |
Date |
Country |
| Parent |
182310 |
Jan 1994 |
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Continuations (2)
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Number |
Date |
Country |
| Parent |
433276 |
May 1995 |
|
| Parent |
881097 |
May 1992 |
|