Claims
- 1. A semiconductor device, comprising:
an array of lateral transistors formed on a trench wall of a trench in a silicon wafer, wherein the silicon wafer has a top surface in a (100) crystal plane orientation and the trench wall has a (110) crystal plane orientation, and wherein each lateral transistor includes:
a first conductive region in a first portion of the trench wall; a second conductive region in a second portion of the trench wall; and a third conductive region in a third portion of the trench wall, such that the third conductive region is between the first and second conductive regions and wherein each lateral transistor is configured to conduct an electrical current between the first conductive regions and the second conductive region in a <110> direction; and a wordline coupled to a gate of each lateral transistor formed on the trench wall of the trench of the silicon wafer.
- 2. The semiconductor device of claim 1, wherein the silicon wafer includes a Silicon On Insulator (SOI) material.
- 3. The semiconductor device of claim 1, wherein each lateral transistor configured to conduct the electrical current in the <110> direction includes each lateral transistor being configured to conduct an electrical current parallel to a top surface of the silicon wafer.
- 4. The semiconductor device of claim I, wherein the third conductive region in each lateral transistor includes a channel region.
- 5. A semiconductor device, comprising:
a first conductive n-type region in a trench of a silicon wafer such that the first conductive n-type region is lateral to a trench wall of the trench, wherein the trench wall has a (110) crystal plane orientation; a second conductive n-type region in the trench such that the second conductive n-type region is lateral to the trench wall; and a conductive p-type region in the trench such that the conductive p-type region is lateral to the trench wall and located between the first and second conductive n-type regions, wherein the semiconductor device is designed to conduct an electrical current between the first and second conductive p-type regions in a direction parallel to a top surface of the silicon wafer.
- 6. The semiconductor device of claim 5, wherein the silicon wafer has a top surface having a (100) crystal plane orientation.
- 7. A semiconductor device, comprising:
a number of trenches formed in a silicon wafer; and a number of spaced MOSFETs in each trench, wherein each MOSFET includes:
a first conductive p-type region in a trench of the silicon wafer such that the first conductive p-type region is lateral to a trench wall of the trench, wherein the trench wall has a (110) crystal plane orientation; a second conductive p-type region in the trench such that the second conductive p-type region is lateral to the trench wall; and a conductive n-type region in the trench such that the conductive n-type region is lateral to the trench wall and between the first and second conductive p-type regions, wherein an electrical current is capable of flowing between the first and second conductive p-type regions in a <110> direction.
- 8. The semiconductor device of claim 7, wherein the silicon wafer includes a bulk silicon material.
- 9. The semiconductor device of claim 7, wherein the silicon wafer has a top surface with a (100) crystal plane orientation.
- 10. The semiconductor device of claim 7, wherein each MOSFET includes a gate which opposes the conductive n-type region.
- 11. The semiconductor device of claim 10, wherein each MOSFET includes a gate oxide separating the gate and the conductive n-type region.
- 12. The semiconductor device of claim 11, further including a wordline coupling together the gates on each MOSFET in each trench.
- 13. An electronic system comprising:
a processor; and an integrated circuit coupled to the processor, wherein the integrated circuit is formed on a silicon wafer, and wherein the silicon wafer includes:
a trench wall having a (110) crystal plane orientation; and a semiconductor device lateral to the trench wall, wherein the semiconductor device is capable of conducting an electrical current in a <110> direction.
- 14. The electronic system of claim 13, wherein the processor and the integrated circuit are formed on the same silicon wafer
- 15. The electronic system of claim 13, wherein a top surface of the silicon wafer has a (100) crystal plane orientation.
- 16. The electronic system of claim 13, wherein the silicon wafer includes a bulk silicon material.
- 17. The electronic system of claim 13, wherein the semiconductor device includes a p-channel Metal Oxide Semiconductor Field Effect Transistor (p-MOSFET) device.
- 18. An electronic system comprising:
a processor; and a semiconductor device coupled to the processor, the semiconductor device including:
a first conductive region of a first type in a trench of a silicon wafer such that the first conductive region of the first type is lateral to a trench wall of the trench, wherein the trench wall has a (110) crystal plane orientation; a second conductive region of the first type in the trench such that the second conductive region of the first type is lateral to the trench wall; and a third conductive region of a second type in the trench such that the third conductive region of the second type is lateral to the trench wall and between the first and second conductive regions of the first type, wherein an electrical current is capable of flowing between the first and second conductive regions of the first type in a <110> direction.
- 19. The electronic system of claim 18, wherein the third conductive region of the second type includes a channel of a Metal Oxide Semiconductor Field Effect Transistor (MOSFET) device.
- 20. The electronic system of claim 18, wherein the first type is an n-type.
- 21. The electronic system of claim 18, wherein the second type is an p-type.
- 22. The electronic system of claim 18, wherein the silicon wafer has a top surface having a (100) crystal plane orientation.
- 23. An electronic system comprising:
a processor; a memory coupled to the processor, wherein the memory further includes:
an array of lateral transistors formed on a trench wall of a trench in a silicon wafer, wherein the silicon wafer has a top surface with a (100) crystal plane orientation and the trench wall has a (110) crystal plane orientation; and wherein each lateral transistor in the array of lateral transistors includes:
a first conductive region in a first portion of the trench, such that the first conductive region is lateral to the trench wall; a second conductive region in a second portion of the trench, such that the second conductive region is lateral to the trench wall; and a third conductive region in a third portion of the trench, such that the third conductive region is lateral to the trench wall and between the first and second conductive regions and wherein an electrical current is capable of flowing between the first conductive region and the second conductive region in a <110> direction.
- 24. The electronic system of claim 23, wherein the memory includes a dynamic random access memory.
- 25. The electronic system of claim 23, wherein the silicon wafer includes a Silicon On Insulator (SOI) material.
- 26. The electronic system of claim 23, wherein each lateral transistor includes a gate which opposes the third conductive region.
- 27. The electronic system of claim 23, wherein each lateral transistor includes a gate oxide separating the gate and the third conductive region.
- 28. The electronic system of claim 26, further including a wordline coupling together the gates of the lateral transistors.
- 29. A semiconductor device, comprising:
a layer of conductive material of a first type; at least one trench formed in the layer of conductive material, the at least one trench including a trench wall; and at least one semiconductor device formed laterally to the trench wall, the at least one semiconductor device comprising:
a first conductive region of a second type formed laterally to the trench wall; a second conductive region of the second type formed laterally to the trench wall; and a third conductive region of the layer of conductive material disposed laterally to the trench wall and separating the first and second conductive regions to provide a channel to conduct electrical current between the first and second conductive regions.
- 30. The semiconductor device of claim 29, wherein the first and second conductive regions are formed by at least one of rapid thermal annealing, ion implantation, angled ion implantation, and chemical vapor deposition.
- 31. The semiconductor device of claim 29, wherein the at least one semiconductor device is one of an n-channel semiconductor device or a p-channel semiconductor device.
- 32. A semiconductor device, comprising:
a substrate; a layer of conductive material of a first type formed on the substrate; at least one trench formed in the layer of conductive material and including trench walls substantially perpendicular to a plane of the substrate; and at least one semiconductor device formed laterally to at least one of the trench walls, the at least one semiconductor device comprising:
a first conductive region of a second type formed laterally to the at least one trench wall; a second conductive region of the second type formed laterally to the at least one trench wall; and a third conductive region of the layer of conductive material disposed laterally to the at least one trench wall and separating the first and second conductive regions to permit electrical current to be conducted between the first and second conductive regions.
- 33. A semiconductor device, comprising:
a layer of conductive material of a first type; at least one trench formed in the layer of conductive material, the at least one trench including a trench wall having a (110) crystal plane orientation; and at least one semiconductor device formed laterally to the trench wall, the at least one semiconductor device comprising:
a first conductive region of a second type formed laterally to the trench wall; a second conductive region of the second type formed laterally to the trench wall; and a third conductive region of the layer of conductive material disposed laterally to the trench wall and separating the first and second conductive regions to permit electrical current to be conducted in a <110> direction between the first and second conductive regions.
- 34. A semiconductor device, comprising:
a substrate; a layer of conductive material of a first type formed on the substrate; at least one trench formed in the layer of conductive material and including a trench wall substantially perpendicular to a top surface of the substrate and including a (110) crystal plane orientation; and at least one semiconductor device formed in a plane defined by the trench wall, the at least one semiconductor device comprising:
a first conductive region of a second type formed in the plane of the trench wall; a second conductive region of the second type formed in the plane of the trench wall; and a third conductive region of the layer of conductive material disposed in the plane of the trench wall and separating the first and second conductive regions to permit electrical current to be conducted in a <110> direction.
- 35. A semiconductor device, comprising:
a layer of conductive material of a first type; a plurality of trenches formed in the layer of conductive material, each trench including a trench wall; at least one semiconductor device formed laterally to the trench wall, the at least one semiconductor device comprising:
a first conductive region of a second type formed laterally to the trench wall; a second conductive region of the second type formed laterally to the trench wall; and a third conductive region of the layer of conductive material disposed laterally to the trench wall and separating the first and second conductive regions to provide a channel to conduct electrical current between the first and second conductive regions.
- 36. A semiconductor device, comprising:
an array of memory elements, each memory element comprising:
a first conductive region of a first type formed laterally in a trench wall; a second conductive region of the first type formed laterally to the trench wall; and a third conductive region of a second type disposed laterally to the trench wall and separating the first and second conductive regions to provide a channel to conduct electrical current between the first and second conductive regions.
- 37. The semiconductor device of claim 36, further comprising a wordline coupled to each memory element.
- 38. A semiconductor device, comprising:
an array of memory elements, each memory element comprising:
a first conductive region of a first type formed laterally to a trench wall having a (110) crystal plane orientation; a second conductive region of the first type formed laterally to the trench wall; and a third conductive region of a second type disposed laterally to the trench wall and separating the first and second conductive regions to permit electrical current to be conducted in a <110> direction between the first and second conductive regions.
- 39. A semiconductor device, comprising:
an array of memory element, each memory element comprising:
a layer of conductive material of a first type formed on a substrate; at least one trench formed in the layer of conductive material and including a trench wall substantially perpendicular to a top surface of the substrate and including a (110) crystal plane orientation; a first conductive region of a second type formed in a plane of the trench wall; a second conductive region of the second type formed in the plane of the trench wall; and a third conductive region of the layer of conductive material disposed in the plane of the trench wall and separating the first and second conductive regions to permit electrical current to be conducted in a <110> direction.
- 40. A semiconductor device, comprising:
a layer of conductive material of a first type; at least one trench formed in the layer of conductive material, the at least one trench including a trench wall; at least one memory element formed laterally to the at least one trench wall, the at least one memory element comprising:
a first conductive region of a second type formed laterally to the trench wall; a second conductive region of the second type formed laterally to the trench wall; and a third conductive region of the layer of conductive material disposed laterally to the trench wall and separating the first and second conductive regions to provide a channel to conduct electrical current between the first and second conductive regions.
- 41. A semiconductor device, comprising:
a first conductive region of a first type formed laterally in a trench wall; a second conductive region of the first type formed laterally to the trench wall; and a third conductive region of a second type disposed laterally to the trench wall and separating the first and second conductive regions to provide a channel to conduct electrical current between the first and second conductive regions.
- 42. A semiconductor device, comprising:
a first conductive region of a first type formed laterally to a trench wall having a (110) crystal plane orientation; a second conductive region of the first type formed laterally to the trench wall; and a third conductive region of a second type disposed laterally to the trench wall and separating the first and second conductive regions to permit electrical current to be conducted in a <110> direction between the first and second conductive regions.
- 43. A semiconductor device, comprising:
a layer of conductive material of a first type formed on a substrate; at least one trench formed in the layer of conductive material and including a trench wall substantially perpendicular to a top surface of the substrate and including a (110) crystal plane orientation; a first conductive region of a second type formed in a plane of the trench wall; a second conductive region of the second type formed in the plane of the trench wall; and a third conductive region of the layer of conductive material disposed in the plane of the trench wall and separating the first and second conductive regions to permit electrical current to be conducted in a <110> direction.
- 44. An electronic system, comprising:
a processor; and a semiconductor device coupled to the processor, wherein the semiconductor device comprises:
a first conductive region of a first type formed laterally in a trench wall; a second conductive region of the first type formed laterally to the trench wall; and a third conductive region of a second type disposed laterally to the trench wall and separating the first and second conductive regions to provide a channel to conduct electrical current between the first and second conductive regions.
- 45. An electronic system, comprising:
a processor; and a semiconductor device coupled to the processor, wherein the semiconductor device comprises:
a first conductive region of a first type formed laterally to a trench wall having a (110) crystal plane orientation; a second conductive region of the first type formed laterally to the trench wall; and a third conductive region of a second type disposed laterally to the trench wall and separating the first and second conductive regions to permit electrical current to be conducted in a <110> direction between the first and second conductive regions.
- 46. An electronic system, comprising:
a processor; and a memory device coupled to the processor, the memory device comprising:
a layer of conductive material of a first type; at least one trench formed in the layer of conductive material, the at least one trench including a trench wall; at least one memory element formed laterally to the at least one trench wall, the at least one memory element comprising:
a first conductive region of a second type formed laterally to the trench wall; a second conductive region of the second type formed laterally to the trench wall; and a third conductive region of the layer of conductive material disposed laterally to the trench wall and separating the first and second conductive regions to provide a channel to conduct electrical current between the first and second conductive regions.
- 47. An electronic system, comprising:
a processor; and a memory device coupled to the processor, the memory device including an array of memory elements, each memory element comprising:
a first conductive region of a first type formed laterally to a trench wall having a (110) crystal plane orientation; a second conductive region of the first type formed laterally to the trench wall; and a third conductive region of a second type disposed laterally to the trench wall and separating the first and second conductive regions to permit electrical current to be conducted in a <110> direction between the first and second conductive regions.
- 48. An electronic system, comprising:
a processor; and a memory device couple to the processor, the memory device comprising:
an array of memory element, each memory element comprising:
a layer of conductive material of a first type formed on a substrate; at least one trench formed in the layer of conductive material and including a trench wall substantially perpendicular to a top surface of the substrate and including a (110) crystal plane orientation; a first conductive region of a second type formed in a plane of the trench wall; a second conductive region of the second type formed in the plane of the trench wall; and a third conductive region of the layer of conductive material disposed in the plane of the trench wall and separating the first and second conductive regions to permit electrical current to be conducted in a <110> direction.
RELATED APPLICATIONS
[0001] This application is a Divisional of U.S. Ser. No. 09/850,764, filed May 8, 2001, which is a Divisional of U.S. Ser. No. 09/386,181 filed Aug. 31, 1999, now U.S. Pat. No. 6,245,615. This application is related to co-pending and co-filed application Ser. No. 09/386,185, attorney docket number 303.604US1, filed on Aug. 31, 1999, entitled “Multiple Oxide Thicknesses for Merged Memory and Logic Applications” by inventors Leonard Forbes and Wendell P. Noble, now U.S. Pat. No. 6,383,871, which is hereby incorporated by reference. This application is further related to co-pending and co-filed application Ser. No. 09/386,313, attorney docket number M4065.180/P180, filed on Aug. 31, 1999, entitled “Vertical Sub-Micron CMOS Transistors on (110), (111), (311), (511), and Higher Order Surfaces of Bulk, SOI and Thin Film Structures and Method of Forming Same,” by inventors Leonard Forbes, Wendell P. Noble and Alan R. Reinberg, which is hereby incorporated by reference. This application is also related to co-pending and co-filed application Ser. No. 09/386,315, attorney docket number M4065.0204/P204, filed on Aug. 31, 1999, entitled “Method for Fabricating CMOS Transistors Having Matching Characteristics and Apparatus Formed Thereby,” by inventors Leonard Forbes and Wendell P. Noble, which is hereby incorporated by reference.
Divisions (2)
|
Number |
Date |
Country |
Parent |
09850764 |
May 2001 |
US |
Child |
10463261 |
Jun 2003 |
US |
Parent |
09386181 |
Aug 1999 |
US |
Child |
09850764 |
May 2001 |
US |