Patent Application
20250028253
Fabricating semiconductor devices, such as logic and memory devices, typically includes processing a substrate such as a semiconductor wafer using a large number of semiconductor fabrication processes to form various features and multiple levels of the semiconductor devices. For example, lithography is a semiconductor fabrication process that involves transferring a pattern from a reticle to a resist arranged on a semiconductor wafer. Additional examples of semiconductor fabrication processes include, but are not limited to, chemical-mechanical polishing (CMP), etch, deposition, and ion implantation.
Inspection processes are used at various steps during a semiconductor manufacturing process to detect defects on wafers or reticles to promote higher yield in the manufacturing process and thus higher profits. However, as the dimensions of semiconductor devices decrease, inspection becomes even more important to the successful manufacture of acceptable semiconductor devices because smaller defects can cause the devices to fail. For instance, as the dimensions of semiconductor devices decrease, detection of defects of decreasing size has become necessary since even relatively small defects may cause unwanted aberrations in the semiconductor devices. Furthermore, as design rules shrink, semiconductor manufacturing processes may be operating closer to the limitations on the performance capability of the processes, and smaller defects can have an impact on the electrical parameters of the device.
Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various structures are not drawn to scale. In fact, the dimensions of the various structures may be arbitrarily increased or reduced for clarity of discussion.
The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of elements and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper”, “on” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.
As used herein, the terms such as “first”, “second” and “third” describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms may be only used to distinguish one element, component, region, layer, or section from another. The terms such as “first”, “second”, and “third” when used herein do not imply a sequence or order unless clearly indicated by the context.
The IC manufacturing process flow can be typically divided into three categories: front-end-of-line (FEOL), middle-end-of-line (MEOL), and back-end-of-line (BEOL). FEOL generally encompasses processes related to fabricating IC devices, such as transistors. For example, FEOL processes can include forming isolation features, gate structures, and source and drain features (generally referred to as source/drain features). MEOL generally encompasses processes related to fabricating contacts to conductive features (or conductive regions) of the IC devices, such as contacts to the gate structures and/or the source/drain features. BEOL generally encompasses processes related to fabricating interconnect structures that interconnect IC features fabricated by FEOL processes and MEOL processes, thereby enabling the operation of the IC devices.
In semiconductor manufacturing processes, defects that occur within the structures formed by metal materials in the MEOL (middle-end-of-line) and BEOL (back-end-of-line) stages can result in an increase in electrical resistance. This heightened resistance can have detrimental effects on semiconductor devices and their overall performance.
For instance, a common type of defect in metal structures involves the presence of impurities, such as foreign materials or contaminants. These impurities can infiltrate the metal layers during the deposition process, subsequently disrupt the flow of electrons within the metal, creating localized areas of increased electrical resistance. Such a situation may result in reduced conductivity, slower signal transmission, and potential performance degradation in semiconductor devices.
Another type of defect is the formation of voids or gaps within the metal structures. These voids can interrupt the continuous conductive path, effectively increasing the resistance along the affected regions. As current passes through these areas of higher resistance, it may generate heat and hence potentially resulting in hotspots. These hotspots can lead to device failure, reduced reliability, and impaired functionality.
Furthermore, the metal layers in the BEOL structure primarily serve to interconnect various components of the semiconductor device. Defects in these interconnects, such as open circuits or shorts, can have an adverse impact on electrical resistance. For instance, the open circuits disrupt the current flow, leading to increased resistance and signal disruption, while the shorts create unintended connections, altering the intended electrical pathways and potentially resulting in functional failures and decreased performance.
In order to inspect semiconductor structures for defects, there are some techniques widely used in the semiconductor manufacturing industry, such as optical inspection, electron microscopy, X-ray inspection, acoustic microscopy, electrical testing, laser scanning inspection, thermography, non-destructive testing (NDT), etc.
Among some common inspection approached, optical inspection generally involves the use of visible or ultraviolet light to visually examine semiconductor surfaces. It is effective in detecting surface defects such as scratches, particles, and irregularities. Optical microscopes and specialized inspection tools are commonly employed for this purpose. However, optical inspection is constrained by the wavelength of visible or ultraviolet light, which limits its ability to detect very small defects or features at the nanoscale. Consequently, it is less effective in identifying sub-micron defects or those within the internal layers of semiconductor structures. Furthermore, optical inspection primarily focuses on the surface of semiconductor materials, making it less suitable for detecting defects buried within the material or located beneath multiple layers. In other words, this technique provides limited information depth, as it cannot offer insights into the three-dimensional structure of defects or their depth within the material.
In another approach, X-ray inspection, including X-ray diffraction (XRD) and X-ray photoelectron spectroscopy (XPS), can be employed to analyze the crystal structure, composition, and chemical properties of semiconductor materials. However, similar to the issues with optical inspection, X-ray inspection is also constrained by the wavelength of X-rays, limiting its spatial resolution. It may struggle to accurately detect very small defects or nanoscale features, especially when compared to higher-resolution techniques like electron microscopy. Moreover, achieving higher resolution in X-ray imaging often involves exposing samples to higher doses of radiation, which may not be suitable for delicate or sensitive semiconductor devices.
In some embodiments of the present disclosure, a method for detecting defects within a semiconductor structure, such as defects in the metal structures in the MEOL and the BEOL structures of the semiconductor structures, can be employed. In some embodiments of the present disclosure, the detection approach is based on techniques such as scanning electron microscopy (SEM) or electron beam inspection (EBI). These related techniques utilize electron beams to examine and inspect various materials, including said semiconductor structures, at the microscale and nanoscale levels.
The EBI is a sophisticated and highly versatile imaging and analysis technique widely used in the semiconductor industry to scrutinize and assess semiconductor materials, integrated circuits, and other microelectronic devices. Briefly, it can be employed for defect detection, precise metrology (measurement of critical dimensions), contamination analysis, and failure analysis. The detection resolution of the EBI is high enough to detect tiny physical defects beyond the ability of optical defect imaging systems, and the EBI can be used to detect electrical defects of integrated circuitry, such as an open defect, a short or a leakage defect underneath the wafer surface by detecting voltage contrast (VC) due to the surface charge induced gray level (GL) variation.
The EBI operates on the principle of utilizing a focused electron beam to meticulously investigate the surface and subsurface features of semiconductor samples, enabling the detection of defects, measurement of critical dimensions, and analysis of material composition. EBI may be used to ensure the quality and reliability of semiconductor products, as even tiny defects or deviations from specifications can have a profound impact on the performance of electronic devices.
One of the primary principles of the EBI involves the generation of a focused electron beam using a high-energy electron gun, similar to the electron microscopes (e.g., SEM) used in scientific research. This electron beam is incredibly fine and can be precisely controlled, allowing it to scan semiconductor samples with exceptional precision. As the electron beam interacts with the sample, it gives rise to various interactions, including electron-sample interactions and electron scattering, which produce emitted signals and secondary electrons from the sample's surface. Specialized detectors are employed to capture these signals, which are subsequently processed to generate high-resolution images and data regarding the sample's topography, morphology, composition, and the presence of defects.
One of the standout features of the EBI is its exceptional spatial resolution, which allows it to discern and analyze sub-micron features and defects on semiconductor surfaces. This level of detail is crucial in semiconductor manufacturing, where even the tiniest irregularities can impair device functionality and reliability. Furthermore, the EBI is non-destructive, meaning it does not harm the sample during the inspection process. This is vital in semiconductor production, where the integrity of the devices must be preserved throughout the manufacturing process.
The EBI also offers the capability to perform subsurface imaging, making it invaluable for identifying defects and structures hidden beneath the surface of semiconductor materials. This capability is especially beneficial in pinpointing defects that may not be readily visible from the surface but can still impact device performance.
To be more detailed, in the aspect of defect detection, the EBI is used to identify and locate a variety of imperfections, including particles, cracks, voids, and electrical shorts on semiconductor wafers and ICs. Detecting defects at an early stage is crucial for improving yield and ensuring the overall quality of semiconductor products. In metrology, the EBI is utilized to precisely measure critical dimensions and verify that semiconductor devices conform to design specifications. This is essential for maintaining consistent device performance and functionality. Furthermore, the EBI can analyze contaminants on the surface of semiconductor materials, helping manufacturers identify and mitigate sources of contamination that can compromise device reliability. In the event of a semiconductor device failure, the EBI is instrumental in conducting failure analysis. By examining the structure of the semiconductor device and identifying defects or anomalies that may have contributed to the failure, the EBI aids in diagnosing and resolving issues to prevent future failures.
In some embodiments of the present disclosure, the open defect in the semiconductor structure can be detected through the EBI. In semiconductor structures, the term “open defect” refers to a type of defect that occurs when there is an interruption or discontinuity in the electrical path within the structure. It can be caused by various factors such as manufacturing errors, material defects, or physical damage.
That is, in the circumstances that a semiconductor structure has an open defect, it means that there is a physical gap or a physical missing connection in the electrical circuitry. This can happen at different portions within the semiconductor structure, such as at the metal lines or metal vias (i.e., within the BEOL structure), or at or in proximity to the transistor portion (i.e., within the FEOL structure or the MEOL structure). The open defect may create a break in the circuit, disrupt the normal flow of electrons, and prevent the flow of current through the affected region, thus lead to a loss of functionality or performance degradation in the semiconductor device.
The impact of an open defect depends on its location and the circuit it affects. For instance, if the open defect occurs in a critical path of the circuit, it can lead to a complete failure of the semiconductor device. On the other hand, if the open defect is in a non-critical path, it may result in reduced performance or intermittent failures.
Furthermore, in the aspect of parameters of the semiconductor structure, the open defect would increase the resistance of the path of the circuit. The resistance of an open defect is can vary depending on the nature of the interruption, and can be influenced by factors such as the size of the defect, the material properties, and the surrounding environment. Nevertheless, comparing to the resistance of a normal conductive structure with stable signal, the resistance of the open defect is extremely high. In some examples, the resistance of the conductive structure having the open defect is greater than about 1×106 ohms or greater than about 1×107 ohms, which is about 80% to about 90% higher than the resistance of a normal conductive structure in the semiconductor structure.
Referring to
In some embodiments, there are a plurality of conductive structures such as conductive contacts 914 in the MEOL structure 910 configured to provide the electrical connection between the transistors 908 and the metal lines 916 in the BEOL structure 912. Some of the conductive contacts 914 are landed on the doped regions (i.e., a part of the transistors 908, not shown in the figure) in the substrate 904. Due to some manufacturing errors, some conductive contacts 914 may have open defects 902 that disrupt the flow of electrons.
Other than the conductive contact 914 having the open defect 902, the semiconductor structure 900 may further includes one or more non-open defects 918 that different from the open defects 902.
In semiconductor structures, a “non-open defect” refers to a type of defect that does not result in a complete break or interruption in the circuitry. As some examples shown in
To be more detailed, the non-open defects can occur due to various reasons during the fabrication process of semiconductor devices. These non-open defects can be caused by issues such as contamination, impurities, or errors in the deposition or etching processes. In some embodiments, the non-open defects can be caused by the bottom residue and thus increase the resistance of the metal via in the BEOL structure 912. The non-open defects can manifest as localized variations in the material properties, such as changes in the doping concentration, the thickness, or the crystal structure. The impact of a non-open defect on the performance of a semiconductor structure depends on its location, size, and the functionality of the affected region. Overall, even though the non-open defect may not completely disrupt the electrical path, it can still introduce unwanted resistive elements into the circuit.
The resistance of a non-open defect can vary depending on its characteristics. The non-open defect may introduce a localized increase in resistance, causing a voltage drop across the affected region. This additional resistance can lead to increased power consumption, reduced signal quality, a loss of signal strength, a decrease in the voltage available for driving subsequent circuitry, and therefore degraded device performance. Comparing to the resistance of the normal conductive structure with stable signal, the resistance of the non-open defect is high (but not as high as the open defect since the non-open defect is not a complete break or interruption in the circuitry). In some examples, the resistance of the conductive structure having the non-open defect is in a range of from about 1×103 ohms to about 1×106 ohms, which is about 30% to about 50% higher than the resistance of a normal conductive structure in the semiconductor structure.
In some embodiments, in order to detect the defects that having abnormal resistance in the semiconductor structure, the EBI system can be employed. In some embodiments, referring to
In some embodiments, the electron source 102 in the SEM system 100 includes a photocathode 104, which serves as the initial stage in the generation of the electron beam 400 used for imaging specimens at high resolution. The operation of the photocathode 104 relies on the principles of the photoelectric effect. For instance, when illuminated with light, typically ultraviolet (UV) or laser light, the photocathode 104 may absorb photons and emit electrons. This phenomenon is possible because the energy of the incoming photons exceeds the work function of the material of the photocathode 104, allowing them to dislodge electrons from the surface of the photocathode 104. The emitted electrons, known as photoelectrons, are then extracted from the photocathode 104 and subsequently focused into a narrow and intense electron beam. This process is facilitated by the electron gun that applies an electric field to accelerate and shape the photoelectrons into a coherent beam. The coherent beam can then be accurately directed and scanned across the specimen's surface to interact with it and generate various signals, including secondary electrons (SE), backscattered electrons (BSE), and characteristic X-rays. These signals are detected and utilized to construct highly detailed images and gather valuable information about the specimen's topography, composition, and other properties. The material of the photocathode 104 depends on factors such as the desired sensitivity to specific wavelengths of light, stability, and efficiency. In some embodiments, the material of the photocathode 104 includes cesium antimonide (Cs3Sb), which exhibits a low work function and sensitivity to visible and UV light.
In some embodiments, the electron source 102 further includes an anode 106, typically in the form of a positively charged electrode positioned near the photocathode 104. The positive electric potential at the anode 106 creates an electrostatic field that attracts and accelerates the emitted electrons, propelling the photoelectrons away from the photocathode 104. This acceleration imparts kinetic energy to the electrons, resulting in the formation of a focused electron beam. The role of the anode 106 in this acceleration process is essential for achieving the desired beam characteristics, including energy and focus, thereby enabling high-resolution imaging capabilities in the SEM system 100.
In some embodiments, the SEM system 100 further includes an electron lens 108, which is positioned along the route of the electron beam 400 after the anode 106. The electron lens 108 serves as a crucial optical component responsible for focusing and directing the electron beam 400, enabling the SEM to achieve high-resolution imaging and analytical capabilities. In some embodiments, the electron lens 108 may include electromagnetic coils or magnetic lenses that generate magnetic fields. These magnetic fields interact with the moving electrons, causing them to follow a curved path due to the Lorentz force. By precisely adjusting the strength and orientation of these magnetic fields, the electron lens 108 can control the convergence or divergence of the electron beam 400. This control may achieve the desired beam characteristics, including focus and spot size, which directly impact image quality and resolution.
Furthermore, in some embodiments, a detector 110 can be positioned near the sample 150 (e.g., a wafer having the semiconductor structure 900) to collect and analyze the signals generated by the interaction of the electron beam 400 with the sample. Some of the common detectors include the secondary electron detectors, the backscattered electron detectors, and the energy-dispersive X-ray spectroscopy (EDS) detectors.
To be more detailed, when the electron beam strikes the surface of the sample 150, there are several interactions may thus occur and lead to the emission of various signals, such as (a) the secondary electrons: these low-energy electrons are emitted from the surface of the sample 150 due to the excitation caused by the primary electron beam, and the secondary electron detectors may collect these electrons to generate high-resolution images, providing topographical information; (b) the backscattered electrons: these are high-energy electrons that are deflected backward after interacting with the atomic nuclei of the sample 150, and the backscattered electron detectors may capture these electrons, providing compositional and crystallographic information about the sample; and (c) the X-ray emission: when the primary electron beam interacts with the sample 150, it can cause the emission of characteristic X-rays, and the EDS detectors may analyze these X-rays to determine the elemental composition of the sample 150.
Under the usage of the SEM system 100, referring to
To be more detailed, as the semiconductor structure 900 previously illustrated in
In some embodiments, the electron beam inspection operation is performed after the MEOL structure 910 is formed over the substrate 904, and therefore the conductive structure having the non-open defect can be identified from the titanium silicide layer 920 or the metal-to-diffusion (MD) layer in the MEOL structure 910, if there is any. In other embodiments, the electron beam inspection operation is performed after the BEOL structure 912 is formed over the MEOL structure 910, and therefore the non-open defect in the BEOL structure 912 can be identified accordingly, if there is any.
Referring to
Furthermore, from other aspect, oxide charging is often occurring around the conductive structures such as conductive contacts and cause the non-open defects (if there are any) unstable and behave in a transient state, so that the detection of the non-open defects is obscured.
Accordingly, in some embodiments of the present disclosure, when performing the electron beam inspection on the plurality of conductive structures within the semiconductor structure to obtain inspection data, the response time of the pulsed electron beam used in the electron beam inspection can be accelerated to a level shorter than microseconds for detecting non-open defects. In other words, the microsecond (1×10−6 s) pulsed beam typically used in electron beam inspection can be replaced with a nanosecond (1×10−9 s) pulsed beam, a picosecond (1×10−12 s) pulsed beam, or even a femtosecond (1×10−15 s) pulsed beam, by using the FE-SEM systems that modified to offer response times faster than microseconds.
Referring to
In some embodiments, as shown in
In some embodiments, the method for detecting defects in the semiconductor structure is implemented under the circumstances that the resistances of the conductive structures with/without defect are different, and the resistances of the types of open/non-open defects are also different. In some embodiments, the resistance of the conductive structure having the non-open defect is in a range of from about 1×103 ohms to about 1×106 ohms, whereas the conductive structure having the open defect is in a range of from about 1×106 ohms to about 1×107 ohms, or even more.
In some embodiments, the resistance of the conductive structure having the non-open defect (e.g., the Hi-R contact) is falls within that is approximately 30% to 50% higher than the resistance of the defect-free conductive structure (e.g., the normal contact). In contrast, the resistance of the conductive structure with an open defect (e.g., the open contact) falls within a range that is approximately 80% to 90% higher than the resistance of the defect-free conductive structure (e.g., the normal contact). In other words, in some embodiments, the method for detecting defects in the semiconductor structure can be applied in cases where the resistance of the conductive structure with the open defect is at least 20% higher than the resistance of the conductive structure with the non-open defect. Essentially, the method described in the present disclosure is capable of distinguishing defects with at least a 20% difference in resistance.
Regarding the selection of the response time of the pulsed electron beam, in some embodiments, the selection of the pulsed electron beam in the electron beam inspection operation is determined by whether the gray level of the conductive structure with the non-open defect in the inspection data is distinguishable from the gray level of the conductive structure free from having defect in the inspection data. Since a typical semiconductor structure may have multiple conductive structures with open defects, non-open defects, or be defect-free, in some embodiments, the response time of the pulsed electron beam used in the electron beam inspection operation can be adjusted to different levels to determine which pulsed beam is fast enough to accurately distinguish between the signals from non-open defects and those that are defect-free.
Accordingly, referring to
Still referring to
In addition, in some embodiments of the present disclosure, the method for detecting defects in the semiconductor structure can be applied to classify the semiconductor structures to ensure that the shipped semiconductor structures are basically free from having defects (i.e., without having open defects and non-open defects). In some embodiments, the semiconductor substrates, wafers, or other semiconductor structures can be classified or based on pre-determined threshold resistance value, which means in the case of the conductive structures in the semiconductor structure having open defects or non-open defects, the resistance value of the conductive structures may excess the pre-determined threshold and thus be classified as a group that not be shipped.
Referring to
Overall, the present disclosure provide an approach in identifying the non-open defects in the semiconductor structure. By enhancing the pulsed beam capability in EBI system, the non-open defects that used to be undetectable can thus be detected. In addition, while the VC signal of the EBI system with response time is in the level of nanosecond, picosecond, and/or femtosecond, the oxide charging effect can also be diminished.
In one exemplary aspect, a method for detecting defects in a semiconductor structure is provided. The method includes the following operations. A semiconductor structure having a plurality of conductive structures is received. An electron beam inspection operation is performed on the plurality of conductive structures of the semiconductor structure to obtain an inspection data, wherein a pulsed electron beam utilized in the electron beam inspection operation is selected from a group consisting of a nanosecond pulsed beam, a picosecond pulsed beam, and a femtosecond pulsed beam. A first conductive structure having a non-open defect is identified from the inspection data.
In another exemplary aspect, a method for detecting defects in a semiconductor structure is provided. The method includes the following operations. A semiconductor structure having a plurality of conductive structures is provided. An electron beam inspection operation is performed on the plurality of conductive structures of the semiconductor structure to obtain an inspection data, wherein a response time of the pulsed electron beam used in the electron beam inspection operation is accelerated to a level shorter than microseconds. A first conductive structure having a non-open defect is identified from the inspection data.
In yet another exemplary aspect, a method for detecting defects in a semiconductor structure is provided. The method includes the following operations. A semiconductor structure is received. A first electron beam inspection operation is performed on the semiconductor structure to obtain an inspection data, wherein a response time of the pulsed electron beam used in the electron beam inspection operation is shorter than a level of microsecond. A first conductive structure having a non-open defect is identified from the semiconductor structure by determining a first gray level of the first conductive structure substantially between a second gray level of a second conductive structure free from having defect and a third gray level of a third conductive structure having an open defect. If no first conductive structure is identified, the response time of the pulsed electron beam used in the electron beam inspection operation is adapted to a level of nanosecond, picosecond, or femtosecond to perform one or more second electron beam inspection operations on the semiconductor structure.
In an additional exemplary aspect, a method for classifying semiconductor structure is provided. The method includes the following operations. A semiconductor structure having a plurality of conductive structures is received. An electron beam inspection operation is performed on the plurality of conductive structures of the semiconductor structure to obtain an inspection data, wherein a response time of a pulsed electron beam used in the electron beam inspection operation is shorter than a level of microsecond. The semiconductor structure having the plurality of conductive structures is classified based on the inspection data, wherein the semiconductor structure is classified into a first group or a second group depending on a predetermined resistance of each conductive structure of the semiconductor structure in the inspection data.
The foregoing outlines structures of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other operations and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.
This application claims the benefit of prior-filed U.S. provisional application No. 63/514,803, filed Jul. 21, 2023, under 35 U.S.C. 120.
| Number | Date | Country | |
|---|---|---|---|
| 63514803 | Jul 2023 | US |
