Claims
- 1. In an integrated circuit, a structure for connecting a first level silicon conductor and a second level metal conductor separated by an insulating layer, comprising:
- an opening having substantially vertical sidewalls and extending through the insulating layer, wherein a portion of the first level conductor is exposed in the opening;
- a titanium silicide layer covering the exposed portion of the first level conductor;
- a titanium nitride layer covering said titanium silicide layer, the sidewalls of said opening, and a portion of an upper surface of the insulating layer; and
- a conformal conductor layer of tungsten disilicide having a substantially uniform thickness and overlying all of said titanium nitride layer;
- wherein the second level conductor overlies said conformal conductor layer above the insulating layer, wherein a conducting connection is made from the first level conductor through said titanium silicide layer, through said titanium nitride layer, and through said conformal layer, to said second level conductor.
- 2. In an integrated circuit, a structure for connecting a first level silicon conductor and a second level metal conductor separated by an insulating layer, comprising:
- an opening having tapered sidewalls and extending through the insulating layer, wherein a portion of the first level conductor is exposed in the opening;
- a titanium silicide layer covering the exposed portion of the first level conductor;
- a titanium nitride layer covering said titanium silicide layer, the sidewalls of said opening, and a portion of an upper surface of the insulating layer; and
- a conformal conductor layer of tungsten disilicide having a substantially uniform thickness and overlying all of said titanium nitride layer;
- wherein the second level conductor overlies said conformal conductor layer above the insulating layer, wherein a conducting connection is made from the first level conductor through said titanium silicide layer, through said titanium nitride layer, and through said conformal conductor layer, to said second level conductor.
Parent Case Info
This is a continuation of application Ser. No. 07/154868, filed on Feb. 11, 1988 and now abandoned.
US Referenced Citations (9)
Foreign Referenced Citations (1)
Number |
Date |
Country |
2825433 |
Dec 1978 |
DEX |
Non-Patent Literature Citations (1)
Entry |
IBM Technical Disclosure Bulletin, vol. 28, #4, p. 1442 Sep. 1985. |
Continuations (1)
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Number |
Date |
Country |
Parent |
154868 |
Feb 1988 |
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