A. Chatterjee et al., “Sub-100nm Gate Length Metal Gate NMOS Transistors Fabricated by a Replacement Gate Process”, 1997 IEEE, pp. 821-824. |
J.C.Hu et al., “Feasibility of Using W/TiN as Metal Gate for Conventional 0.13 um CMOS Technology and Beyond”, 1997 IEEE, pp. 825-828. |
Yasushi Akasaka, et al., “Low-Resistivity Poly-Metal Gate Electrode Durable for High-Temperature Processing”,Nov. 1996 IEEE Transactions on Electron Devices, vol. 43, No. 11, pp. 1864-1868. |
Bi-Shiou Chiou et al., “Microstucture and Properties of Multilayer-Derived Tungsten Silicide”, Journal of Electronic Materials, vol. 16, No. 4, 1987, pp. 251-255. |
A. Chatterjee et al., “CMOS Metal Replacement Gate Transistors using Tantalum Pentoxide Gate Insulator”, Dec. 1998 International Electron Devices (Electron Dev. Society of IEEE), 4 pgs. |
Pradeep L. Shah, “Refractory Metal Gate Processes for VLSI Applications”, Apr. 1979 IEEE Transactions on Electron Devices, vol. ED-26, No. 4, pp. 631-640. |