Patent Application
20180019298
This disclosure relates generally to methods for forming tantalum nitride (TaN) resistors and more particularly to methods for forming tantalum nitride (TaN) resistors on dielectric material passivation layers.
As is known in the art, tantalum nitride (TaN) thin films are used in many applications such as for example to form resistors, which are a critical passive component, on RFICs (Radio Frequency Integrated Circuits) and MMICs (Monolithic Microwave Integrated Circuits). A TaN resistive film is usually deposited on top of a dielectric passivation layer, such as silicon nitride or silicon dioxide, for example, to protect active transistors such as FETs (Field Effect Transistors) and BJTs (Bipolar Junction Transistors) and then patterned into the resistor using a masking-etching process. More particularly, current process to form resistors to make integrated circuits typically starts with deposition of TaN across on top of the dielectric passivation layer, such as a silicon nitride or silicon dioxide film disposed on top of substrate wafer. Then a certain area to form a resistor is covered with photoresist mask to protect the resistor area during a dry etch process that removes all the unmasked TaN resistive film on top of the passivation dielectric film. The dry etch process is supposed to remove only the portion of the TaN film exposed by the mask, and should not etch off the passivation dielectric film underneath the exposed TaN; however, the etch rate selectivity between TaN and the dielectric passivation layer or film under the TaN is in a range of from 1 to 1 to 10 to 1 depending on the dry etch gas chemistry. Therefore, if the thickness of TaN is 400 to 500 nm, and the thickness of a silicon nitride passivation layer underneath the TaN is 40 to 50 nm, for example, the dry etch process may damage the passivation film. Thus, with the mask formed over the portion of the TaN resistive film where the resistor is to be formed, the unmasked portions of the TaN are etched away using a dry etch process applied for a period of time calculated from predetermined etch rate of TaN resistive film and the thickness of the TaN resistive film. The practical application of such a timed etch process leads to undesired etching of the underlying silicon nitride film due to poor etch selectivity between the TaN film and the silicon nitride film using typical halogen-based pasma or wet chemistries.
In accordance with the present disclosure, a structure is provided having: a substrate; a passivation layer disposed over a surface of substrate; an etch stop layer disposed on the passivation layer; resistor comprising tantalum nitride, disposed on the etch stop layer. The etch stop layer has an etch rate at least 100 times slower than the etch rate of the tantalum nitride to a predetermined etchant.
In one embodiment, the passivation layer is a nitride and the predetermined etchant is a non-nitrogen compound etchant.
In one embodiment, the passivation layer is silicon nitride;
In one embodiment the passivation layer is silicon dioxide.
In one embodiment, the etchant is a halogen.
In one embodiment, the etch stop layer is aluminum oxide.
In one embodiment, a method is provided, comprising: forming a dielectric passivation layer over a surface of a substrate; forming an etch stop layer on the dielectric passivation layer; and forming a tantalum nitride layer on the etch stop layer. The etch stop layer has an etch rate at least 100 times slower than an etch rate of the tantalum nitride layer to a predetermined etchant. The method includes: masking a selected portion of a surface of the tantalum nitride layer while exposing adjacent portions of the selected portion of the surface of the tantalum nitride layer; and subjecting both the masked selected portion of the tantalum nitride layer and the exposed adjacent portions of the tantalum nitride layer to the predetermined etchant to selectively remove the exposed adjacent portions of the tantalum nitride layer while leaving the masked selected portion of the tantalum nitride layer.
Thus, in accordance with the disclosure, a thin dielectric film such as an aluminum oxide film is introduced between the TaN resistor film and passivation film as an etch stop layer. The inventors have recognized that the etch rate selectivity between TaN resistive film and aluminum oxide dielectric film is almost infinite when using a chlorine and/or fluorine gas dry etch process. Therefore, the aluminum oxide film can be used as an excellent etch stop layer, so the dry etch process etches off TaN resistive film, then stops at aluminum oxide layer. The disclosure thus solves a problem of poor etch selectivity between a TaN resistive film and passivation layer by introducing a thin highly etch rate selective dielectric film. In this way, then thin dielectric passivation film underneath TaN resistive film is not damaged or altered during the removal of TaN resistive film thereby significantly improving chip yield.
The inventors have also recognized significant etch rate difference between tantalum nitride and aluminum oxide. More particularly, the inventors have recognized the following: Equations (1), (2) and (3) below describe products resulting from the dry etch processing of tantalum nitride resistive film (TaN), silicon nitride film (SiN), and aluminum oxide film (Al2O3), respectively, with chlorine based gas. The volatility of the products of TaCl and SiCl (equations (1) and (2)) are much higher than that of AlCl, the product of equation (3), Therefore the selective etching of TaN resistive film on top of a SiN film using chlorine based dry etch process is very poor. However aluminum chloride (AlCl) formed by dry etch process using chlorine based gas has very low volatility, so the high selectivity between TaN, SiN, and Al2O3 using a chlorine based dry etch process makes the Aluminum oxide film to be an excellent etch stop layer.
TaN+Cl2=TaCl+N2 (1)
SiN+Cl2=SiCl+N2 (2)
Al2O3+Cl2=AlCl+O2 (3)
Further, a similar dry etch reaction occurs when fluorine based gas, for example SF6, is used to etch TaN, SiN, and Al2O3 films.
TaN+SF6=TaF+N2+S (3)
SiN+SF6=SiF+N2+S (4)
Al2O3+SF6+=AlF+O2+S (5)
More particularly, the volatility of Tantalum fluoride (TaF) and Silicon fluoride (SiF) is much higher than Aluminum fluoride (AlF), therefore the high selectivity between TaN, SiN, and Al2O3 under fluorine based dry etch process makes the alumninum oxide film to be an excellent etch stop layer.
Thus, time based day etch process using chlorine based gas or fluorine based gas to selectively etch off a tantalum nitride film on top of silicon nitride film increases the risk to over etching that may damage underlying portions of the silicon nitride dielectric passivation film or under etching that may leave TaN resistive film on a certain undesired areas.
The details of one or more embodiments of the disclosure are set forth in the accompanying drawings and the description below. Other features, objects, and advantages to of the disclosure will be apparent from the description and drawings, and from the claims.
Like reference symbols in the various drawings indicate like elements.
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Thus, in accordance with the disclosure, a thin dielectric film such as aluminum oxide film is introduced between the TaN resistor film and passivation film. The aluminum oxide film is an excellent etch stop layer, so the dry etch process etches off TaN resistive film, then stops at aluminum oxide layer. The disclosure thus solves a problem with poor etch selectivity between a TaN film and a passivation layer by introducing a thin highly etch rate selective dielectric layer. In this way, then thin dielectric passivation film, such as silicon nitride and silicon dioxide, underneath TaN resistive film is not damaged or altered during the removal of TaN film thereby improving chip yield.
A number of embodiments of the disclosure have been described. Nevertheless, it will be understood that various modifications may be made without departing from the spirit and scope of the disclosure. Accordingly, other embodiments are within the scope of the following claims.
