Patent Application
20240397636
Embodiments of the present invention relate generally to printed circuit boards (PCB) structures and methods for integrating copper-graphene therein.
A PCB is a laminated structure of conductive and insulating layers that are used to support electronic components and to provide electrical connections and open circuits between electrical terminals. In general, each of the conductive layers comprises a pattern of electrical pathways or traces that provides electrical connections on that conductive layer. In addition, vias, or plated through-holes, may be provided to allow electrical interconnections between different conductive layers.
Graphene is known to have several beneficial properties which can passivate copper metal lines and improve by high-frequency conductivity, and/or the like, when incorporated into a PCB. Incorporating graphene into a PCB can be difficult as graphene is easily damaged or destroyed, such as during the lamination process, lithography, the drilling process, and/or the electroplating process. Such damage or destruction may, in turn, lead to improper passivation of the copper and/or lower conductivity. Thus, there exists a problem with incorporating graphene into PCBs and retaining the integrity of the graphene.
Embodiments of the present invention provide an improved method of creating PCBs that integrates graphene as a passivation layer on copper and allows drilling and electroplating without damaging or unintentionally removing portions of the graphene, which may render the PCB useless (e.g., may remove the copper capping layer and render the PCB vulnerable to oxidation and rapid deterioration), as well associated methods for forming the lamination stack comprising the graphene.
In some embodiments a method of forming a lamination stack comprises: providing a core; applying a first graphene layer to a surface portion of the core; applying a metal layer to the first graphene layer; applying a second graphene layer to the metal layer; applying a photoresist layer to the second graphene layer; applying a protective layer to the photoresist layer; drilling through the protective layer and at least one of the photoresist layer, the second graphene layer, the metal layer, the first graphene layer, or the core; applying a metallic plating to the lamination stack, wherein the metallic plating is applied to the lamination stack, such that the metallic plating covers an internal surface of the lamination stack formed by the drilling; and removing the protective layer from the photoresist layer, wherein the removal of the protective layer causes a removal of the metallic plating in contact with the protective layer.
In some embodiments, the metallic plating is a material comprising at least one of palladium, tin, or copper.
In some embodiments, removing the protective layer comprises applying heat at a predefined temperature to the lamination stack, wherein the temperature is based on the protective layer. In some embodiments, the temperature is in the range of approximately 90 degrees Celsius to approximately 180 degrees Celsius.
In some embodiments, the protective layer is a material comprising a resiliency to Hydrogen score of at least one, two, three, four, eleven, twelve, thirteen, or fourteen.
In some embodiments, the protective layer is a material comprising at least one of a polymethyl methacrylate (PMMA), a polydimethyloxyaniline (PDMA), a poly ethylene vinyl acetate, a water-insoluble film polymer, a polyetherimide, a thermoplastic polymer, or an elastomeric polymer.
In some embodiments, the protective layer comprises at least one of an adhesive tape, a thermal release tape, a dry film photoresist, an atomic deposition layer, or a photoresist.
In some embodiments, the protective layer is applied in a room-temperature environment.
In some embodiments, a lamination stack integrating copper-graphene laminate comprises: a core; a first graphene layer disposed on a surface portion of the core; a metal layer disposed on the first graphene layer; a second graphene layer disposed on the metal layer; a photoresist layer disposed on the second graphene layer; and a protective layer disposed on the photoresist layer, wherein the lamination stack defines an opening through the protective layer and at least one of the photoresist layer, the second graphene layer, the metal layer, the first graphene layer, or the core.
In some embodiments, a metallic plating is disposed on the surface of the lamination stack, such that the metallic plating covers an internal surface of the lamination stack defined by the opening. In some embodiments, the metallic plating is a material comprising at least one of a palladium or copper. In some embodiments, the metallic plating in contact with the protective layer and the protective layer are removed.
In some embodiments, the metal layer defines a gap. In some embodiments, the first graphene layer and the second graphene layer are cut to correspond to the gap.
In some embodiments, the protective layer is a material comprising a potential of Hydrogen score of one, two, three, four, eleven, twelve, thirteen, or fourteen.
In some embodiments, the protective layer is a material comprising at least one of a polymethyl methacrylate (PMMA), a poly (PDMA), a poly ethylene vinyl acetate, polyetherimide, a water-insoluble film polymer, a thermoplastic polymer, or an elastomeric polymer.
In some embodiments, the protective layer comprises at least one of an adhesive tape, a dry film photoresist, an atomic deposition layer, or a photoresist.
In some embodiments, the protective layer is applied in a room-temperature environment.
In some embodiments, the opening is a via.
The above summary is provided merely for purposes of summarizing some example embodiments to provide a basic understanding of some aspects of the present disclosure. Accordingly, it will be appreciated that the above-described embodiments are merely examples and should not be construed to narrow the scope or spirit of the disclosure in any way. It will be appreciated that the scope of the present disclosure encompasses many potential embodiments in addition to those here summarized, some of which will be further described below.
Having thus described the disclosure in general terms, reference will now be made to the accompanying drawings, which are not necessarily drawn to scale. The components illustrated in the figures may or may not be present in certain embodiments described herein. Some embodiments may include fewer (or more) components than those shown in the figures.
Example embodiments will now be described more fully hereinafter with reference to the accompanying drawings, in which some, but not all, embodiments are shown. Indeed, the embodiments may take many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will satisfy applicable legal requirements. Like reference numerals refer to like elements throughout. The term “exemplary” and “example” as may be used herein are not provided to convey any qualitative assessment, but instead merely to convey an illustration of an example. As used herein, terms such as “front,” “rear,” “top,” “bottom,” “inside,” “outside,” “inner,” “outer,” etc. are used for explanatory purposes in the examples provided below to describe the relative position of certain components or portions of components. Furthermore, as would be evident to one of ordinary skill in the art in light of the present disclosure, the terms “substantially” and “approximately” indicate that the referenced element or associated description is accurate to within applicable engineering tolerances. Thus, use of any such terms should not be taken to limit the spirit and scope of embodiments of the present invention.
A lamination stack, generally, is a structure formed by layers of materials (e.g., conductive and non-conductive) that are heated, pressed, and/or further processed to form a PCB. For example, such materials may include a non-conductive material (e.g., the core) possessing dielectric properties, an adhesive layer, and a conductive material, such as the commonly used metal, copper (e.g., copper foil). The lamination stack may then be laminated (i.e., heated and/or pressurized under vacuum and/or controlled gas atmosphere) to solidify a bond between the layers of material to create the structure of the PCB. In some aspects of the present invention, heat may be applied to the bottom of the lamination stack (e.g., from below the lamination stack), applied to the top of the lamination stack (e.g., from above the lamination stack), and/or applied from various directions around the lamination stack (e.g., using an oven chamber to heat the lamination stack from multiple sides). The electrical and thermal conductive material (e.g., copper) may then be etched to create the conductive trace of the PCB. In some aspects, the process of adding a metallic plating after the drilling and electroplating of the lamination stack may be used to create the PCB. For instance, a metallic plating, such as copper, palladium, tin, and/or the like, is often used within the vias drilled through the lamination stack to promote conductivity between a top and bottom surface of the lamination stack. However, a problem arises as, in the process of applying the metallic plating on the inner surface of the vias, the metallic plating is applied on the entire surface of the lamination stack (e.g., including the top and bottom of the lamination stack). As a result, the metallic plating must be removed from certain locations (e.g., the top and bottom of the lamination stack) without damaging the materials adjacent to the metallic plating (e.g., the protective layer, any lithographically patterned material such as a photoresist layer, graphene layer, and/or the like).
Graphene, an allotrope of carbon, consists of a single layer of atoms (one atomic layer of graphite) arranged in a two-dimensional honeycomb lattice nanostructure. It is considered a semi-metal having unusual electronic properties that may be described by theories for massless relativistic particles. One characteristic of graphene is that it conducts heat and electricity very efficiently along its plane. In addition, it has exceptionally high tensile strength, electrical conductivity, and transparency. Additionally, graphene can passivate the surface of copper and prevent oxidation of copper lines exposed to air. In high-frequency copper transmission lines, the electrical signal is concentrated close to the outer skin of the copper, where the conductivity of the capping layer takes significant portion of the overall conductivity. In the case where graphene is grown on copper by CVD, the thermal annealing causes copper grain growth and results in improved thermal conductivity of copper by about 20%. The surface roughness of copper after graphene growth is improved significantly and the smoother surface has lower impedance at high frequency.
Due to such properties of graphene, the use of graphene as a capping layer to copper within a lamination stack could have beneficial effects on the properties of the resulting PCB, including higher bandwidth, greater conductivity, and better thermal management over conventional PCBs. However, there exists a problem in creating PCB structures when integrating graphene in the stack-up process of the PCB (pre-lamination of the PCB layers within a lamination stack). Thus, it is important to protect the graphene from damage caused during the lamination process, brown copper oxidation, the drilling process, and the removal process of the protective layer and metallic plating.
According to embodiments of the present invention, a protective layer may be placed on the outer surface of materials of the lamination stack (e.g., the core, the graphene layer(s), the adhesive layer, the lithographically patterned layer (e.g., a photoresist layer), the conductive metal layer such as copper, and/or the like) before applying a metallic plating. By adding the protective layer to the outer surface of materials of the lamination stack, the metallic plating may be removed in certain locations without damaging the materials underneath. In contrast, if the metallic plating were applied directly to a graphene layer or other layer (e.g., lithographically patterned layer), attempts to remove the metallic plating to finalize the PCB structure could damage the underlying layer. Accordingly, the use of a protective layer between the metallic plating and underlying layers of the lamination stack according to embodiments of the invention allow portions of the metallic plating to be removed from the lamination stack without causing damage to the underlying materials and may allow only portions of the metallic plating to be removed (e.g., the metallic plating on the top and bottom surface of the lamination stack which are in contact with the protective layer) without removing the metallic plating on other surfaces of the lamination stack (e.g., the metallic plating inside the vias).
With reference to
Turning again to
In some embodiments, and as described above, before the photolithography and/or photoengraving of the photoresist layer 106, a protective layer 104 (and/or 114) may be added to the outer surface(s) of the lamination stack, such as the top-portion of the lamination stack (e.g., protective layer 104), the bottom-portion of the lamination stack (e.g., protective layer 114), the side portions of the lamination stack (not pictured), and/or the like. Such addition of protective layers may be strategically added to specific surfaces or locations on the lamination stack, such as where the metallic plating will need to be removed during the process of creating the PCB.
In some embodiments, and as shown in
In some embodiments, a patterned mask (not shown) may be applied adjacent to the photoresist layer (or any lithographically patterned material or layer) 106, such that when light is applied, the mask which is disposed between the light source and the photoresist layer, then the photoresist layer-which is not protected by the mask-will change its solubility. In other areas, the patterned mask will block the light, such that no change in the photoresist material occurs in the regions underlying the mask. The mask may then be removed, and a solvent or developer can be applied to the surface of the photoresist. Because the solubility of portions of the photoresist have been changed, those portions will be dissolved by the solvent or developer, forming gaps (150) in the photoresist layer 106 and exposing the second graphene layer 108 beneath (e.g., the graphene layer directly underneath the photoresist layer 106). In some cases (e.g., where a negative photoresist is used), the application of light will serve to strengthen the unmasked regions of the photoresist material. Thus, in these cases, the application of the solvent will degrade or wear away only the portions of the photoresist layer 106 that were not exposed to the light.
With the gaps formed in the photoresist layer 106, the first graphene layer 118 and second graphene layer 108, and the metal layer 110, may be etched (e.g., via wet etching) to the same pattern of the gaps in the photoresist layer 106. In some embodiments, the gaps 150 in the photoresist layer 106 may be of a different size (e.g., width and/or length) than the gaps 150 formed in the graphene layers (118 and 108) and the metal layer 110. Subsequently, and in some embodiments, a protective layer 104 and/or 114, may be applied to the top and bottom of the lamination stack 100 in preparation for a drilling procedure, as shown in
In some embodiments, and where the protective layer 104 is a thermal release tape, the protective layer 104 may be applied to the photoresist layer 106 by laying a sticky (or adhesive) surface of the thermal release tape on the top surface of the photoresist layer 106 and/or a sticky surface of the thermal release tape on the bottom surface of the core 116. As will be understood by a person of ordinary skill in the art, the sticky surface of the thermal release tape may be applied to any exterior surface of the lamination stack (e.g., a bottom surface of a core, a top surface of the core, a bottom surface of a lithographically patterned material, a top surface of a lithographically patterned material, a top or bottom surface of a metal layer, and/or the like). In some embodiments, and where the protective layer 104 is a dry film photoresist, the protective layer 104 may be applied by heat and pressure at the same time.
The protective layers 104 and 114 may thus serve to shield and protect one or more of the intermediate layers (e.g., the core material 116, the first layer of graphene 118, the metal layer 110, the second layer of graphene 108, the photoresist layer 106 in the depicted embodiment) as a metallic plating is applied and/or removed. Such embodiments are described more fully herein with respect to
With reference to
By way of non-limiting example, the electroplating of the lamination stack may comprise an application of a metallic plating to the inner surface of the vias, where the metallic plating may comprise copper and/or other such conductive materials (tin, palladium, copper and/or the like). The metallic plating applied to the inner surface of the vias may provide a conductive path from the top surface of the lamination stack to the bottom surface of the lamination stack, and such a conductive path may include the material layers within the lamination stack. For instance, the conductive path may pass through at least the core layer 116, the first graphene layer 118, the metal layer 110, the second graphene layer 108, and/or the photoresist layer 106, from the top surface to the bottom surface.
With reference to
With reference to
In some embodiments, the protective layer (104 shown in
With reference to
As shown in block 502, the method 500 may comprise the step of providing a core. In some embodiments, the lamination stack (100, 200, 300, 400) may comprise a core 116 that is a dielectric. In some embodiments, the core 116 may comprise at least one of polyimide, polyester, polyurethane, bismaleimide triazine (BT), cyanate ester, fused silica, woven glass, fiberglass, microfiber glass, epoxy resin, phenol compounds, polytetrafluoroethylene (PTFE), low density polyethylene (LDPE), high density polyethylene (HDPE), polyethylene terephthalate (PET), thermoplastic polyurethane (TPU) or ceramic material.
As shown in block 504, the method 500 may comprise the step of applying a first graphene layer to a surface portion of the core. In some embodiments, and by way of non-limiting example, the lamination stack (100, 200, 300, 400) may comprise a plurality of graphene layers, including a first graphene layer 118, which may be disposed and/or grown on 110). For instance, the graphene layers (at least a first graphene layer 118 and a second graphene layer 108) may be grown on the surface of the core 110 at the same time. In some embodiments, and upon growing at least one layer of graphene on the metal layer 110, the metal layer comprising at least one graphene layer (e.g., a first graphene layer 118 and/or a second graphene layer 108) may be placed on a surface portion of the core 116.
As shown in block 506, the method 500 may comprise the step of applying a conductive layer to the first graphene layer. In some embodiments, the lamination stack (100, 200, 300, 400) may comprise a conductive layer that is a metal layer 110, such as a copper layer and/or the like, which may be used to grow a first graphene layer 118 on the surface (e.g., a top surface) of the conductive layer. In some embodiments, the metal layer 110 may comprise copper.
As shown in block 508, the method 500 may comprise the step of applying a second graphene layer to the metal layer (e.g., a copper layer) 110. In some embodiments, the lamination stack (100, 200, 300, 400) may comprise a second graphene layer, such as that shown as graphene layer 108 in
As shown in block 510, the method 500 may comprise the step of applying a photoresist layer (106) to the second graphene layer. In some embodiments, the lamination stack (100, 200, 300, 400) may comprise a photoresist layer 106 attached and/or placed on the second graphene layer 108. In some embodiments, the photoresist layer 106 may be patterned, such that the light-sensitive material of the photoresist layer may be exposed to light—or another focused energy source such as a laser beam-which will change the layer's solubility or sensitivity with respect to a developer, thereby allowing the layer to be patterned.
As shown in block 512, the method 500 may comprise the step of applying a protective layer to the photoresist layer. In some embodiments, the protective layer 104 may be a material having a resiliency to acidic and basic materials, such as a resiliency to materials comprising Hydrogen scores of one, two, three, four, eleven, twelve, thirteen, or fourteen. Such resiliency may be necessary for the protection of the metal layer 110 during the metal deposition process when forming the vias (e.g., via 151). In some embodiments, the protective layer 104 is a material comprising at least one of a polymethyl methacrylate (PMMA), a polydimethyloxyaniline (PDMA), a poly ethylene vinyl acetate, polyetherimide or a thermoplastic polymer or an elastic polymer. In some embodiments, the protective layer 104 comprises an adhesive tape, a thermal plastic release tape, a dry film photoresist, an atomic deposition layer, or a photoresist. In some embodiments, and where the protective layer 104 is a dry film photoresist, the protective layer 104 may be placed on top of the photoresist layer 106. In some embodiments, properties of the dry film photoresist may be such that the protective layer 104 can be peeled off the underlying photoresist layer 106.
As shown in block 514, the method 500 may comprise the step of drilling through the protective layer and at least one of the photoresist layer, the second graphene layer, the metal layer, the first graphene layer, and/or the core. In some embodiments, the lamination stack may thus comprise a via that is drilled through a portion of each layer (such as the vias 151 shown in
With reference to
In some embodiments, and as shown in block 602, the method 600 may comprise the step of applying a metallic plating to the lamination stack, wherein the metallic plating is applied to an outer surface of the lamination stack, such that the metallic plating covers an internal surface of the lamination stack formed by the drilling (e.g., the internal surface of the vias 151). In some embodiments, block 602 and its associated process may occur subsequent to block 514 of
In some embodiments, and as shown in block 604, the method 600 may comprise the step of removing the protective layer from the photoresist layer, wherein the removal of the protective layer results in the removal of the metallic plating in contact with the protective layer. In some embodiments, and once heat at the predetermined temperature has been applied to the lamination stack, the protective layer 104 and/or 114 (and the adjacent metallic plating 102) may be removed by simply pulling the protective layer 104 and/or 114 (and, along with it, the adjacent metallic plating 102) away from the photoresist layer 106. In some embodiments, the protective layer (and the adjacent metallic plating 102) may be removed by etching the protective layer 104 (and/or 114) and the metallic plating 102.
By way of non-limiting example, the metallic plating 102 in contact with (e.g., overlying) the protective layer 104, 114 may comprise the metallic plating that is touching and/or directly adjacent to the protective layer 104, 114 (such as the top-most and bottom-most metallic plating shown in
In some embodiments, the removal of the protective layer from the photoresist layer may comprise an application of heat at a predetermined temperature to the lamination stack, where the temperature is based on the material properties of the selected protective layer. For instance, and by way of a non-limiting example, a protective layer 104 may be removed from another layer of material, such as photoresist layer 106, by applying a heat at a predefined temperature to the lamination stack (including the core 116, the first graphene layer 118, the metal layer 110, the second graphene layer 108, the photoresist layer 106, the protective layer 104, and the metallic plating 102). In some embodiments, the predetermined heat may comprise a temperature of a range from approximately 90 degrees Celsius to approximately 180 degrees Celsius. In some embodiments, and based on the properties (e.g., material(s)) used in the protective layer 104, the protective layer 104 may be removed by applying the predetermined heat to the lamination stack. In some embodiments, the protective layer may be a thermal release tape, which may be removed from the photoresist layer by applying heat and/or a specific solvent. For instance, and in some embodiments, heat at a temperature of between 180 and 220 degrees Celsius may be applied for a protective layer comprising a prepreg which has glue properties (such as a thermal release tape).
In some embodiments, the protective layer may comprise a dry film. Such a dry film as a protective layer may be removed by spraying and/or applying a dry film solvent to the surface of the protective layer. In some embodiments, and upon applying the dry film solvent, the protective layer may be peeled off or stripped from the photoresist layer 106.
In some embodiments, and during and/or after the removal of the protective layer 106 and metallic plating 102 on a top and bottom surface of the lamination stack, the photoresist layer 106 may be additionally removed from the lamination stack. For instance, and in some embodiments, a secondary lamination stack may be applied to the (first) lamination stack in order to generate a multi-layer PCB, such that the multi-layer PCB comprises a plurality of different lithographically patterned circuits. In some embodiments, the via(s) (e.g., via 151) may be in the same location for each layer of the lamination stack within the multi-layer PCB, such that each of the vias (e.g., via 151) are aligned to electrically connect the layers of the lamination stacks. As will be understood by a person of skill in the art, similar processes as described herein may be used for each of the lamination stacks within a multi-layer PCB.
Many modifications and other embodiments of the present inventions set forth herein will come to mind to one skilled in the art to which these inventions pertain having the benefit of the teachings presented in the foregoing descriptions and the associated drawings. Therefore, it is to be understood that the present inventions are not to be limited to the specific embodiments disclosed and that modifications and other embodiments are intended to be included within the scope of the appended claims. Moreover, although the foregoing descriptions and the associated drawings describe example embodiments in the context of certain example combinations of elements and/or functions, it should be appreciated that different combinations of elements and/or functions may be provided by alternative embodiments without departing from the scope of the appended claims. In this regard, for example, different combinations of elements and/or functions than those explicitly described above are also contemplated as may be set forth in some of the appended claims. Although specific terms are employed herein, they are used in a generic and descriptive sense only and not for purposes of limitation.
