Method for making internally overlapped conditioners

Abstract

The application discloses novel internal structures of energy conditioners, assemblies of external structures of energy conditioners and mounting structure, and novel circuits including energy conditioners having A, B, and G master electrodes.

Description

FIELD OF THE INVENTION

This invention relates to energy conditioning.

BACKGROUND OF THE INVENTION

Electrical circuits using low frequency electrical power generate noise that is coupled through the power distribution system. That noise is generally detrimental. In the past, capacitors have been used to condition the electrical power propagating to and from devices. One type of device in which capacitors have been used to condition electrical power is an active circuitry. Capacitors have been used to in active circuitry to decouple noise from the power lines. Typically, in applications involving Large or Very Large

Scale Integration (LSI or VLSI) Integrated Circuits (ICs), multiple rows of capacitors are arrayed on a PC board as close as feasible to the location of the IC in the PC board, given design constraints. This arrangement provides sufficient decoupling of the power and ground from the IC's active circuitry. The terms “bypass” and “decoupling” are used interchangeable herein.

SUMMARY OF THE INVENTION

This application discloses novel energy conditioner structures and novel combinations of the connections of the energy conditioners on other structures, such as PC board structures, and novel circuit arrangements of the energy conditioners with structures, such as PC boards, described herein, generally provide improved decoupling, per conditioner, and require less conditioners and related structure, such as vias, to provide sufficient decoupling. Similarly to PC boards, the structures to which the novel conditioners and the novel combination of the connections of the energy conditioners may be applied include first level interconnects and semiconductor chips, including for example ASIC, FPGA, CPU, memory, transceiver, computer on a chip, and the like.

More particularly, this application discloses and claims energy conditioner internal structures and external structures, connection structure, and circuits including energy conditioners having A, B, and G master electrodes.

In one aspect, the claims define an internal structure of an energy conditioner: wherein said internal structure has a left side surface, a right side surface, an upper side surface, a lower side surface, a top side surface, and a bottom side surface;

wherein said internal structure comprises a dielectric material and a conductive material;

wherein surfaces of said dielectric material and surfaces of said conductive material define said left side surface, said right side surface, said upper side surface, said lower side surface, said top side surface, and said bottom side surface;

wherein said conductive material comprises a first A conductive layer and a first B conductive layer in a first plane;

wherein said first A conductive layer and said first B conductive layer are electrically isolated from one another in said structure;

wherein said first A conductive layer comprises at least one first A conductive layer first tab and a first A conductive layer main body portion;

wherein said first B conductive comprises at least one first B conductive layer first tab and a first B conductive layer main body portion;

wherein said first A conductive layer main body portion does not extend to any one of said left side, right side, upper side, and lower side;

wherein said first B conductive layer main body portion does not extend to any one of said left side, right side, upper side, and lower side;

wherein said at least one first A conductive layer first tab extends to said left side surface, said upper side surface, and said lower side surface; and

wherein said at least one first B conductive layer first tab extends to at least portions of said right side surface, said upper side surface, and said lower side surface.

In aspects dependent upon the foregoing, the claims define wherein said first A conductive layer main body portion extends to a region closer to said right side surface than said left side surface and closer to said upper side surface than said lower side surface, and wherein said first B conductive layer main body portion extends to a region closer to said left side surface than said right side surface and closer to said lower side surface than said upper side surface; wherein said at least one first A conductive layer first tab comprises a single tab extending across all of said left side, extending to a left side end of said upper side surface, and extending to a left side end of said lower side surface; wherein said at least one first A conductive layer first tab comprises at least two tabs; wherein said conductive material further comprises a first G conductive layer; wherein conductive material further comprises a first G conductive layer between said first A conductive layer and said first B conductive layer; wherein conductive material further comprises a first G conductive layer in a second plane parallel to said first plane, and said G conductive layer has a G conductive layer main body portion having a region opposing at least a portion of said first A conductive layer A main body portion and a portion of said first B conductive layer main body portion;

wherein said conductive material comprises a second A conductive layer in a second plane and a second B conductive layer in said second plane;

wherein said second A conductive layer and said second B conductive layer are electrically isolated from one another in said structure;

wherein said second A conductive layer comprises at least one second A conductive layer first tab and a second A conductive layer main body portion;

wherein said second B conductive layer comprises at least one second B conductive layer first tab and a second B conductive layer main body portion;

wherein said second A conductive layer main body portion does not extend to any one of said left side surface, said right side surface, said upper side surface, and said lower side surface;

wherein said second B conductive layer main body portion does not extend to any one of said left side surface, said right side surface, said upper side surface, and said lower side surface;

wherein said at least one second A conductive layer first tab extends to at least portions of said left side surface, said upper side surface, and said lower side surface;

wherein said at least one second B conductive layer first tab extends to at least portions of said right side surface, said upper side surface, and said lower side surface;

wherein said second A conductive layer main body portion extends to a region closer to said right side surface than said left side surface and closer to said lower side surface than said upper side surface, and wherein said second B conductive layer main body portion extends to a region closer to said left side surface than said right side surface and closer to said upper side surface than said lower side surface;

whereby said first A conductive layer main body portion and said second B conductive layer main body portion have a first region of substantial overlap and said second A conductive layer main body portion and said first B conductive layer main body portion have a second region of substantial overlap; wherein said conductive material further comprises a first G conductive layer, and wherein said first G conductive layer comprises a main body portion having a substantial overlap with both said first region and said second region; wherein said first G conductive layer is in a third plane between said first plane and said second plane; wherein said conductive material further comprises:

a first G conductive layer in said first plane between said first A conductive layer and said first B conductive layer and electrically isolated in said structure from said first A conductive layer and said first B conductive layer; and

a second G conductive layer in said second plane between said second A conductive layer and said second B conductive layer and electrically isolated in said structure from said second A conductive layer and said second B conductive layer; wherein said conductive material further comprises a second G conductive layer, and wherein said second G conductive layer comprises a main body portion having a substantial overlap with both said first region and said second region; and wherein said first G conductive layer is in a third plane between said first plane and said second plane.

In a second aspect the claims define an assembly comprising said internal structure and an external structure of an energy conditioner, wherein said external structure comprises: a first conductive integration region that extends along at least one of said left side surface, said upper side surface, and said lower side surface and contacts there at, at least one of said at least one first A conductive layer first tab; and a second conductive integration region that extends along at least one of said right side surface, said upper side surface, and said lower side surface and contacts thereat at least one of said at least one first B conductive layer first tab.

Dependent upon the second aspect, the claims define wherein said internal structure further comprises a G conductive layer including a G conductive layer main body portion, a G conductive layer first tab, and a G conductive layer second tab, and wherein said external structure further comprises a third conductive integration region that extends along at least one side surface of said internal structure and contacts thereat said G conductive layer first tab; wherein said external structure further comprises a fourth conductive integration region that extends along at least one side surface of said internal structure opposite the one side surface of said internal structure along which said third conductive integration region extends where at said fourth conductive integration region contacts said G conductive layer second tab; wherein at least one of said first conductive integration region, said second conductive integration region, said third conductive integration region, and said fourth conductive integration region are formed from solder; wherein at least one of said first conductive integration region, said second conductive integration region, said third conductive integration region, and said fourth conductive integration region comprise a conductive band; further comprising a mounting structure to which said external structure is mounted, wherein said mounting structure consists of only a first conductive regions, a second conductive region, and a third conductive region; wherein said first conductive region comprises conductive material in a first via, said second conductive region comprises conductive material in a second via, and said third conductive region comprises conductive material in a third via.

In a third aspect the claims define a circuit comprising an internal structure of an energy conditioner having A and B layers in the same plane and tabs extending to at least three side surfaces; a source, and a load, wherein said internal structure is connected in said circuit in a circuit 1 configuration; a circuit comprising an internal structure of an energy conditioner having A and B layers in the same plane and tabs extending to at least three side surfaces, a source, and a load, wherein said internal structure is connected in said circuit in a circuit 2 configuration; a circuit comprising an internal structure of an energy conditioner having A, B, and G master electrode components, a source, and a load, wherein said internal structure is connected in said circuit in a circuit 3 configuration; a circuit comprising an internal structure of an energy conditioner having A, B, and G master electrode components, a first source, a second source, a first load, and a second load, wherein said internal structure is connected in said circuit in a circuit 4 configuration; a circuit comprising an internal structure of an energy conditioner having A, B, and G master electrode components, a first source, a first load, and a second load, wherein said internal structure is connected in said circuit in a circuit 5 configuration; a circuit comprising said internal structure of an energy conditioner having A, B, and G master electrode components, a first source, a first load, and a second load, wherein said internal structure is connected in said circuit in a circuit 6 configuration.

In additional aspects, the invention comprises an assembly having an energy conditioner having an internal structure, a mounting structure; and wherein said internal structure is mounted on said mounting structure; wherein said mounting structure comprises no more than three separate conductive elements; an assembly comprising: an energy conditioner having an internal structure including components of A, B, and G master electrodes, and an external structure comprising conductive regions that conductively connect components of the A master electrode to one another, components of the B master electrode to one another, and components of the G master electrode to one another; a mounting structure; wherein said internal structure is mounted on said mounting structure; wherein said mounting structure consists of only a first conductive region, a second conductive region, and a third conductive region; and wherein said A master electrode contacts said first conductive region, said B master electrode contacts said second conductive region, and said G master electrode contacts said third conductive region.

In additional aspects, the claims define that said G master electrode includes a first G conductive integration region that and a second G conductive integration region spatially separated and not contacting said first G conductive integration region, wherein both said a first G conductive integration region and said second G conductive integration region contact said third conductive region.

In another aspect, the claims define an internal structure of an energy conditioner: wherein said internal structure has a left side surface, a right side surface, an upper side surface, a lower side surface, a top side surface, and a bottom side surface; wherein said internal structure comprises a dielectric material and a conductive material; wherein surfaces of said dielectric material and surfaces of said conductive material define said left side surface, said right side surface, said upper side surface, said lower side surface, said top side surface, and said bottom side surface; wherein said conductive material comprises a stack of at least seven conductive layers in the following order from top to bottom: A1; G1; B1; G1; A1; G1; and B1 wherein each A1 conductive layer has an A1 first tab that extends to said upper side surface near said left side surface and an A2 tab that extends to said lower side surface near said left side surface; wherein each G1 conductive layer has a G1 first tab that extends to said left side surface and a G2 tab that extends to said right side surface near; and wherein each B1 conductive layer has a B1 first tab that extends to said upper side surface near said right side surface and a B2 tab that extends to said lower side surface near said right side surface. In dependent aspects, each tab of the same type has a vertical overlap with all other tabs of the same type, and conductive integration regions conductively connect layers of the same type only to one another; and wherein additional conductive layers exist within the seven layer sequence.

BRIEF DESCRIPTION OF THE DRAWINGS

The figures show elements of embodiments of the inventions. The same reference number in different figures refers to identical elements or elements with similar structure or function.

FIG. 1A is a plan view of a conventional digital circuit board, also called a PC board, for a conventional high speed VLSI IC (Very Large Scale Integration Integrated Circuit) chip;

FIG. 1B is schematic partial edge side sectional view of the conventional board of FIG. 1A;

FIG. 2A is a partial side sectional view of a structure including a more than two terminal energy conditioner mounted via pads to a board, showing vias connecting the conditioner and conductive planes in the board;

FIG. 2B is another side sectional view showing power and ground planes and connection of the multi terminal conditioner to the power and ground planes;

FIGS. 3A to 3K are perspective views of exterior surfaces of novel energy conditioners disclosed herein, particularly showing surfaces of conductive band structures, C, and surfaces of dielectric material, D;

FIGS. 4A-O are plan views each showing arrangements of conductive elements of mounting surface structure, including conductive pad and/or via structure to which novel discrete component energy conditioners disclosed herein may be mounted;

FIGS. 5A and 5B are plan views showing geometric relationships of vias;

FIG. 6A is a schematic view showing a novel combination of a novel energy conditioner on an arrangement of mounting surface structure elements including conductive pads and vias, with two vias per pad;

FIG. 6B is a schematic view showing a novel combination of a novel energy conditioner on an arrangement of mounting surface structure elements including conductive pads and vias, with two vias per pad, and a central pad that extends further than the outer two pads such that the central pad contacts conductive terminals, caps, or bands on left and right hand sides of the energy conditioner;

FIG. 6C is a top plan view showing a novel combination of a novel energy conditioner on an arrangement of mounting surface structure elements including conductive pads and vias showing overlap of terminals of the conditioner with vias;

FIG. 7 is a partial schematic of circuit one for use with an energy conditioner having A, B, and G master electrodes;

FIG. 8 is a partial schematic of circuit two for use with an energy conditioner having A, B, and G master electrodes;

FIG. 9 is a partial schematic of circuit three for use with an energy conditioner having A, B, and G master electrodes;

FIG. 10 is a partial schematic of a circuit four for use with an energy conditioner having A, B, and G master electrodes;

FIG. 11 is a partial schematic of a circuit five for use with an energy conditioner having A, B, and G master electrodes;

FIG. 12 is a partial schematic of a circuit six for use with an energy conditioner having A, B, and G master electrodes;

FIG. 13 is an exploded view of a stack of four plates internal to a novel energy conditioner in which the plate elements have been displaced laterally in the page;

FIG. 14 is a schematic plan view of an assembly of the plates of FIG. 13;

FIG. 15 is an exploded view of a stack of three plates internal to a novel energy conditioner in which the plate elements have been displaced laterally in the page;

FIG. 16 is an exploded view of a stack of three plates internal to a novel energy conditioner in which the plate elements have been displaced laterally in the page;

FIG. 17 is an exploded view of a stack of three plates internal to a novel energy conditioner in which the plate elements have been displaced laterally in the page;

FIG. 18 is an exploded view of a stack of three plates internal to a novel energy conditioner in which the plate elements have been displaced laterally in the page;

FIG. 19 is an exploded view of a stack of three plates internal to a novel energy conditioner in which the plate elements have been displaced laterally in the page;

FIG. 20 is an exploded view of a stack of three plates internal to a novel energy conditioner in which the plate elements have been displaced laterally in the page;

FIG. 21 is an exploded view of a stack of four plates internal to a novel energy conditioner in which the plate elements have been displaced laterally in the page;

FIG. 22 is a set of exploded views of stacks 22A-22H of plates of novel energy conditioners in which the plates of each stack have been displaced vertically in the page;

FIG. 23 is a set of exploded views of stacks 23A-23C of plates of novel energy conditioners in which the plates of each stack have been displaced vertically in the page;

FIG. 24 is an exploded view of a stack of plates of a novel energy conditioner in which the plates have been displaced vertically in the page;

FIG. 25 is an exploded view of a set of two plates of a novel energy conditioner in which the plates have been displaced vertically in the page;

FIG. 26 is a perspective view of an exterior surface of a novel energy conditioner including the stack of two plates shown in FIG. 25;

FIG. 27 is an exploded view of a set of two plates of a novel energy conditioner in which the plates have been displaced vertically in the page;

FIG. 28 is a perspective view of an exterior surface of a novel energy conditioner including the stack of two plates shown in FIG. 27;

FIG. 29 is an exploded view of a set of two plates of a novel energy conditioner in which the plates have been displaced vertically in the page;

FIG. 30 is a perspective view of an exterior surface of a novel energy conditioner including the stack of two plates shown in FIG. 29;

FIG. 31 is an exploded view of a set of two plates of a novel energy conditioner in which the plates have been displaced vertically in the page;

FIG. 32 is a perspective view of an exterior surface of a novel energy conditioner including the stack of two plates shown in FIG. 31; and

FIG. 33 is an exploded view of a stack of 8 plates of a novel energy conditioner in which the plates have been displaced vertically in the page.

DETAILED DESCRIPTION OF THE EMBODIMENTS

FIG. 1A shows PC board 1 having sides 2, 3, 4, and 5, top surface 6, array 7 of structure for mounting discrete capacitors, and region 8 for mounting an IC. Each side of array 7 defines plural rows, such as rows 9 and 10. Each element of array 7 represents mounting structure for mounting a discrete capacitor. Conventional PC boards often have an array including at least two rows of structure for mounting capacitors. Each row may have several to tens of array elements for mounting capacitors. The board is designed so that capacitors mounted to the elements of array 7 sufficiently decouple the power to the IC from active circuitry so that the IC and any other coupled circuit elements functions as intended.

Conventional capacitors are two terminal discrete devices.

FIG. 1B shows a portion of board 1, a source of electrical power 11, a ground 12, mounting structure 13 corresponding to one element of array 7, mounting structure 14 corresponding to another element of array 7, power plane 15, and ground plane 16. In addition, FIG. 1B shows three vias extend down from each mounting structure element, such as vias 17, 18, 19 below mounting structure 13. Use of more than two vias enables mounting unconventional devices, such as 3 terminal energy conditioners.

In operation, power source 11 distributes electrical power to circuit elements mounted to board 1 via conductive connection of power source 11 to power plane 15. Ground plane 16 conductively connects to ground 12. Vias 17 and 19 conductively connect to power plane 15. Via 18 does not conductively connect to power plane 15 and instead passes through an aperture in power plane 15 to ground plane 16. Power plane 15 is above ground plane 16.

FIG. 2A shows assembly 200 including energy conditioner 201 mounted on board 1. Board 1 includes pads 202, 203, 204 that separate conditioner 201 from board surface 6 by a distance 205 as indicated by the distance between facing arrows 206. Vias 17, 18, 19, have a width 207 as indicated by the distance between facing arrows 209.

FIG. 2B shows additional structure underneath conditioner 201 including additional power, ground, and/or signal planes 208, 209, 210, and aperture 211 through which the conductive path in via 18 passes without shorting to power plane 15. Additional power, ground and/or signal planes may exist in any particular board.

In operation, power feed from source 11 through one or more power planes provides power for active circuitry in the IC mounted in region 8 to operate. Conditioners mounted to the elements of array 7, one conditioner per array element, decouple transients otherwise induced in power due to switching and the like in the active circuitry of the IC.

FIGS. 3A to 3K are perspective views of exterior surfaces 3A to 3K of certain novel energy conditioners disclosed herein. In FIGS. 3A to 3K, “C” denotes electrically conductive material and “D” denotes dielectric material (electrically insulating). The electrically conductive portions, C, may be referred to herein as bands or outer terminals.

FIG. 3A shows conductive bands C, and FIG. 3G shows conductive bands C, for purpose of discussion with energy conditioner internal structure disclosed herein below.

FIG. 4A-4O each show one arrangement of conductive elements of mounting structure for mounting a single one of the novel discrete energy conditioners. These arrangements are also referred to as land patterns. The mounting surface may be a surface of a PC board, first level interconnect, or semiconductor chip.

FIG. 4A shows an arrangement 4A of mounting surface structure including a set of three generally rectangularly shaped conductive pads 401, 402, 403. Conductive pads 401, 402, 403, have relatively long sides (unnumbered) and relatively short sides. The relatively short sides are labeled 401A, 402A, 403A. Relatively short sides 401A, 402A, 403A are aligned with one another such that a straight line segment could contact substantially all of short sides 401A, 402A, 403A. Conductive pad 401 contains vias 401V1, 401V2. Conductive pad 402 contains vias 402V1, 402V2. Conductive pad 403 contains vias 403 V1, 403V2. Vias 401 V1, 402V1, and 403 V1 are aligned such that a single line segment could intersect them. Vias 401V2, 402V2, and 403V2 are aligned such that a single line segment could intersect them.

In alternatives to arrangement 4A, pads may have different sizes, lengths, or widths from one another. For example, pad 402 may be shorter than pads 401, 403.

In another alternative to arrangement 4A, outer pads 401, 403 may have a different shape than central pad 402. For example, outer pads 401, 403 may include convex central regions and/or flared end regions. For example, outer pads 401, 403 may be the same length as one another but shorter or longer than central pad 402.

In another alternative to arrangement 4A, certain vias may have a diameter larger than the width or length of the pad to which they are attached such that the via is not entirely contained within the footprint of a conductive pad. For example, a via diameter may be equal to a width of a conductive pad, 1.5, 2, or 3 times a width of the conductive pad.

In another alternative to arrangement 4A, certain vias may have different cross-sectional diameters from one. For example, cross-section diameters of vias connecting to the central pad 402 may be ⅓, ½, 1, 1.5, 2, or 3 times the cross-sectional diameter of vias connecting to outer pads 401, 403.

In another alternative to arrangement 4A, vias 402V1, 402V2 may be spaced from one another by more than or less than the spacing between vias 401V1, 401V2 and the spacing between 403V1, 403V2.

In another alternative to arrangement 4A, each conductive pad may contain one, two, three, or more vias. For example, each conductive pad 401, 402, 403 may contain a single via. For example, pads 401 and 403 may contain 2 or 3 vias and pad 402 may contain one via. For example, pads 401 and 403 may contain 1 via and pad 402 may contain 2 or 3 vias.

In another alternative to arrangement 4A, the pads may not exist in which case just conductive vias exist in one of the foregoing arrangements. For example, two parallel rows of three vias.

In another alternative to arrangement 4A, some pads may have connected vias and some may not. For example, central pad 402 may contain 1, 2, 3, or more vias and outer pads 401, 403 may contain no vias. For example, central pad 402 may contain no vias and each outer pad 401, 403, may contain 1, 2, 3, or more vias.

In another alternative to arrangement 4A, the cross-sections of vias may not be circular, such as elliptical, elongated, or irregular.

FIGS. 4B-4L show various arrangements of the alternatives discussed above.

FIG. 4B shows arrangement 4B of mounting structure having vias of pad 402 more widely spaced from one another than the spacing between vias of either pad 401 or pad 403.

FIG. 4C shows arrangement 4C of mounting structure having vias having elongated elliptical cross-sections.

FIG. 4D shows arrangement 4D of mounting structure having a single via in each one of pads 401, 402, 403.

FIG. 4E shows arrangement 4E of mounting structure having outer pads 401, 403 having one centrally located via.

FIG. 4F shows arrangement 4F of mounting structure having pads 401, 402, 403 having no vias. In this alternative, conductive lines may radiate along the surface of the structure from each pad.

FIG. 4G shows arrangement 4G of mounting structure having pads 401, 402, 403 each having three vias, each via in each pad aligned with one via in each one of the other two pads.

FIG. 4H shows arrangement 4H of mounting structure having a single via in each pad, and in which the central pad 402 is short than the outer pads 401, 403.

FIG. 41 shows arrangement 41 of mounting surface structure having equal length pads 401, 402, 403, and in which the central pad 402 connects to only one via whereas the outer pads 401, 402 connect to 2 vias.

FIG. 4J shows arrangement 4J of mounting structure having three pairs of vias, and no pads.

FIG. 4K shows arrangement 4K of mounting structure having outer pads 401, 403 connecting to two vias and central pad 402 connecting to three vias.

FIG. 4L shows arrangement 4L of mounting structure having central pad 402 connecting to one via and outer pads 401, 403 having no vias.

FIG. 4M shows mounting structure 4M having cental pad 402 extending further than pads 401, 403, and vias in central pad 402.

FIG. 4N shows mounting structure 4N having via 501 having a larger diameter than via 502. Moreover, larger via 501 is more centrally located than the other smaller diameter vias. That is, FIG. 5N contemplates benefits from conductively filled or lined vias of different dimensions from one another, and in which the larger vias are more centrally located relative to the energy conditioner to which they connect.

FIG. 4O shows mounting structure 40 having central pad 402 extending symmetrically further than pads 401, 403.

Preferably, vias in each pad are spaced symmetrically on either side of the center of the pad. Preferably, the arrangement of vias is symmetric about the center point of central pad 402.

The inventors contemplate all variations of arrangements of mounting structures (pads and vias combinations, sizes, and shapes) and energy conditioners mounted therein that provide conductive connection between the conductive elements of the mounting structure and A, B, and G master electrodes (defined herein below) internal to the energy conditioner. The A, B, and G master electrodes either have regions forming part of the surface of the energy conditioner or internally physically contact conductive bands (outer electrodes) forming part of the surface of the energy conditioner. Thus, all variations of the conductive band structures and mounting structure that provide suitable connection to the A, B, and G master electrodes are contemplated. In addition, the inventors contemplate all variations of energy conditioners lacking conductive band (outer electrodes) that can be mounted on and soldered (or conductively pasted) to the board thereby conductively connecting the A, B, and G master electrodes to the conductive regions of the mounting structure.

Herein, conductive integration region, means either a conductive band or equivalent solder providing the contact to tabs of layers of a master electrode thereby conductively integrating those conductive layers to one master electrode. Tabs mean those portions of conductive layers of an internal structure of an energy conditioner that extend to the upper, lower, left or right side surfaces of the internal structure. Main body portions of conductive layers of an internal structure means those portions of the conductive layers that do not extend to the upper, lower, left or right side surfaces of the internal structure.

Thus, the inventors contemplate all combinations of the mounting structure configurations for mounting a conditioner to a surface and (1) either conductive band configurations or exposed A, B, and G master electrodes surfaces of energy conditioners that provide suitable connections for the A, B, and G master electrodes.

Some combinations of novel energy conditioner and surface mounting structure provide (1) a first conductive and mechanical contact, such as a solder connection, to at least one and more preferably all conductive bands connected to one side of the A and B master electrodes, (2) a second conductive and mechanical contact, such as a solder contact, to at least one and preferably all conductive bands connected to the opposite side of the A and B master electrodes, and (3) a third conductive contact to at least one and preferably all bands connected to both of the opposite ends of the G master electrode. The foregoing reference to electrical contact includes situations where DC current is blocked, such as where a dielectric cap or layer exists somewhere along a via.

FIG. 5A shows geometric values and dimensions for one currently preferred mounting structure.

FIG. 5B shows geometric values and dimensions for another currently preferred mounting structure.

It has been determined by numerical calculations that the values shown in FIGS. 5A and 5B provided superior decoupling when 0603 X2Y type energy conditioners are mounted thereto. 0603 X2Y type capacitors have a capacitance of 1 to 100 nano farads, and nominal length, width, and thickness and height of 0.8, 0.6, 0.6, and 0.4 millimeters, respectively, as indicated for example by the URL: http://www.yageo.com/pdf/X2Y_series_—10.pdf?5423212=EE8DCCAFD2263EBA74A6443AF7A8BC75&4620207=.

FIGS. 6A-6B each schematically show a combination of a novel energy conditioner having a certain exterior surface structure in operable location on mounting structure.

FIG. 6A shows an arrangement 6A of energy conditioner 601 on mounting structure 4A. Conditioner 601 had exterior surface structure 3A. Conductive band C1 is on top of conductive pad 401. Part of conductive band C2 is on top (since its ends extend beyond) of a first end of conductive pad 402. Conductive band C3 is on top of pad 403. Conductive band C4 is on top of a second end of conductive pad 402. The first and second ends of conductive pad 402 are on opposite sides of energy conditioner 601 from one another. Vias and portions of pads hidden from view are shown in dashed lines.

FIG. 6B shows arrangement 6B of energy conditioner 602 mounted on arrangement 4O of FIG. 4O. Conditioner 602 also has exterior surface structure 3A. Conductive band C1, C3 contact near opposite ends of conductive pad 402. Conductive bands C4, C2 contact respectively to conductive pads 401, 403.

FIG. 6C shows arrangement 6C of energy conditioner 603 mounted on mounting structure 4J showing alignment of conductive bands of conditioner 603, and also solder, on vias of mounting structure 4J.

FIGS. 7-12 show circuits including an energy conditioner having A, B, and G master electrodes, which relate to the special properties of such conditioners. The inventors have determined that connection of the G master electrode at at least two points, preferably at two points on opposite sides from one another, provides significant advantages. This is in spite of the fact that the G master electrode is a single conductive structure wherein location of connection would not be relevant in a lumped circuit representation. Circuit diagrams rely upon a lumped circuit model for accuracy of representation. In order to represent this geometric requirement relating to distributed circuit design in lumped circuit figures, the inventors schematically represent the energy conditioners as devices having at least 3 terminal device, with A, B, G terminals. More terminals may exist for each master electrode, and additional master electrodes may be integrated into the same component. The inventors have also determined that relative locations of A, B, and G electrode terminals relative to the A, B, and G master electrode structures, may affect performance of the energy conditioners. FIG. 7-12 therefore show circuits peculiar to this type of energy conditioner.

In FIGS. 7-12, external terminal A conductively connects to the A master electrode, external terminal B conductively connects to the B master electrode, external terminal G1 conductively connects to the G master electrode. More specifically as used in FIGS. 7-12, embodiments having at least 2 G external terminals, such as a G1 and G2, a first side of the G master electrode, and external terminal G2 conductively connects to a different side of the G master electrode.

FIGS. 7-12 each show conditioner 700, and external terminals A, B, G1, and G2. The G master electrodes is represented by portions 702, 705, and the A and B master electrodes are represented respective by flat plate elements 703, 704. Internal to conditioner 700, the G master electrode is spaced between or acts to shield the effects of charge buildup on the A master electrode from the B master electrode. This is schematically represented by the portion 702 of the G master electrode extending between the flat plate elements 703, 704 of the A and B master electrodes. G master electrode portion 705 schematically represents shielding by the G master electrode of the A and B master electrodes relative to space outside conditioner 700.

FIG. 7 show a circuit 1 configuration for a conditioner 700 having A, B, and G master electrodes. In circuit one, external terminal A conductively connects to node AS of conductive path S between a source of electrical power, SOURCE, and a load, LOAD. In addition, external terminal B conductively connects to node BR of a return conductive path R between LOAD and SOURCE. In addition, external G1 and G2 terminals both conductively connect to a source of ground/constant potential P. Arrows above and below conductive paths between SOURCE and LOAD indicate that current flows in a loop.

FIG. 8 shows a circuit 2 configuration wherein external terminal A is tied to node AS on path S, external terminal B is tied to node BS also on path S, external terminal G1 is tied to node G1R on path R, and external terminal G2 is tied to node G2R also on path R.

FIG. 9 shows a circuit 3 configuration wherein external terminal A is tied to node AS on path S, external terminal B is tied to node BR on path R, external terminal G1 is tied to node G1R on path R, and external terminal G2 is tied to node G2R on path R.

FIG. 10 shows a circuit 4 configuration wherein external terminal A is tied to a node on path S, and external terminals G1, B, and G2 are tied to nodes on path R.

FIG. 11 shows a circuit 5 configuration wherein external terminal A is tied to a node on source path Si from a source to a first load, L1, external terminal B is tied to a node S2 on a path from a source to a second load L2, and external terminals G1 and G2 are tied to a common return path CR.

FIG. 12 shows a circuit 6 configuration wherein external terminal A is tied to a node on path R (see element R in FIG. 7), external terminal B is tied to a node on path R, and external terminals G1 and G2 are tied to nodes on path S (see element S in FIG. 7).

Relation of Internal Structure to External Structure of Energy Conditioners

FIGS. 13-33 generally show structure internal to the external surface 3A to 3K of FIGS. 3A-3K. The configuration of conductive layers of FIGS. 13-33 can be arranged relative to the external surfaces 3A to 3K so that the conductive layers of the A master electrode contact the same conductive band or bands as one, the conductive layers of the B master electrode contact the same conductive band or bands as one, and the conductive layers of the G master electrode contact the same conductive band or bands as one. Alternatively, instead of conductive bands, solder applied to the sides of the conditioners may conductively contact the conductive layers of the A master electrode to one another, the conductive layers of the B master electrode to one another, and the conductive layers of the G master electrode to one another. The same solder contacts may also contact corresponding conductive regions of the mounting structures shown in FIGS. 4A to 40.

Meaning of “Plate”, and Interconnector and IC Alternative Embodiments

The term “plate” herein generally is used to simplify explanation by defining a combination of a dielectric under layer with none, one, or more than one distinct conductive over layers. However, the relevant structure is the sequence of conductive layers separated by dielectric material. The hidden surface of the structures referred as plates in the following figures represents a dielectric surface; that is, dielectric material vertically separating the defined conductive layers from one another. In discrete energy conditioner component embodiments, the structure are often formed by layering dielectric precursor material (green material) with conductive layer precursor material (conductive paste or the like), firing that layered structure at temperatures sufficient to convert the dielectric precursor to a desired structurally rigid dielectric material and to convert the conductive precursor layer to a high relatively conductivity (low resistivity) conductive layer. However, embodiments formed in interconnects and semiconductor structures would use different techniques, including conventional lithographic techniques, to fabricate equivalent or corresponding structures to those shown in FIGS. 13-25, 27, 29, 31, and 33. Importantly, the conductive bands and solder connections for stacked layers discussed herein below would in many cases be replaced by an array of conductively filled or lined vias selectively connecting conductive layers of the same master electrode to one another. Preferably, those vias would be spaced to selectively contact the tab regions of the A, B, and G layers discussed herein.

Regardless of the mechanism of formation, it is the existence of the master electrodes' morphologies, assembly with external conductive structure, assembly with mounting structure, and integration into circuits 1-6 that are functionally important for decoupling.

Common Features of Internal Structure of Energy Conditioners

A master electrode refers to the conductive layers or regions internal to an energy conditioner and the structure internal to the energy conditioner physically contacting those conductive layers or regions so that they form one integral conductive structure.

Internal structure of energy conditioners includes conductive layers or regions spaces by dielectric material from other conductive layers or regions. The conductive layers or regions each have tab regions that extend to an edge or periphery of the dielectric material. An edge of each tab region of each conductive layer is contacted to external surface conductive structure. The external surface conductive structure may be either conductive bands integral to the discrete energy conditioner or by solder employed also to mount the energy conditioner internal structure to mounting structure. In energy conditioner internal structures having a plurality of conductive layers or regions designed to form a single master electrode, tabs of those conductive layers or regions are vertically aligned in the stack of layers so that a single conductive tab may conductively connect those conductive layers or regions to thereby form a master electrode.

Alternatively, or in addition to conductive bands or solder connecting to externally exposed edges of conductive layers or regions of a master electrode, conductively filled or lined vias may selectively connect to the same conductive layers or regions.

RELATIONSHIP BETWEEN INTERNAL STRUCTURES OF ENERGY CONDITIONERS AND EXTERNAL STRUCTURE OF ENERGY CONDITIONERS

Each one of the internal structures of energy conditioners shown in FIGS. 13-25, 27, 29, 31, and 33 may reside in each one of external surface 3A to 3K of FIGS. 3A-3K in two distinct configurations. In one configuration, a first set of tabs of a G conductive layer of the G master electrode are on the left and right sides (as shown in FIGS. 3A to 3K) of the external surfaces 3A to 3K. In the other configuration, the same first set of tabs of that same G conductive layer of the G master electrode are on the upper and lower sides (as shown in FIGS. 3A to 3K) of the external surfaces 3A to 3K. In each configuration of the internal structures of energy conditioners shown in FIGS. 13-25, 27, 29, 31, and 33 and external surfaces 3A to 3K, the conductive layers of the A and B master electrodes each have a region that extends into contact with at least one conductive band (or solder, when solder is applied) of the corresponding one of external surfaces 3A to 3K.

Relationship Between Internal Structures of Energy Conditioners, External Structure of Energy Conditioners, and Circuits 1-6

At least in circuits wherein the A and B master electrode are not tied to the same conductive path of the circuit (circuits 1, 3, 4, and 5; see FIGS. 7-12), the conductive layer or layers of the A master electrode do not contact the same conductive band on external surfaces 3A to 3K as the conductive layer or layers of the B master electrode.

At least in circuits wherein the A master electrode is not tied to the same conductive path of the circuit as the G master electrode (circuits 1-6; see FIGS. 7-12), the conductive layer or layers of the A master electrode do not contact the same conductive band on external surfaces 3A to 3K as the conductive layer or layers of the G master electrode.

At least in circuits wherein the B master electrode is not tied to the same conductive path of the circuit as the G master electrode (circuits 1,2 and 6; see FIGS. 7-12), the conductive layer or layers of the B master electrode do not contact the same conductive band on external surfaces 3A to 3K as the conductive layer or layers of the G master electrode.

Features Common to Various Internal Structures Shown in FIGS. 13-33.

FIGS. 13-33 all show structures wherein a G master electrode has at least two distinct tabs. As used herein, tab does not require a narrowing or necking compared to a body. Instead, it requires only extension to an edge of a dielectric structure. However, many of the conductive layers of G master electrodes shown in FIGS. 13-33 include tab regions that are narrowed or necked compared to the region of the same conductive layer not adjacent the edge of dielectric structure.

FIGS. 13-16, 21, 22, 23 show conductive layers of an A master electrode and conductive layers of a B master electrode that each have only have one distinct tab.

FIGS. 17, 18, 19, 24, 25, 27, 29, 31, and 33 show conductive layers of an A master electrode and conductive layers of a B master electrode that each have two distinct tabs.

FIGS. 20 shows conductive layers of an A master electrode and conductive layers of a B master electrode that each have three distinct tabs.

FIGS. 13, 16, 17, 18, 19, 20, 21, 22, 23, and 24 show plates having conductive layers of A and B master electrodes that extend to portions of at least three edges of their plate.

FIGS. 13-25, 27, 29, 31, and 33 show internal structure of novel energy conditioners.

FIGS. 28, 30, and 32 show external structure of novel energy conditioner embodiments of FIGS. 27, 29, and 31, respectively;

FIGS. 13-25, 27, 29, and 31 show plates that each have a conductive layer of an A master electrode and a conductive layer of a B master electrode in the same plate.

FIGS. 13-24 show stacks of plates that each have a conductive layer of an A master electrode and a conductive layer of a B master electrode in the same plate, and wherein two such plates are mirror images of one another about a line of symmetry extending vertically or horizontally in the plane of the paper of each figure.

FIGS. 13-24 show both (1) structures that each have a conductive layer of an A master electrode and a conductive layer of a B master electrode in the same plate and (2) stacks of plates wherein a conductive layer of an A master electrode on one plate has a region of substantial overlap with a conductive layer of a B master electrode on another plate.

FIGS. 13-24 show structures that include stacks of plates wherein (1) a first plate has a surface including a conductive layer of an A master electrode and a conductive layer of a B master electrode, (2) a second plate also has a surface including a conductive layer of an A master electrode and a conductive layer of a B master electrode, the conductive layer of the A master electrode in the first plate and the conductive layer of the B master electrode in the second plate have a region of substantial overlap, and (3) a third plate resides between the first two plates and has a conductive layer of a G master electrode extending throughout the region of substantial overlap.

FIGS. 25, 27, and stacks 22A and 22B of FIG. 22 show structures including only a single plate having a surface including a conductive layer of an A master electrode and a conductive layer of a B master electrode, and a single plate having a surface including a conductive layer of a G master electrode.

FIGS. 29 and 31 show structures including only a two plate each having a surface including a conductive layer of an A master electrode and a conductive layer of a B master electrode, and a single plate there between having a surface including a conductive layer of a G master electrode.

FIGS. 21, 22, and 23 show structures including at least one plate having a surface including a conductive layer of an A master electrode, a conductive layer of a B master electrode and a conductive layer of a G master electrode between the aforementioned conductive layers of the A and B master electrodes.

FIGS. 22 stacks 22E and 22G, and FIG. 23 stacks 23A, 23B, and 23C each show structures including plates having a substantial region of a conductive layer of an A master electrode opposing a corresponding region of a conductive layer of a B master electrode on another plate having no intervening conductive layer of a G master electrode there between.

FIGS. 22 stack 22H and FIG. 23 stack 23C show structures in which the outermost conductive layers on one or both ends of the stack have a sequence of two or three conductive layers.

FIG. 33 shows a structure including a stack of plates wherein: (1) each plate has a surface including a conductive layer of only one master electrode, the sequence of conductive layers follows the pattern A, G, B, G, A, G, B; (2) conductive layers of the A and B master electrodes substantially overlap; (3) conductive layers of the G master electrode extend substantially throughout the area of overlap; (4) each conductive layer of the A master electrode has A tabs extends to front and back edges of the corresponding plate; (5) each conductive layer of the B master electrode has B tabs extends to front and back edges of the corresponding plate without overlapping any of the A tabs; and (6) each conductive layer of the G master electrode extends to left and right side edges of the corresponding plate.

DETAILED DESCRIPTION OF FIGS. 13-33

In the following figures, plates of a stack shown displaced horizontally or vertically in the page exist in the stack in the sequence as expanded horizontally or vertically in the page. Each stack includes a top and a bottom spaced from one another in a direction perpendicular to the face of the paper of the figures. In addition, each plate of each stack is shown in the figures as having in the plane of the paper a left side LS, right side RS, upper side US, and lower side LLS.

FIG. 13 shows stack 1300 of plates 1300A, 1300B, and 1300C. Plate 1300A includes dielectric material uniformly extending to the LS, RS, US, and LLS of stack 1300. Conductive layer A1 designed to be part of the A master electrode and conductive layer B1 designed to be part of the B master electrode reside on the surface of dielectric material of plate 1300A. Conductive layers A1 and B1 are separated from one another by exposed dielectric surface D. Conductive layer A1 has a tab A1 T extending to the entire LS, and also the far left sides of the US and LLS. Conductive layer B1 has a tab B1T extending to the entire RS, and also to the far right sides of the US and LLS. Conductive layer A1 has a main body portion A1M extending the majority of the distance from the LS to the RS on the upper half of plate 1300A. Conductive layer B1 has a main body portion B1M extending the majority of the distance from the RS to the LS on the lower half of plate 1300A.

Plate 1300B includes dielectric material on which resides conductive layer G1. Conductive layer G1 has tab G1T1 extending to a central region of the US. Conductive layer G1 has tab G1T2 extending to a central region of the LS. Conductive layer G1 has a main body portion B1M between tabs G1T1 and G1T2.

Plate 1300C includes conductive layer A2 for the A master electrode, conductive layer B2 for the B master electrode. Conductive layers A2 and B2 are separated from one another by exposed dielectric surface D. Conductive layer A2 has a tab A2T extending to the entire LS, and also the far left sides of the US and LLS. Conductive layer B2 has a tab B2T extending to the entire RS, and also to the far right sides of the US and LLS. Conductive layer A2 has a main body portion A2M extending the majority of the distance from the LS to the RS on the lower half of plate 1300A. Conductive layer B2 has a main body portion B2M extending the majority of the distance from the RS to the LS on the upper half of plate 1300A.

FIG. 14 schematically shows the stack of layers 1300C, 1300B, 1300A wherein main bodies A1M and B2M have a region of substantial overlap, and main bodies A2 and B1M have a region of substantial overlap, and conductive layer G1M extends over a substantial portion of the regions of overlap. Preferably, the regions of overlap occupy at least 20, more preferably at least 40 and more preferably at least 60 percent of the area of the A1M conductive layer. Preferably, the G1M layer extends over lat least 40, and more preferably at least 60 percent of the areas of overlap.

The stack of FIGS. 13 and 14, once formed, may be mounted to mounting structure on a PC board or interconnect, and soldered in place to complete the connections of the A, B, and G master electrodes. Alternatively, the structure of FIGS. 13 and 14 may be fabricated with conductive bands forming a portion of the external structure thereby completing formation of the A, B, and G master electrodes.

FIGS. 13 and 14 are only exemplary of a sequence of layers forming an energy conditioner using the plates 1300A, 1300B, 1300C. Alternatively to the FIGS. 13 and 14 stack embodiment, a stack may have an integral number of repeats of the sequence 1300A, 1300B, 1300C. Alternatively, a stack may have the sequence 1300A, 1300B, 1300C followed by any integral number of repeats of either the sequence 1300B, 1300C or the sequence 1300A, 1300B. Alternatively, one, two, or more than two 1300B plates may reside at either or both of the top and the bottom of a stack.

FIGS. 15-20 show alternative shapes for conductive layers of A, B, and G master electrodes wherein each plate having an conductive layer for an A master electrode also has a conductive layer for a B master electrode. The same alternatives and methods of assembly just noted for the FIGS. 13 and 14 embodiment apply to the FIGS. 15-20 stack embodiments.

FIG. 15 shows conductive layer A1M having tab A1T extending over only a portion of LS and over no other side.

FIG. 16 is identical to FIG. 13. FIG. 17 shows a stack of plates including plates 1700A, 1700B, and 1700C. Plate 1700A having conductive layer A1M having tabs A1T1 and A1T2 separated by exposed dielectric D at the center of the LS. Plate 1700B includes conductive layer of a G master electrode include main body portion G1M, and tab portions G1T1, G1T2, G1T3, and

G1T4 in each side edge. Plate 1700C includes conductive layers A2 and B2 for the A and B master electrodes respectively. Tabs of the A1 and A2 plated, the B1 and B2 plates in the stack are vertically aligned. Dielectric surface is exposed at the center of each side of plate 1700A and 1700C. The existence of exposed dielectric surfaces vertically aligned in the stack of plates, and existing on each side of the plates having conductive layers for the A and B electrodes, enables the existence of G tabs aligned on each side of the stack to be contacted by a conductive connecting material (conductive band or solder) without shorting the G tabs to the A or B tabs. In one alternative to FIG. 17, the G1 layer has only two tabs that extend to either the US and LLS or the LS and RS.

FIG. 18 shows a stack of plates wherein the conductive layers for the A master electrode each have two tabs, and those tabs are not completely aligned with one another. FIG. 18 shows layer A1 and A2 having tabs A1T1 and A2T1 that only partially align at the left side of the US. Similarly the remaining tabs for the A and B layers have partial overlap.

FIG. 19 shows a stack similar to that shown in FIG. 18 except that extent of the tabs of the A1, B1, A2, and B2 layers is reduced so that the exposed dielectric D extends over the center of the LS and RS, and the G1 layer has four tabs two of which extend to the center of the LS and RS. In one alternative to FIG. 19, the G1 layer has only two tabs that extend to either the US and LLS or the LS and RS.

FIG. 20 shows a stack wherein the A1 layer has tabs that extend to portions of the LS, US, and LLS, but not to any corner, and not to the center of the LS. This configuration enables up to three separate conductive connections on the side of the stack to the A layer, and likewise to the B layer, for example with the external structure 3K's left side and right side conductive bands connecting to the A and B layers.

FIG. 21 shows a stack 2100 including plates 2100A, 2100B, 2100C, and 2100D. Each one of plates 2100A and 2100C contain conductive layers for the A, B, and G master electrodes separated by dielectric D. Plate 2100A includes conductive layer A1 that includes tab A1T1 extending over the entire LS and portions of the left end of the US and LLS. Plate 2100A also includes conductive layer B1 that includes tab B1 extending over the entire RS and portions of the right end of the US and LLS. Between A1 and B1 resides conductive layer G1 that winds between the main body portions of A1 and B1 to tabs G1T1 and G1T2 in the center of the US and LLS. Plate 2100B includes layer G2 having tabs G2T1 and G2T2 in the center of the US and LLS. Plate 2100C includes layers A2, B2, and G3, and it is a mirror image of plate 2100A. Plate 2100D is identical to plate 2100B. The stack 2100 has all tabs for the G layers aligned in the center of the US and LLS so that the G layers between A and B layers as well as the G layers above or below A and B layers are integrated into the G master electrode. Alternatively, stack sequences are feasible, including the plate sequence 2100A, 2100B, 2100C, and 2100D followed or preceded by any number of repetitions of either 2100C, 2100D or 2100A, 2100B; by including 2 or more of plates of the form of 2100B/2100D instead of single plates, and not including the central G conductive layer in one, or alternating ones of the plates of the form 2100A/2100C, and including one, two, or more plates of the form of 2100B/2100D at one or both ends of the stack.

FIG. 22 shows stacks, 22A to 22H each including additional alternative stacks of the plates 2100A to 2100D. Note in particular that stacks 22A, 22B, and 22C have less than 4 plates; one, two, and three plates or layers, respectively.

FIG. 23 shows stacks 23A, 23B, and 23C which employ the same plates 2100A, 2100B, 2100C, 2100D as the stack of FIG. 21. However, FIG. 23's sequence differs from the sequences in FIGS. 21 and 22 in that there are adjacent pair 2301 of mirror image layers M, M′ where overlap regions of conductive surfaces for A1 and B1 layers oppose one another without an intervening conductive layer for the G master electrode, like layers G2 and G4 of FIG. 21. There are also plates where G conductive layers like layers G2 and G4 do bracket a layer in which A, B, and G conductive layers reside, like plate 2302. FIG. 23 shows paired layers M, M′. Alternatively, stack sequences may include any number of repeats of the pair of M, M′ adjacent to one another with or without any of the layers having a single G layer, like layers G2 and G4 of FIG. 21. Preferably, there is an odd total number of layers in which conductive layers exist, and an odd total number of layers in which only layers forming part of the G master electrode exist.

FIG. 24 shows a stack containing plates having various shapes from the preceding embodiments (a top plate having the same conductive pattern as the left side plate in FIG. 18, a second from top plate having the conductive pattern of G1 in FIG. 13, a third plate having the conductive pattern of a plate from FIG. 19, a fourth plate representing a dielectric spacer region, and a fifth plate like the third plate) showing the plates of different shapes and sizes and of non-uniform spacings may exist in stacks contemplated by the inventors. All such modifications and variations of layers are within the scope contemplated.

FIGS. 25-28 are views of energy conditioners including conductive layers on only two planes and various external structures.

FIG. 25 shows stack 25A containing plate 2500A and 2500B. An upper surface of plate 2500A is formed from surfaces of conductive layer A1, conductive layer B1, and exposed dielectric material D. An upper surface of plate 2500B is formed from conductive layer G1 and exposed dielectric material D. A1 has tabs A1T1 near the left hand end of the US and A1T2 at near lower left hand end of the LLS. G1 has tabs G1T1 in the middle of the US and G1T2 in the middle of the LLS. A1 does not extent to the RS, and B1 does not extend to the LS. A1 has main body portion A1M. B1 has main body portion B1M. A1M extends to a location closer to the US and RS than the LLS and LS. B1M extends to a location closer to the LS and LLS than the US and RS.

FIG. 26 schematically shows an energy conditioner defined by one arrangement of (1) stack 25A and (2) external structure 3A of FIG. 3A. In this arrangement, tabs A1T1 and A2T2 contact internal surfaces of conductive band C1, tabs G1T1 and G1T2 respectively contact internal surfaces of bands C2 and C4, and tabs B1T1 and B1T2 contact internal surfaces of conductive band C3.

In one alternative external structure, the third conductive integration structure and the fourth conductive integration structure form a single conductive band around the outer surface of said energy conditioner. The same alternative applies to FIGS. 28, 30, and 32.

FIG. 27 shows stack 27A including plates 2500A and 2700B. Plate 2700B differs from plate 2500B in that the tabs G1T1 and G1T2 of layer G1 are in the LS and RS as opposed to the US and LLS.

FIG. 28 schematically shows an energy conditioner defined by one arrangement of (1) stack 27A and (2) external structure 3A of FIG. 3A. Tabs A1T1 and B1T1 contact the internal surface of conductive band C3, tabs A1T2 and B1T2 contact the internal surface of conductive band C1, tab G1T1 contacts the internal surface of conductive band C2, and tab G1T2 contacts the internal surface of conductive band C4. In this energy conditioner, the A and B master electrodes are conductively tied together at the edges of the tabs by conductive bands C1, C3.

FIGS. 29-32 are views of energy conditioners including conductive layers on three planes and various external structures.

FIG. 29 shows stack 29A including plates 2500A and 2500B. Stack 29A also includes another plate 2500C (not shown) having the same layered pattern as plate 2500A and on an opposite side of plate 2500A relative to plate 2500B. Plate 2500C has elements A2T1, A2T2, B2T1, B2T2, A2M, and B2M aligned with corresponding elements of plate 2500A. Plate 2500C has conductive layers A2 and B2 having tabs aligned with corresponding tabs of plate 2500A, including tab A2T1, A2T2, B2T1, and B2T2. In addition, plate 2500C has A1M and B1M as shown in FIG. 25.

Alternatively, for FIG. 29, and stack 29A, plate 2500C may be replaced by a plate having a conductive pattern that is a mirror image of the conductive pattern on plate 2500A, the mirror defined by a vertical line passing through the center of conductive plate 2500A. In this alternative, conductive tabs A1T1 and A2T2, for example, are still vertically aligned and conductively connected by contacts to the inner surface of conductive band C1. However, in this alternative, A1M has a substantial overlap with B2M, and A2M has a substantial overlap with B1M.

FIG. 30 schematically shows an energy conditioner defined by one arrangement of (1) stack 29A and (2) external structure 3A of FIG. 3A. In this structure, tabs for conductive layers of the same master electrode are aligned in the stack and contact conductive band structure. For example, tabs A1T1 and A2T1 are aligned and contact the internal surface of conductive band C1. In an alternative to stack 29A, discussed above, A1M has a substantial overlap with B2M, and A2M has a substantial overlap with B1M. As with other embodiments, additional alternatives stacks include a repeating sequences of the three plates of layers of stack 29A, and irregular sequences of 2500A, 2500B, and 2500C, and the alternative to 2500C noted above.

FIG. 31 shows stack 31A including plates 2500A and 2500B. Stack 31A also includes a second plate 2500C having the same layered pattern as plate 2500A and on an opposite side of plate 2500A relative to plate 2500B. Plate 2500C has conductive layers A2 and B2 having tabs aligned with corresponding tabs of plate 2500A, including tab A2T1, A2T2, B2T1, and B2T2.

FIG. 32 schematically shows an energy conditioner defined by one arrangement of (1) stack 31A and (2) external structure 3A of FIG. 3A. In this structure, tabs for conductive layers of the same master electrode are aligned in the stack and contact conductive band structure. For example, tabs A1T1 and A2T1 are aligned and contact the internal surface of conductive band C1.

Alternatively, for FIG. 31, plate 2500C may be replaced by a plate having a conductive pattern that is a mirror image of the conductive pattern on plate 2500A, the mirror defined by a vertical line passing through the center of conductive plate 2500A. In this alternative, conductive tabs A1T1 and A2T2, for example, are still vertically aligned and conductively connected by contacts to the inner surface of conductive band C1. As with other embodiments, additional alternatives stacks include a repeating sequences of the three plates of layers of stack 29A, and irregular sequences of 2500A, 2500B, and 2500C, and the alternative to 2500C noted above.

FIG. 33 shows stack 33A including a sequence of plates 3300A, 3300B, 3300C, 3300B, 3300A, 3300B, 3300C.

Plates 3300A each have an upper surface that consists of a surface of conductive layer A1 and exposed dielectric surface D. Conductive layer A1 consists of tabs A1T1, A1T2, and main body portion AMB. Conductive layer A1 is part of an A master electrode. Tab A1T1 extends to the US near the LS. Tab A1T2 extends to the LLS near the LS. AMB extends from tabs A1T1 and A1T2 towards the LS. Plates 3300B each have an upper surface that consists of a surface of conductive layer G1 and exposed dielectric surface D. Conductive layer G1 consists of tabs G1T1, G1T2, and main body portion GMB. Tab G1T1 extends to the middle of the LS. Tab G1T2 extends to the middle of the RS.

Plates 3300C each have an upper surface that consists of a surface of conductive layer B1 and exposed dielectric surface D. Conductive layer B1 consists of tabs B1T1, B1T2, and main body portion BMB. Conductive layer B1 is part of a B master electrode. Tab B1T1 extends to the US near the LS. Tab A1T2 extends to the LLS near the LS. AMB extends from both tabs A1T1 and A1T2 towards the center.

Stack 33A also shows a dielectric plate having no conductive layers thereon at the top of the stack. The dielectric cover represents the condition that the conductive layers not be shorted to external conductive material, as might happen if they were otherwise uncovered.

Alternatives to stack 33A include one or more repetitions of the sequence of plates 3300A, 3300B, 3300C, 3300B, 3300A, 3300B, 3300C, and one or more repetitions of the sequence of plates 3300A, 3300B, 3300C added to the top or the bottom of the sequence of plates 3300A, 3300B, 3300C, 3300B, 3300A, 3300B, 3300C.

Stack 33A may be assembled in a variety of external structures to provide various connections. In one assembly of stack 33A and external structure 31 of FIG. 31 results in tabs A1T2 of the A1 conductive layers in contact with the internal surface of band C4, tabs A1T1 in contact with the internal surface of band C2, tabs B1T2 in contact with the internal surface of band C6, tabs B1T1 in contact with the internal surface of band C5, tabs G1T1 in contact with the internal surface of the LS of band C1, and tabs G1T2 in contact with the internal surface of the RS of band C3.

In alternatives assemblies, stack 33A is assembled with either external structure 3A or 3G wherein the tabs of the G conductive layer contact internal surfaces of bands C2 and C4. In these alternatives, band C1 contacts to tabs at opposite ends of contact A conductive layer thereby forming two parallel conductive paths from tab A1T1 to tab A1T2; one directly between the tabs and the other through the connecting structure of band C1. Similarly, two parallel conductive paths are formed from B tabs of the same B layer by band C3.

The foregoing describe embodiments and alternatives within the scope of the novel concepts disclosed herein. The following claims define the scope of protection sought.

Claims

1. A method for making an energy conditioning structure with stacked, overlapping conductive layers, said method comprising: providing a plurality of dielectric layers;providing a plurality of conductive material layers;placing a first conductive material layer of said plurality of conductive material layers upon a first dielectric layer of said plurality of dielectric layers;positioning a first electrode of said first conductive material layer in a first position upon said first dielectric layer such that a first electrode main body portion of said first conductive material layer does not extend to any one of a left side surface edge, a right side surface edge, an upper side surface edge, and a lower side surface edge of a first dielectric surface of said first dielectric layer and also that a first electrode tab of said first conductive material layer extends to at least a portion of said left side surface edge of said first dielectric layer but does not extend to said right side surface edge of said first dielectric layer;positioning a second electrode of said first conductive material layer in a second position upon said first dielectric layer such that a second electrode main body portion of said first conductive material layer does not extend to any one of said left side surface edge, said right side surface edge, said upper side surface edge, and said lower side surface edge of said first dielectric surface of said first dielectric layer and also that a second electrode tab of said first conductive material layer extends to at least a portion of said right side surface edge of said first dielectric layer but does not extend to said left side surface edge of said first dielectric layer;electrically isolating said first electrode of said first conductive material layer from said second electrode of said first conductive material layer;placing a second conductive material layer of said plurality of conductive material layers upon a second dielectric layer of said plurality of dielectric layers;positioning upon said second dielectric layer a single electrode that is contained in said second conductive material layer and contains at least two electrode tabs;placing a third conductive material layer of said plurality of conductive material layers upon a third dielectric layer of said plurality of dielectric layers;positioning a first electrode of said third conductive material layer in a first position upon said third dielectric layers such that a first electrode main body portion of said third conductive material layer does not extend to any one of a left side surface edge, a right side surface edge, a upper side surface edge, and a lower side surface edge of a first dielectric surface of said third dielectric layer and also that a first electrode tab of said third conductive material layer extends to at least a portion of said left side surface edge of said third dielectric layer but does not extend to said right side surface edge of said third dielectric layer;positioning a second electrode of said third conductive material layer in a second position upon said third dielectric layer such that a second electrode main body portion of said third conductive material layer does not extend to any one of said left side surface edge, said right side surface edge, said upper side surface edge, and said lower side surface edge of said first dielectric surface of said third dielectric layer and also that a second electrode tab of said third conductive material layers extends to at least a portion of said right side surface edge of said third dielectric layer but does not extend to said left side surface edge of said third dielectric layer;positioning a second electrode of said third conductive material layer in a second position upon said dielectric layer;electrically isolating said first electrode of said third conductive material layer from said second electrode of said third conductive material layer;electrically isolating said single electrode of said second conductive material layer from said first and second electrodes of said first conductive material layer;electrically isolating said single electrode of said second conductive material layer from said first and second electrodes of said third conductive material layer;stacking said second dielectric layer upon said first conductive material layer of said plurality of conductive material layers and a portion of said first surface of said first dielectric layer;stacking said third dielectric layer upon said second conductive material layer of said plurality of conductive material layers and a portion of said first surface of said second dielectric layer;stacking a fourth dielectric layer of said plurality of dielectric layers upon said third conductive material layer of said plurality of conductive material layers and a portion of said first surface of said third dielectric layer;stacking said second dielectric layer upon said first dielectric layer, stacking said third dielectric layer upon said second dielectric layer, and stacking said fourth dielectric layer upon said third dielectric layer;positioning a main body portion of said second electrode to completely shield said first electrode main body portion and said second electrode main body portion of said first conductive material layer from said first electrode main body potion and said second electrode main body portion of said third conductive material layer;positioning said first electrode tab of said first conductive material layer to overlap said first electrode tab of said third conductive material layer;positioning said second electrode tab of said first conductive material layer to overlap said second electrode tab of said third conductive material layer;conductively coupling said first electrode tab of said first conductive material layer to said first electrode tab of said third conductive material layer;conductively coupling said second electrode tab of said first conductive material layer to said second electrode tab of said third conductive material layer;aligning said first electrode main body portion of said first conductive material layer to overlap said second electrode main body portion of said third conductive material layer; andaligning said second electrode main body portion of said first conductive material layer to overlap said first electrode main body portion of said third conductive material layer.