Patent Application
20250163609
The present invention relates to a method for producing a heteroepitaxial film.
Most devices formed on silicon substrates, such as advanced CMOS (Complementary Metal Oxide Silicon) or IGBT (Insulated Gate Bipolar Transistor), are not used at an initial silicon substrate thickness intact but are used in a thin filmed form by methods such as grinding in most cases. This is because thick silicon substrates make the substrates resistive and thus problematic. On the other hand, the thin silicon substrates from the beginning may warp during a process, making the substrates impossible to pass through a device process, thus thickness is required. Meanwhile, in addition to conventional miniaturization, recent devices have employed integration by methods such as Chip on Wafer, in which cut-out devices are attached to wafers prewired with metal wiring. In this case, the devices to be cut out are also thinned, and most silicon substrates are removed.
In addition, materials other than silicon have been actively used in devices, contributing to higher performance. Among them, SiC has a wider bandgap of 2.2 to 3.3 eV, compared with a bandgap of Si of 1.1 eV, which gives a high dielectric breakdown strength and high thermal conductivity, making it a promising material as a semiconductor material for various semiconductor devices such as power devices and high-frequency devices.
Considering these factors, for example, Patent Documents 1, 2, and 3 propose techniques in which ion implantation, such as hydrogen, is applied to SiC or silicon, and then the substrate is delaminated from this implantation layer. With these methods, a thin-film side can be reused as a device, and a thick-film side can be reused as a substrate once more (although surface polishing is required) after delaminating. Thus, these methods have great merits. However, these methods perform delaminating by creating a frangible layer with ion implantation such as hydrogen, thus an ion implantation apparatus is needed (this is particularly expensive for a large diameter substrate), and timing to form the frangible layer is extremely difficult (when the frangible layer is formed at an early stage of the process, it is highly likely that a crack is generated because of a thermal step during the process. On the other hand, when the layer is formed in the latter stage of the process, the device that has been formed is destroyed by ion implantation). Therefore, a practical application still has a hurdle.
The present invention has been made in view of solving the above-described problem and efficiently obtaining a heteroepitaxial film in a thin film shape with less damage to a device and less material loss.
To achieve the object described above, the present invention provides a method for producing a heteroepitaxial film, including a step of heteroepitaxially growing a 3C—SiC single crystal film on a single crystal silicon substrate and then delaminating the 3C—SiC single crystal film from the single crystal silicon substrate, the method comprising: with using a reduced-pressure CVD apparatus,
In this way, by removing the native oxide film on the surface of the single crystal silicon substrate in the first step, the nucleation of SiC becomes possible in the second step.
In addition, by combining pressure and temperature conditions that facilitate the nucleation of SiC in the second step and pressure and temperature conditions that facilitate the growth of the SiC single crystal in the third step, it is possible to efficiently produce the heteroepitaxial wafer with 3C—SiC single crystal film having the excellent quality.
Moreover, making the pressure 1333 Pa (10 Torr) or lower can prevent reactions of secondary or higher orders, such as a reaction of reactive active species with a raw material gas in the gas phase, thus ensuring the heteroepitaxial growth. Thereby, polycrystallization of 3C—SiC can be prevented. Furthermore, the vacancy can be formed in a silicon layer (single crystal silicon substrate) (hereinafter, also referred to as an interface between 3C—SiC and silicon) directly under the 3C—SiC single crystal film while growing the 3C—SiC single crystal film. The presence of the vacancy not only relaxes a lattice mismatch between 3C—SiC and silicon but also the stress-relaxes of an entire epitaxial layer, thus enabling more reliable formation of the 3C—SiC single crystal film without crystal defects even for a thick 3C—SiC single crystal film.
As described above, by combining pressure and temperature conditions, which facilitate the nucleation of SiC, and pressure and temperature conditions, which facilitate a growth of the SiC single crystal and form a vacancy at an interface between SiC and silicon, a heteroepitaxial wafer having the 3C—SiC single crystal film can be efficiently obtained. Moreover, in the fourth step, separating and delaminating along the vacancy at the interface between 3C—SiC and silicon, a heteroepitaxial film, including an objective 3C—SiC single crystal film, can be efficiently obtained.
Furthermore, because of the delamination at the interface between 3C—SiC and silicon, the separation can be performed with a small loss of a single crystal silicon substrate. In other words, a thicker single crystal silicon substrate can be obtained after separation, which is effective in terms of reuse.
For example, even in the case of delaminating after forming the device on the 3C—SiC single crystal film, damage to the device is small.
In this case, the source gas can be monomethylsilane or trimethylsilane.
Such a raw material gas can supply both Si and C by a single gas, thus, a step of nucleation, which is called carbonization before the 3C—SiC single crystal film growth, as in the conventional method, is also unnecessary, in which a carbon atom is attached to the surface of the single crystal silicon substrate by the gas containing carbon source precursor. Then, forming the 3C—SiC single crystal film is enabled on a very simple condition.
Moreover, compared with a conventional method, in which the carbon atom is first attached on the surface of the single crystal silicon substrate by a gas containing carbon source precursor for nucleation and then the 3C—SiC single crystal film is formed using the gas containing carbon source precursor and a gas containing silicon source precursor; the reactive active species in the gas phase are more controllable, and the heteroepitaxial growth is more reliable, thereby forming the thick 3C—SiC single crystal film much easier without stopping the growth of a 3C—SiC single crystal.
Meanwhile, the first step can be performed on condition of a temperature of 1000° C. or higher and 1200° C. or lower.
By using such a temperature condition, the native oxide film on the surface of the single crystal silicon substrate can be removed more efficiently, and the 3C—SiC single crystal film can be formed more reliably. Moreover, the generation of slip dislocations can be prevented.
In addition, the third step can be performed on condition of pressure of 133 Pa or lower.
In this way, by making the pressure 133 Pa (1 Torr) or lower in the third step, the vacancy can be formed more reliably at the interface between 3C—SiC and silicon while growing 3C—SiC single crystal film and the 3C—SiC single crystal film (heteroepitaxial film) can be delaminated more reliably in the fourth step.
Meanwhile, the third step can be performed with one or more of pressure and temperature higher than the condition of the second step.
The third step can be performed on the condition identical to the condition of the second step, but when the condition is described above, a growth rate of the 3C—SiC single crystal film can be much faster in the third step. Thus, the formation can be performed efficiently even when forming the thick 3C—SiC single crystal film.
In this case, the third step can be performed on condition of a temperature of 1000° C. or higher and lower than 1200° C.
On this growth condition, the heteroepitaxial growth can be controlled by transport of the supply gas and is not restricted by such as limitation of the plane orientation of the single crystal silicon substrate to make the lattice mismatch between silicon and SiC smaller, which is generated in another conventional method. There is no need to form a frangible layer such as hydrogen by ion implantation, and the 3C—SiC single crystal film can be grown more reliably. Furthermore, the 3C—SiC single crystal film can be more easily formed on a single silicon substrate, for example, with a large diameter of such as 300 mm.
Meanwhile, one or more of the pressure and temperature can be raised higher during the third step.
With this method, it is possible to make the conditions of the pressure to, for example, 133 Pa (1 Torr) or lower in an initial stage of the third step and then raise the pressure to accelerate the film-formation rate. Similarly, the temperature can be raised to a high temperature to accelerate the film-formation rate from the middle of the stage.
In this case, the second step and the third step are performed on condition of gradually raising a temperature from a range from 300° C. or higher to 950° C. or lower to the range from 1000° C. or higher to lower than 1200° C.,
In this way, the heteroepitaxial growth can be controlled by transport of the supply gas and cannot be restricted by the plane orientation of the single crystal silicon substrate, and containing hydrogen is unnecessary. Moreover, the 3C—SiC single crystal film can be more easily formed on a single crystal silicon substrate having a large diameter.
Besides, the temperature rise can be at a rate of temperature rise of 0.5° C./sec or faster and 2° C./sec or slower.
With such a rate of temperature rise, controlling the temperature can be performed more reliably. In addition, uniform nucleation of SiC can be performed, and the generation of defects during heteroepitaxial growth can be effectively prevented.
Moreover, after the third step and before the fourth step, a GaN layer can be formed on a surface of the formed 3C—SiC single crystal film by further growing GaN thereon, or after the third step and before the fourth step, a Si layer can be formed on a surface of the formed 3C—SiC single crystal film by further growing Si thereon.
The 3C—SiC single crystal film grown as described above has a flat surface. Thus, the GaN layer or the Si layer can be further heteroepitaxial grown on the surface of the 3C—SiC single crystal film.
Meanwhile, after the third step, a protective film can be formed on the formed 3C—SiC single crystal film, and then the fourth step can be performed. Otherwise, after the third step, a device can be formed and a protective film can be formed on the formed 3C—SiC single crystal film, and then the fourth step can be performed. Alternatively, after the third step, the device can be formed on the formed 3C—SiC single crystal film, and the protective film can be formed after the device is cut out along a scribe line of the device, and then the fourth step can be performed.
In this way, the 3C—SiC single crystal film can be delaminated intact, or can be delaminated after the formation of the device.
According to the inventive method for producing the heteroepitaxial film, heteroepitaxial growth of the 3C—SiC single crystal film is performed efficiently on the single crystal silicon substrate so as to generate the vacancy in the silicon substrate (the interface between 3C—SiC and silicon) while maintaining excellent 3C—SiC single crystalline, and the heteroepitaxial film in a thin film shape can be efficiently obtained by delaminating the 3C—SiC single crystal film from the silicon substrate using this vacancy. It is also extremely effective in terms of damage to the device and material loss. Furthermore, by using SiC as an underlayer, such heteroepitaxial film can improve device isolation due to an insulating property with characteristics of a wide bandgap and cooling efficiency due to high thermal conductivity.
Hereinafter, embodiments of the present invention will be described with reference to the drawings. However, the present invention is not limited thereto.
As described above, a method of efficiently obtaining a heteroepitaxial film (a 3C—SiC single crystal film) has been required. The present inventors, therefore, have earnestly studied and found out that; with using a reduced-pressure CVD apparatus, in addition to hydrogen baking for removing a native oxide film on a surface of a single crystal silicon substrate (First Step), while supplying source gas (containing carbon and silicon), by combining a predetermined condition with respect to pressure and temperature (pressure of 1333 Pa or lower and a temperature of 300° C. or higher and 950° C. or lower) that facilitates nucleation of SiC (Second Step) and a predetermined condition (pressure of 1333 Pa or lower and a temperature of 800° C. or higher and lower than 1200° C.) to facilitate a growth of a SiC single crystal and form a vacancy at an interface between 3C—SiC and silicon (Third Step), then the 3C—SiC single crystal film with excellent quality can be efficiently formed; and even more, when the 3C—SiC single crystal film is separated and delaminated from the single crystal silicon substrate along the vacancy (Fourth Step); the heteroepitaxial film can be efficiently obtained. This finding has led to the completion of the present invention.
Hereinafter, each step is described, referring to various specific examples.
To begin with, a single crystal silicon substrate is placed in a reduced-pressure CVD apparatus (hereinafter, also referred to as an RP-CVD apparatus), a hydrogen gas is introduced, and then a native oxide film on the surface is removed by H2 anneal. When an oxide film remains, the nucleation of SiC on the single crystal silicon substrate becomes impossible. H2 anneal, in this case, is preferably on condition of, for example, a temperature of 1000° C. or higher and 1200° C. or lower. Making the temperature 1000° C. or higher can prevent long processing time to prevent residual native oxide film, thus being efficient. Meanwhile, making the temperature 1200° C. or lower can effectively prevent a generation of a slip dislocation due to high temperature. However, the pressure or time of H2 anneal at the time has no particular restriction as long as the native oxide film can be removed.
In the example shown in
Then, the single crystal silicon substrate is set to a predetermined pressure and temperature, and a source gas containing carbon and silicon is introduced as a raw material gas for SiC into the RP-CVD apparatus, and then the nucleation of SiC is performed. Monomethylsilane or trimethylsilane (TMS) can be introduced as the source gas, for example. It is simpler and easier to control than using a plurality of types of gases, and more reliable formation of the 3C—SiC single crystal film is possible. Further, since C has smaller atoms and vaporizes more easily than Si, trimethylsilane is easier for a condition setting regarding raw material efficiency.
Such introduction of the source gas is performed in this second step and the following third step.
Moreover, this nucleation of SiC can be performed on the surface of the single crystal silicon substrate when the pressure is 1333 Pa (10 Torr) or lower, and the temperature is 300° C. or higher and 950° C. or lower.
In the nucleation step of SiC, when a temperature condition is higher than 950° C., the reaction between the single crystal silicon substrate and the raw material gas proceeds, and the nucleation of SiC on the surface of the single crystal silicon substrate cannot be formed. On the other hand, when a temperature is lower than 300° C., the temperature is too low, thereby making efficient nucleation of SiC impossible.
Additionally, considering the third step described next at this point, if the temperature is lower than 800° C. during the third step, the heteroepitaxial growth of SiC does not proceed. Thereupon, from the time of the second step, for example, the temperature of nucleation of SiC can be set preferably between 800° C. or higher and 950° C. and lower, more preferably between 850° C. or higher and 900° C. or lower. By making the temperature of the second step 800° C. or higher and 950° C. or lower, the temperature range for the nucleation step of SiC (Second Step) and the following third step, which is the formation of the 3C—SiC single crystal film, can be overlapped, in particular, these second and third steps can be performed under the same temperature condition.
Moreover, keeping the pressure at 1333 Pa (10 Torr) or lower is efficient because it prevents secondary or higher-order reactions, such as the reaction of the reactive active species with the raw material gas in the gas phase. The lower pressure limit is not particularly limited but can be 13 Pa (0.1 Torr), for example. Moreover, the pressure, as in the temperature, can be the same conditions in the second and third steps.
In the example shown in
In addition, the formation step of the 3C—SiC single crystal film, which is the third step, is performed on condition of the pressure of 1333 Pa (10 Torr) or lower and the temperature of 800° C. or higher and lower than 1200° C. With such conditions, the SiC single crystal can be efficiently grown, thereby forming the 3C—SiC single crystal film.
Moreover, in the present invention, the pressure in the third step is made to be 1333 Pa (10 Torr) or lower, thus polycrystallization of the formed 3C—SiC can be prevented, and the secondary or higher-order reactions can be suppressed in the vapor phase as described above, and the 3C—SiC single crystal film can be formed reliably and efficiently. Simultaneously, a vacancy is formed directly under the 3C—SiC single crystal film, thereby obtaining an effect of stress-relaxing of an entire heteroepitaxial layer. In addition, the pressure can preferably be 133 Pa (1 Torr) or lower to form the above vacancy more reliably and to obtain the above stress-relaxing effect more reliably. The lower pressure limit is not limited but can be 13 Pa (0.1 Torr), for example.
Furthermore, concerning the temperature, the SiC single crystal growth does not progress at lower than 800° C. as described above, and the slip dislocation may be generated at 1200° C. or higher. Consequently, the temperature is defined between 800° C. or higher and lower than 1200° C. as described above.
In the example shown in
Since the film thickness at this time depends on the pressure and temperature, the formation time can be determined appropriately based on the pressure and temperature conditions determined to achieve the desired film thickness.
In this case, the film thickness of the 3C—SiC single crystal film can be formed within a thin film of about 2 nm to a thick film of several μm, for example.
In addition, a layered growth in two-dimensional growth mode shown in
When GaN is grown on the 3C—SiC single crystal film grown in such a way, a heteroepitaxial wafer having a GaN layer with excellent quality can be obtained.
In this event, GaN growth is performed for film-formation by MOCVD using organometallic materials such as trimethylgallium and trimethylammonium to grow GaN of about 3 μm.
Furthermore, by growing Si on the 3C—SiC single crystal film grown in this way, it is possible to obtain a substrate with a high-quality Si epitaxial layer. With this structure, in the case of power devices such as IGBTs, for example, the 3C—SiC single crystal film serves as a breakdown-voltage-retaining layer in the IGBT. The dielectric breakdown electric field strength of silicon is 0.3 MV/cm, while the dielectric breakdown electric field strength of 3C—SiC is 3 MV/cm; thus, that of 3C—SiC is ten times larger. That is, the same performance can be obtained with one-tenth of the thickness of a breakdown-voltage-retaining layer of a conventional silicon IGBT. Needless to say, it is not necessary to form the breakdown-voltage-retaining layer only with the 3C—SiC single crystal film, and a combination of SiC and Si is also sufficient. SiC is grown to a predetermined thickness in this way, and then the Si epitaxial layer is grown thereon. In conventional SiC devices, a gate insulator film is formed using SiC, which has problems with reliability. However, silicon is grown in this structure, and then a gate insulator film is grown using this silicon, thus the same gate reliability as the conventional silicon IGBT can be ensured. Moreover, a thickness of the silicon layer in this case can be determined discretionary as long as the layer is thicker than the required gate structure.
Then, as a fourth step, a heteroepitaxial film is produced by separating and then delaminating a formed 3C—SiC single crystal film from a single crystal silicon substrate along a vacancy.
In addition, as shown in the middle of
Then, as shown on the lower side of
Moreover,
In addition, scribe can be performed instead of dicing.
As still another example, after forming the device on the 3C—SiC single crystal film, a protective film is formed, and then the fourth step can be performed. Moreover, the protective film is formed after forming the device on the 3C—SiC single crystal film and cutting out of the device along a scribe line of the device, and then the fourth step may be performed. Furthermore, the fourth step can be performed after adhesion with an adhesive to a holding stage (for example, various substrates) with or without the protective film. Thus, depending on a desired form of the heteroepitaxial film, the necessary treatment can be performed between the third step and the fourth step as appropriate.
With the inventive method for producing the heteroepitaxial film, the heteroepitaxial film can be efficiently formed with the vacancy, and even when the device has been already formed, damage to that device is minimized due to separation and delamination along the vacancy region, thus the heteroepitaxial film can be obtained efficiently and easily. Moreover, the separation can be performed at the interface between the 3C—SiC single crystal film and the single crystal silicon substrate, thus a loss of the single crystal silicon substrate obtained after delamination can be made extremely small and then the substrate can be reused for the following production of the heteroepitaxial film.
To begin with, a single crystal silicon substrate is placed in an RP-CVD apparatus, and a native oxide film on the surface is removed by H2 anneal. This can be done as in the first embodiment.
Then, as a nucleation step of SiC, the single crystal silicon substrate is set at a temperature of 300° C. or higher and 950° C. or lower, preferably 800° C. or higher and 950° C. or lower, more preferably 850° C. or higher and 900° C. or lower, and then monomethylsilane or trimethylsilane is introduced as a raw material gas for SiC. The time for nucleation can be five minutes, for example.
Then, as a formation step of the 3C—SiC single crystal film, the temperature of the single crystal silicon substrate is raised to 1000° C. or higher and lower than 1200° C., and then monomethylsilane or trimethylsilane is introduced as a raw material gas of SiC.
The third step, which is the formation step of this 3C—SiC single crystal film, raises one or more of the pressure and the temperature higher than the second step, which is the nucleation step of SiC, thereby facilitating growth at a high rate (change between steps). Moreover, raising one or more of the pressure and the temperature during the third step can facilitate growth at a high rate (change within a step). Only one of the above change between steps or change within the step can be made, or both can be made.
Then, the temperature in the third step can be made to 1000° C. or higher and lower than 1200° C. In this case, heteroepitaxial growth can be controlled by transport of a supplied gas. A plane orientation of the single crystal silicon substrate is not subjected to restrictions and can easily be made to accommodate a substrate having a large diameter, such as 300 mm.
In addition, the growth in
In particular, the pressure is set to 1333 Pa (10 Torr) or lower, preferably 133 Pa (1 Torr) or lower, in the nucleation step of SiC and the initial stage of the formation step of 3C—SiC single crystal film to form a vacancy directly under the 3C—SiC single crystal film. Then, the pressure is changed to a higher condition than the initial stage within a range of 1333 Pa (10 Torr) or lower, thereby achieving both stress-relaxing of the entire heteroepitaxial layer and efficient formation of the 3C—SiC single crystal film.
Then, by growing GaN or Si on the 3C—SiC single crystal film grown in this way, the substrate having a high-quality GaN epitaxial layer or Si epitaxial layer can be obtained.
The formed 3C—SiC single crystal film is separated and delaminated from the single crystal silicon substrate along the vacancy, thereby producing the heteroepitaxial film. This can be performed in the same manner as in the first embodiment.
To begin with, a single crystal silicon substrate is placed in an RP-CVD apparatus, and a native oxide film on a surface of the substrate is removed by H2 anneal as on a similar condition in the first embodiment.
Then, in order to perform the nucleation of SiC and subsequent formation of a 3C—SiC single crystal film in succession on the surface of the single crystal silicon substrate, a temperature is gradually raised from a range of 300° C. or higher and 950° C. or lower to a range of 1000° C. or higher and lower than 1200° C., while introducing monomethylsilane or trimethylsilane as a raw material gas. In this way, the second step and third step can be performed in succession while raising the temperature.
A rate of temperature rise is preferably 0.5° C./sec or higher and 2° C./sec or lower, for example. The rate of temperature rise at this level is not too fast rate of temperature rise, thus, the deviation between the set temperature and the actual temperature can be effectively prevented, and the temperature control can be properly performed. Moreover, the rate of temperature rise is not too slow; thus, it can prevent facilitating a generation of ununiform nucleation due to a long transit time of a temperature zone for SiC nucleation or facilitating a generation of a defect during heteroepitaxial growth.
In this case, the temperature may be raised to a predetermined temperature within a range of 1000° C. or higher and lower than 1200° C., then the growth may be stopped there, or the growth can be continued until a predetermined film thickness is achieved while maintaining at that temperature. Moreover, the growth may be stopped when the predetermined film thickness is achieved along with the temperature rise, even if the temperature has reached 1000° C. or higher but has not reached the predetermined temperature described above. A gradual acceleration of the forming rate of the film is enabled by growth with a continuously changing growth mode (changing from nucleation to two-dimensional growth) by growing with varying temperatures.
In
In particular, the pressure is set to 1333 Pa (10 Torr) or lower, preferably 133 Pa (1 Torr) or lower, in the nucleation step of SiC and the initial stage of the formation step of 3C—SiC single crystal film to form a vacancy directly under the 3C—SiC single crystal film. Then, the pressure is changed to a higher condition than the initial stage within a range of 1333 Pa (10 Torr) or lower, thereby achieving both stress-relaxing of the entire heteroepitaxial layer and efficient formation of the 3C—SiC single crystal film.
Then, by growing GaN or Si on the 3C—SiC single crystal film grown in this way, the substrate having an excellent quality GaN epitaxial layer or Si epitaxial layer can be obtained.
The formed 3C—SiC single crystal film is separated and delaminated from the single crystal silicon substrate along the vacancy, thereby producing the heteroepitaxial film. This can be performed in the same manner as in the first embodiment.
Hereinafter, the present invention will be specifically described with reference to Examples and Comparative Examples of the present invention. However, the present invention is not limited thereto.
High-resistivity single crystal silicon substrates having a diameter of 300 mm, plane orientation (111), and boron-doped were provided, and wafers were placed on a susceptor in a reactor of an RP-CVD apparatus, and then H2 anneal was performed at 1080° C. for one minute (First Step).
Then, a trimethylsilane gas was introduced at a growth temperature of 900° C. and a growth pressure of 133 Pa (1 Torr), and a nucleation step of SiC (Second Step) and 3C—SiC single crystal film growth (Third Step) was performed. As a result of five minutes of growth, the film thickness was 13 nm.
Subsequently, when an XRD (X-ray diffraction) spectrum was confirmed in in-plane arrangement, a peak of 3C—SiC (220) parallel to Si (220) was successfully confirmed, as shown in a graph of XRD analysis results in
Moreover,
Subsequently, a surface of a protective film on the 3C—SiC single crystal film was coated with an adhesive and bonded to a quartz substrate. Then, with this substrate in a state of being chucked, peeling off was performed, then separation and delamination of the 3C—SiC single crystal film (heteroepitaxial film) was achieved along the vacancy formed portion at an interface between 3C—SiC and silicon (Fourth Step).
As still another delamination method, dicing with the size of 1 mm×1 mm was performed from the 3C—SiC single crystal film side (the dicing depth was slightly deeper than the thickness of the 3C—SiC single crystal film) to the substrate in which the 3C—SiC single crystal film was grown, then a surface thereof was adsorbed by a clipper and then the 3C—SiC single crystal film was successfully delaminated as a chip at the vacancy formed portion.
High-resistivity single crystal silicon substrate having a diameter of 300 mm, plane orientation (111), and boron-doped were provided, and wafers were placed on a susceptor in a reactor of an RP-CVD apparatus, and then H2 anneal was performed at 1080° C. for one minute (First Step).
Subsequently, a trimethylsilane gas was introduced at a growth temperature of 900° C. for five minutes as a second step (Nucleation Step of SiC Nucleus).
Then, the growth temperature was raised to 1190° C. as a third step (Formation Step of 3C—SiC single crystal film), and a trimethylsilane gas was introduced to grow a 3C—SiC single crystal film. The growth pressure here was uniformly 133 Pa (1 Torr). As a result of growth for one minute, film thickness was about 30 nm.
After the formation, when an XRD spectrum was confirmed in an in-plane arrangement, a peak of 3C—SiC (220) parallel to Si (220) was successfully confirmed as in Example 1, and the growth of a single crystal 3C—SiC film was confirmed.
Moreover,
Subsequently, when the fourth step was performed as in Example 1 using an adhesive and a quartz substrate, then delamination of the 3C—SiC single crystal film was achieved along a vacancy formed portion at an interface between 3C—SiC and silicon.
When still another delamination method was performed as in Example 1, the 3C—SiC single crystal film was successfully delaminated as a chip at the vacancy formed portion.
A 3C—SiC single crystal film was formed on the same condition as in Example 1, except that a growth pressure was 1333 Pa (10 Torr) and a growth temperature was 950° C. in the second step and the third step. As a result, a film thickness was about 20 nm.
Subsequently, when an XRD spectrum was confirmed in an in-plane arrangement, a peak of 3C—SiC (220) parallel to Si (220) was successfully confirmed, and the growth of a single crystal 3C—SiC film was confirmed. Moreover, a formation of a vacancy directly under the 3C—SiC single crystal film was confirmed.
Furthermore, when the fourth step was performed as in Example 1 using an adhesive and a quartz substrate, then delamination of the 3C—SiC single crystal film was achieved along a vacancy formed portion at an interface between 3C—SiC and silicon.
A 3C—SiC single crystal film was formed on the same condition as in Example 2, except that a growth temperature was 300° C. and 800° C. in the second step and the third step, respectively. As a result, a film thickness was about 12 nm.
Subsequently, when an XRD spectrum was confirmed in an in-plane arrangement, a peak of 3C—SiC (220) parallel to Si (220) was successfully confirmed, and the growth of a single crystal 3C—SiC film was confirmed. Moreover, a formation of a vacancy directly under the 3C—SiC single crystal film was confirmed.
Furthermore, when the fourth step was performed as in Example 2 using an adhesive and a quartz substrate, then delamination of the 3C—SiC single crystal film was achieved along a vacancy formed portion at an interface between 3C—SiC and silicon.
A 3C—SiC single crystal film was formed on the same condition as in Example 2, except that a growth pressure was 3999 Pa (30 Torr) in the second step and the third step. As a result, a film thickness was about 33 nm.
Subsequently, when an XRD spectrum was confirmed in an in-plane arrangement, a peak of 3C—SiC (220) parallel to Si (220) was successfully confirmed, and the growth of a single crystal 3C—SiC film was confirmed. However, a formation of a vacancy directly under the 3C—SiC single crystal film could not be confirmed.
Furthermore, delamination of the 3C—SiC single crystal film was attempted as in Example 2 using an adhesive and a quartz substrate, but delamination could not be achieved. This is considered to be due to a failure to form the vacancy described above.
A 3C—SiC single crystal film was formed on the same condition as in Example 2, except that a growth temperature was 200° C. or 1000° C. in the second step. As a result, a film thickness was about 2 nm and 4 nm, respectively.
The film thickness formed in such a way was extremely thin compared with Example 2, and the efficiency thereof was significantly inferior. This is considered that the temperature in the second step was too high or too low, thus nucleation of SiC was insufficient, and consequently, little heteroepitaxial growth was made in the third step.
A 3C—SiC single crystal film was formed on the same condition as in Example 2, except that a growth temperature was 700° C. or 1250° C. in the third step. As a result, a film thickness was about 7 nm and 50 nm, respectively.
Thus, in the case of 700° C., the film thickness formed was extremely thin compared with Example 2, and the efficiency thereof was significantly inferior. Moreover, a slip dislocation was generated in the case of 1250° C.
It should be noted that the present invention is not limited to the above-described embodiments. The embodiments are just examples, and any examples that have substantially the same feature and demonstrate the same functions and effects as those in the technical concept disclosed in claims of the present invention are included in the technical scope of the present invention.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2021-164648 | Oct 2021 | JP | national |
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/JP2022/032016 | 8/25/2022 | WO |
