Patent Application
20250216600
Electrical signaling and processing are one technique for signal transmission and processing. Optical signaling and processing have been used in increasingly more applications in recent years, particularly due to the use of optical fiber-related applications for signal transmission.
Optical signaling and processing are typically combined with electrical signaling and processing to provide full-fledged applications. For example, optical fibers may be used for long-range signal transmission, and electrical signals may be used for short-range signal transmission as well as processing and controlling. Accordingly, devices integrating long-range optical components and short-range electrical components are formed for the conversion between optical signals and electrical signals, as well as the processing of optical signals and electrical signals. Packages thus may include both optical (photonic) dies including optical devices and electronic dies including electronic devices.
Maintaining alignment between optical components within a semiconductor device is particularly advantageous for efficient and high quality transfer of light energy. However, known methods of fabrication can result in misalignment due to relative motion between components as a result of the fabrication process.
Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.
Embodiments will now be discussed with respect to certain embodiments in which one or more laser dies and one or more compact universal photonic engine (COUPE) dies are embedded in an integrated package. Light from the laser dies is coupled to other optical devices, including the COUPE die. However, the embodiments presented herein are intended to be illustrative and are not intended to limit the embodiments to the precise descriptions as discussed. Rather, the embodiments discussed may be incorporated into a wide variety of implementations, and all such implementations are fully intended to be included within the scope of the embodiments.
With reference now to
In some embodiments the one or more PICs may include optical components such as additional optical waveguides (e.g., ridge waveguides, rib waveguides, buried channel waveguides, diffused waveguides, etc.), couplers (e.g., grating couplers, edge couplers that are a narrowed waveguide with a width of between about 1 nm and about 200 nm, etc.), directional couplers, optical modulators (e.g., Mach-Zehnder silicon-photonic switches, microelectromechanical switches, micro-ring resonators, etc.), amplifiers, multiplexors, demultiplexors, optical-to-electrical converters (e.g., P-N junctions), electrical-to-optical converters, lasers, combinations of these, or the like. However, any suitable optical components may be used.
In some embodiments, the first coupling waveguides 210 may be comprised of silicon nitride. The first coupling waveguides 210 may be multi-layer, multi-line, or trench style waveguides. For example, in the embodiment shown in
In an embodiment the first support substrate 230 may be a support material that is transparent to the wavelength of light that is desired to be used, such as silicon, and may be attached using, e.g., an adhesive (not separately illustrated in
The first support substrate 230 may additionally comprise a coupling lens 240 positioned to facilitate movement from an optical fiber (not illustrated in
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In accordance with some embodiments, as shown in
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In an embodiment, and as illustrated in
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In some embodiments, the dry etching process results in a substantially straight profile. In this context, as shown in
In some embodiments the etching process may be performed in multiple steps and may utilize a plasma dry etch process and/or a reactive ion etch (RIE). For example, a first reactive ion etch using reactive gases such as CF4, CAF8, CHF3, or CH3F may be performed to preferentially etch through the dielectric portions of the first bonding layer 410 and the first active portion 610 of the COUPE dies. In some cases, the depth of the trench formed by the first dry etch may be between 3 μm and 30 μm. A second reactive ion etch may then be performed using gases such as SF6 or NF3 to preferentially etch between 20 μm and 200 μm into the support substrate. The depth of the etch may be controlled by varying the timing of the etching process, among other process parameters. In some embodiments a third etch may be performed where the third etch is a wet etch to cure any surface defects in the COUPE die resulting from the dry etching process.
As shown in
In some embodiments, after the partial etching process, the COUPE die wafer 520 (shown in
In some embodiments, as shown in
By performing a multi-step singulation process as described above, the sidewalls of the first active portion 220 of the singulated COUPE die 110 are smoother than the sawed-through portions of the first support substrate 230. In some embodiments the roughness of the dry etched sidewalls of the first active portion 220 of the singulated COUPE die 110 is less than 10 nm and results in an optical transmission rate at the boundary of the first coupling waveguides 210 of greater than or equal to 99%. In contrast, singulating the COUPE dies 110 using only a saw can result in sidewall roughness greater than 100 nm and optical transmission rates of less than 90%. Accordingly, there is lower optical interference at the boundary of the active portion sidewall, and specifically at the boundary of the first coupling waveguides 210 when transferring optical energy into or out of the COUPE die.
In some embodiments, the second coupling waveguides 1010 may be comprised of silicon nitride. The second coupling waveguides 1010 may be multi-layer, multi-line, or trench style waveguides. For example, in the embodiment shown in
In an embodiment the second support substrate 1030 may be a material, such as silicon, and may be attached using, e.g., an adhesive (not separately illustrated in
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In accordance with some embodiments, as shown in
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In an embodiment, and as illustrated in
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In some embodiments, the dry etching process results in a substantially straight profile. In this context, and as shown in
In some embodiments the etching process may be performed in multiple steps and may utilize a plasma dry etch process and/or a reactive ion etch (RIE). For example, a fourth reactive ion etch using reactive gases such as CF4, C4F8, CHF3, or CH3F may be performed to preferentially etch through the dielectric portions of the second bonding layer 1210 and the second active portion 1250 of the laser dies. In some cases, the depth of the trench formed by the first dry etch may be between 3 μm and 30 μm. A fifth reactive ion etch may then be performed using gases such as SF6 or NF3 to preferentially etch between 20 μm and 200 μm into the second support substrate 1260. The depth of the etch may be controlled by varying the timing of the etching process, among other process parameters. In some embodiments a sixth etch may be performed where the third etch is a wet etch to cure any surface defects in the laser die resulting from the dry etching process.
As shown in
In some embodiments, after the partial etching process, the laser die wafer (not shown) is cleaned and flipped over to complete the multi-step singulation process. As shown in
In some embodiments, as shown in
By performing a multi-step singulation process as described above, the sidewalls of the second active portion 1250 of the singulated laser die 120 are smoother than the sawed-through portions of the second support substrate 1030. Accordingly, there is lower optical interference at the boundary of the active portion sidewall, and specifically at the boundary of the second coupling waveguides 1010 when transferring optical energy into or out of the laser die.
In an embodiment, the third substrate 1510 may be a material that can be used not only for structural support but also may be used as a seed material for epitaxially growing overlying materials and may be, for example, a 2-inch or 4-inch wafer of material, although any suitable size and material may be utilized. In an embodiment the third substrate 1510 may be a semiconductor material used for structural support during subsequent processing, and may be, e.g., a silicon wafer, a silicon germanium wafer, a silicon-on-insulator wafer, or the like. The third substrate 1510 may comprise bulk silicon, doped or undoped, or an active layer of a silicon-on-insulator (SOI) substrate. Generally, an SOI substrate comprises a layer of a semiconductor material such as silicon, germanium, silicon germanium, SOI, silicon germanium on insulator (SGOI), or combinations thereof. Other substrates that may be used include multi-layered substrates, gradient substrates, or hybrid orientation substrates.
Optionally, active devices (not shown here) may be added to the third substrate 1510. The active devices comprise a wide variety of active devices and passive devices such as capacitors, resistors, inductors and the like that may be used to generate the desired structural and functional requirements of the design for the third substrate 1510. The active devices may be formed using any suitable methods either within or else on the third substrate 1510.
In an embodiment the metallization layers are formed of alternating layers of dielectric material 1550 (e.g., low-k dielectric materials, extremely low-k dielectric material, ultra low-k dielectric materials, combinations of these, or the like) and conductive material 1540 and may be formed through any suitable processes (such as deposition, damascene, dual damascene, etc.). However, any suitable materials and processes may be utilized. In particular embodiments there may be multiple layers of metallization used to interconnect the various optical components, but the precise number of metallization layers is dependent upon the design of the interposer 130 and the first integrated package 100.
In some embodiments, the interposer 130 may additionally include a core substrate and/or dielectric layers 1530, and bonding vias 1520 electrically connecting the conductive material 1540 in the metallization layers to the third bonding pads 1580 in a third bonding layer 1560. The third bonding layer 1560 additionally includes a third dielectric material 1570. The third bonding layer may be formed using a damascene, dual damascene, etc., process as described above in relation to
In a particular embodiment which utilizes a dielectric-to-dielectric and metal-to-metal bonding process, the process may be initiated by activating the surfaces of the singulated COUPE die 110, the surfaces of the first bonding layer 910, the surfaces of the singulated laser die 120, the surfaces of the second bonding layer 1410, the surfaces of the interposer, and the surfaces of the third bonding layer 1560. Activating the top surfaces of the bonding layers, the singulated COUPE die 110, the singulated laser die 120, and the interposer 130 may comprise a dry treatment, a wet treatment, a plasma treatment, exposure to an inert gas plasma, exposure to H2, exposure to N2, exposure to O2, combinations thereof, or the like, as examples. In embodiments where a wet treatment is used, an RCA cleaning may be used, for example. In another embodiment, the activation process may comprise other types of treatments. The activation process assists in the bonding of the singulated COUPE die 110 and the singulated laser die 120 to the interposer 130.
After the activation process the interposer 130, the singulated COUPE die 110, and the singulated laser die 120 may be cleaned using, e.g., a chemical rinse, and then the singulated COUPE die 110 and the singulated laser die 120 are aligned and placed into physical contact with the interposer 130. In some embodiments, the singulated COUPE die 110 and the singulated laser die 120 may be placed on the interposer 130 at a distance D3 between about 5 μm to about 100 μm apart.
The interposer 130, the singulated COUPE die 110, the singulated laser die 120 are then subjected to thermal treatment and contact pressure to bond the singulated COUPE die 110 and the singulated laser die 120 to the interposer 130. For example, the interposer 130, the singulated COUPE die 110, and the singulated laser die 120 may be subjected to a pressure of about 200 kPa or less, and a temperature between about 25° C. and about 250° C. to fuse the singulated COUPE die 110 and the singulated laser die 120 with the interposer 130. The interposer 130, the singulated COUPE die 110, and the singulated laser die 120 may then be subjected to a temperature at or above the eutectic point for material of the first bond pads 440, second bond pad 1240, and the third bond pads 1580, e.g., between about 150° C. and about 650° C., to fuse the metal. In this manner, the singulated COUPE die 110 and the singulated laser die 120 forms a dielectric-to-dielectric and metal-to-metal bonded device with the interposer 130. In some embodiments, the bonded dies are subsequently baked, annealed, pressed, or otherwise treated to strengthen or finalize the bond.
Additionally, while specific processes have been described to initiate and strengthen the bonds, these descriptions are intended to be illustrative and are not intended to be limiting upon the embodiments. Rather, any suitable combination of baking, annealing, pressing, or combination of processes may be utilized. All such processes are fully intended to be included within the scope of the embodiments.
Due to the preparation of the bonding layers of the singulated COUPE die 110, the singulated laser die 120, and the interposer 130, and specifically due to the CMP finishing of each of the associated bonding layers described above, the surfaces of the singulated COUPE die 110, the singulated laser die 120, and the interposer 130 achieve a high level of coplanarity. As a result, when compared to conventional methods utilizing micro-bump joint between dies and an interposer, vertical shift between the alignment of the singulated COUPE die 110 and the singulated laser die 120 after placement from a reflow bonding process is virtually eliminated, or at least substantially reduced.
The dielectric-to-dielectric and metal-to-metal bond has the added benefit of resulting in harder rigidity of the individual components due at least in part to the stronger silicon oxide bond. The dielectric-to-dielectric and metal-to-metal bond additionally results in reduced vertical shift when compared to conventional micro-bump joints. Conventional micro-bump joints exhibit a 1 μm to 3 μm horizontal shift during reflow. In comparison the dielectric-to-dielectric and metal-to-metal bond limits the horizontal shift to between 0.2 μm to 0.8 μm. All these benefits result in improved optical alignment between the first coupling waveguides 210 of the singulated COUPE die 110 and second coupling waveguides 1010 of the singulated laser die 120. This results in lower optical loss, fewer manufacturing defects, larger allowable design tolerances, and smaller sized manufacturing capabilities relative to conventional bonding approached such as micro-bump joints.
In some embodiments, as shown in
In
In instances where the coupling lens 240 of the singulated COUPE die 110 is recessed below the topmost surface of the singulated COUPE die 110, further etching, grinding, and/or patterning may be performed on the encapsulant 1710 to expose the coupling lens 240 of the singulated COUPE die 110.
In some embodiments, as shown in
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In other embodiments, such as shown in
For example, in a possible embodiment, at any desired point in the manufacturing process, the TSVs 1910 may be formed within the third substrate 1510 in order to provide electrical connectivity from a front side of the third substrate 1510 to a back side of the third substrate 1510. In an embodiment the second TSVs 1910 may be formed by initially forming through silicon via (TSV) openings into the third substrate 1510 prior to forming the alternating layers of dielectric material 1550 and conductive materials 1540, as well as the third bonding layer 1560, as described in relation to
Once the TSV openings have been formed within the third substrate 1510, the TSV openings may be lined with a liner. The liner may be, e.g., an oxide formed from tetraethylorthosilicate (TEOS) or silicon nitride, although any suitable dielectric material may be used. The liner may be formed using a plasma enhanced chemical vapor deposition (PECVD) process, although other suitable processes, such as physical vapor deposition or a thermal process, may be used.
Once the liner has been formed along the sidewalls and bottom of the TSV openings, a barrier layer may be formed and the remainder of the TSV openings may be filled with first conductive material. The first conductive material may comprise copper, although other suitable materials such as aluminum, alloys, doped polysilicon, combinations thereof, and the like, may be utilized. The first conductive material may be formed by electroplating copper onto a seed layer, filling and overfilling the TSV openings. Once the TSV openings have been filled, excess liner, barrier layer, seed layer, and conductive material outside of the TSV openings may be removed through a planarization process such as chemical mechanical polishing (CMP), although any suitable removal process may be used.
Once the TSV openings have been filled, after the formation of the alternating layers of dielectric material 1550 and conductive materials 1540, as well as the formation of the third bonding layer 1560, and after bonding the COUPE die(s) 810 and laser die(s) 1310 to the interposer 130, the third substrate 1510 may be thinned until the TSVs 1910 have been exposed. In an embodiment the third substrate 1510 may be thinned using, e.g., a chemical mechanical polishing process, a grinding process, or the like. Further, once exposed, the TSVs 1910 may be recessed using, e.g., one or more etching processes, such as a wet etch process in order to recess the third substrate 1510 so that the TSVs 1910 extend out of the third substrate 1510.
In an embodiment the second external connectors 1940 may be placed on the third substrate 1510 in electrical connection with the second TSVs 1910 and may be, e.g., a ball grid array (BGA) which comprises a eutectic material such as solder 1950, although any suitable materials may be used. Optionally, an underbump metallization or additional metallization layers (not separately illustrated in
Embodiments have been described with respect to a specific context, namely applied to a system on integrated chip (SoIC) package. However, other embodiments may also be applied to other packages, including Chip-on-Wafer-on-Substrate (CoWoS®) packages or integrated fan-out (InFO) packages, as examples. Further, as shown in
By utilizing the methods and processes as described above, vertical misalignment during fabrication between dies sending and receiving optical signals/energy can be virtually eliminated or at least substantially reduced, and horizontal misalignment during fabrication can be greatly reduced. Further, optical losses resulting from medium shifts between dies sending and receiving optical signals/energy can be reduced. Accordingly, utilizing the processes described can result in fewer manufacturing defects, and allow for smaller optical design requirements.
In an embodiment, an integrated package includes: an optical die, where the optical die include photonic integrated circuits (PICs), electronic integrated circuits (EICs), and one or more first coupling waveguides; a laser die, where the laser die includes at least one laser diode, and one or more second coupling waveguides; an interposer, where the optical die is bonded to a first side of the interposer using a metal-to-metal bonding, where the laser die is bonded to the first side of the interposer using a metal-to-metal bonding, and where at least one of the one or more first coupling waveguides is optically aligned with at least one of the one or more second coupling waveguides; and an optical glue filling a gap between the aligned at least one of the one or more first coupling waveguides and the at least one of the one or more second coupling waveguides.
In an embodiment, the integrated package further includes an encapsulant, where the encapsulant covers the interposer and surrounds the optical die, the laser die, and the optical glue.
In an embodiment, the integrated package further includes a redistribution structure on a second side of the interposer opposite the first side, where the redistribution structure includes one or more layers of dielectric and one or more layers of metallization, and where the one or more layers of metallization electrically connect the interposer to a plurality of external connectors.
In an embodiment, the integrated package further includes a silicon substrate attached to a second side of the interposer opposite the first side, where the silicon substrate includes through-silicon vias (TSVs) through the silicon substrate and electrically connecting the interposer to a plurality of external connectors.
In an embodiment, at least two sidewalls of the optical die include a substantially straight first portion closest to the interposer, a substantially straight second portion furthest from the interposer, and a third portion between the first portion and the second portion that is tapered; where the at least two sidewalls are on opposite sides of the optical die, where at least one of the at least two sidewalls intersects with the least one of the one or more first coupling waveguides optically aligned with the at least one of the one or more second coupling waveguides; and where a first width of the optical die between the first portion of the at least two sidewalls is larger than a second width of the optical die between the second portion of the at least two sidewalls.
In an embodiment, the third portion is tapered to form a rounded concave profile in the sidewall of the optical die between the first portion and the second portion of the sidewall.
In an embodiment, the optical die and the laser die are horizontally spaced between about 5 μm and about 100 μm apart on the interposer, and the optical die and laser die are each further bonded to the interposer using a dielectric-to-dielectric bond.
In an embodiment, a method for forming an integrated package includes: forming a first bonding layer, including a first dielectric layer and a first metallization layer, on a first side of an optical die, where the optical die includes photonic integrated circuits (PICs), electronic integrated circuits (EICs), and one or more first coupling waveguides; forming a second bonding layer, including a second dielectric layer and a second metallization layer, on a first side of a laser die, where the laser die includes at least one laser diode and one or more second coupling waveguides; forming a third bonding layer, including a third dielectric layer and a third metallization layer, on a first side of an interposer; aligning the first side of the optical die and the first side of the laser die on the first side of the interposer, where the first bonding layer of the optical die and the second bonding layer of the laser die are in physical contact with the third bonding layer of the interposer, and where at least one of the one or more first coupling waveguides is optically aligned with at least one of the one or more second coupling waveguides; forming a metal-to-metal bond between the first bonding layer and the third bonding layer and between the second bonding layer and the third bonding layer; and filling a void between the optical die and the laser die with an optical glue.
In an embodiment, the method of forming the integrated package further includes, before aligning the first side of the optical die and the first side of the laser die on the first side of the interposer, a multi-step singulation of the optical die including: performing a dry etch from a first direction to partially singulate between at least two optical dies, where the dry etch forms a trench penetrating into the optical die through an active portion of the optical die, and where the dry etch partially penetrates through a first substrate of the optical die attached to the active portion of the optical die; and sawing through an un-etched portion of the first substrate from a second direction, opposite the first direction, using a saw blade, where the saw blade forms a tapered or rounded cutting profile in at least a portion of a cut surface of the first substrate, and where a largest width of a cutting portion of the saw blade is greater than a largest width of the dry etch trench.
In an embodiment, the method of forming the integrated package further includes, before aligning the first side of the optical die and the first side of the laser die on the first side of the interposer, a multi-step singulation of the laser die including: performing a dry etch from a first direction to partially singulate between at least two laser dies, where the dry etch forms a trench penetrating into the laser die through an active portion of the laser die including a laser diode, and where the dry etch partially penetrates through a second substrate of the laser die attached to the active portion of the laser die; and sawing through an un-etched portion of the second substrate from a second direction, opposite the first direction, using a saw blade, where the saw blade forms a tapered or rounded cutting profile in at least a portion of a cut surface of the second substrate, and where a largest width of a cutting portion of the saw blade is greater than a largest width of the dry etch trench.
In an embodiment, the method of forming the integrated package further includes: forming a dielectric-to-dielectric bond between the first bonding layer and the third bonding layer and between the second bonding layer and the third bonding layer; and forming an encapsulant over the interposer, where the encapsulant surrounds the optical die, the laser die, and the optical glue.
In an embodiment, the method of forming the integrated package further includes electrically connecting the interposer to a plurality of external connectors on a side of the interposer opposite the optical die and the laser die.
In an embodiment, electrically connecting the interposer to the plurality of external connectors includes: de-bonding a third substrate from the interposer; forming or attaching a first side of a redistribution structure on a second side of the interposer opposite the optical die and the laser die, where the redistribution structure includes one or more dielectric layers, and one or more metallization layers; and forming external connectors on a second side of the redistribution structure opposite the interposer, where the one or more metallization layers of the redistribution structure electrically connect the interposer to the plurality of external connectors.
In an embodiment, electrically connecting the interposer to the plurality of external connectors includes: forming one or more through-silicon vias (TSVs) through a third substrate attached to a second side of the interposer opposite the optical die and the laser die; and forming external connectors on a side of the third substrate opposite the interposer, where the TSVs electrically connect the interposer to the plurality of external connectors.
In an embodiment, a device includes: one or more integrated packages, where each integrated package includes: an optical die, where the optical die includes one or more photonic integrated circuits (PICs), one or more first coupling waveguides optically connected to at least one of the one or more PICS, and a first bonding layer including a first dielectric and a first metallization layer formed using a damascene or dual damascene process; a laser die, where the laser die includes at least one laser diode, one or more second coupling waveguides, and a second bonding layer including a second dielectric and a second metallization layer formed using a damascene or dual damascene process, and where at least one of the one or more second coupling waveguides is optically connected to the laser diode; an interposer, where the interposer includes a third bonding layer including a third dielectric and a third metallization layer, where the first bonding layer of the optical die is bonded to the third bonding layer of the interposer using metal-to-metal bonding, where the second bonding layer of the laser die is bonded to the third bonding layer of the interposer using metal-to-metal bonding, and where at least one of the one or more first coupling waveguides is optically aligned with at least one of the one or more second coupling waveguides; and an optical glue, where the optical glue fills a gap between the aligned at least one of the one or more first coupling waveguides and the at least one of the one or more second coupling waveguides as an optical transmission medium between the optical die and the laser die.
In an embodiment, the first bonding layer of the optical die and the second bonding layer of the laser die are each further bonded to the third bonding layer of the interposer using a dielectric-to-dielectric bond, where the one or more integrated packages further include an encapsulant, where the encapsulant covers the interposer and surrounds the optical die, the laser die, and the optical glue, and where the encapsulant is in contact with at least one sidewall of the optical die, one sidewall or the laser die, and a top of the optical glue.
In an embodiment, the one or more integrated packages further include a redistribution structure attached to a second side of the interposer opposite the third bonding layer, where the redistribution structure includes one or more layers of dielectric and one or more layers of metallization, and where the one or more layers of metallization electrically connect the interposer to a plurality of external connectors.
In an embodiment, the one or more integrated packages further include a silicon substrate attached to a second side of the interposer opposite the third bonding layer, where the silicon substrate includes through-silicon vias (TSVs) electrically connecting the interposer to a plurality of external connectors.
In an embodiment, at least two sidewalls of the optical die and at least two sidewalls of the laser die include a substantially straight first portion closest to the interposer, a substantially straight second portion furthest from the interposer, and a third portion between the first portion and the second portion that is tapered; where the at least two sidewalls are on opposite sides of the optical die and the laser die, and where at least one of the at least two sidewalls of the optical die intersects with the least one of the one or more first coupling waveguides optically aligned with the at least one of the one or more second coupling waveguides, and where the at least one of the at least two sidewalls of the laser die intersects with the least one of the one or more second coupling waveguides optically aligned with the at least one of the one or more first coupling waveguides; where a first width of the optical die between the first portion of the at least two sidewalls is larger than a second width of the optical die between the second portion of the at least two sidewalls; and where a third width of the laser die between the first portion of the at least two sidewalls is larger than a fourth width of the laser die between the second portion of the at least two sidewalls.
In an embodiment, the one or more integrated packages are integrated horizontally and/or vertically on a redistribution layer (RDL) interconnect, on a silicon interposer, on an RDL interposer, on a local silicon interconnect and a RDL interposer, or on an integrated fan out with one or more additional heterogeneous integrated packages, memories, or dies.
The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.
