Patent Grant
10748904
The present invention relates to semiconductor memory technology. More specifically, the present invention relates to methods of maintaining the state of semiconductor memory device/array of devices having an electrically floating body transistor.
Semiconductor memory devices are used extensively to store data. Static and Dynamic Random Access Memory (SRAM and DRAM, respectively) are widely used in many applications. SRAM typically consists of six transistors and hence has a large cell size. However, unlike DRAM, it does not require periodic refresh operations to maintain its memory state. Conventional DRAM cells consist of a one-transistor and one-capacitor (1T/1C) structure. As the 1T/1C memory cell feature is being scaled, difficulties arise due to the necessity of maintaining the capacitance value.
DRAM based on the electrically floating body effect has been proposed (see for example “A Capacitor-less 1T-DRAM Cell”, S. Okhonin et al., pp. 85-87, IEEE Electron Device Letters, vol. 23, no. 2, February 2002 and “Memory Design Using One-Transistor Gain Cell on SOI”, T. Ohsawa et al., pp. 152-153, Tech. Digest, 2002 IEEE International Solid-State Circuits Conference, February 2002). Such memory eliminates the capacitor used in the conventional 1T/1C memory cell, and thus is easier to scale to smaller feature size. In addition, such memory allows for a smaller cell size compared to the conventional 1T/1C memory cell. However, unlike SRAM, such DRAM memory cell still requires refresh operation, since the stored charge leaks over time.
A conventional 1T/1C DRAM refresh operation involves first reading the state of the memory cell, followed by re-writing the memory cell with the same data. Thus this read-then-write refresh requires two operations: read and write. The memory cell cannot be accessed while being refreshed. An “automatic refresh” method”, which does not require first reading the memory cell state, has been described in Fazan et al., U.S. Pat. No. 7,170,807. However, such operation still interrupts access to the memory cells being refreshed.
In addition, the charge in a floating body DRAM memory cell decreases over repeated read operations. This reduction in floating body charge is due to charge pumping, where the floating body charge is attracted to the surface and trapped at the interface (see for example “Principles of Transient Charge Pumping on Partially Depleted SOI MOSFETs”, S. Okhonin, et al., pp. 279-281, IEEE Electron Device Letters, vol. 23, no. 5, May 2002).
Thus there is a continuing need for semiconductor memory devices and methods of operating such devices such that the states of the memory cells of the semiconductor memory device are maintained without interrupting the memory cell access.
There is also a need for semiconductor memory devices and methods of operating the same such that the states of the memory cells are maintained upon repeated read operations.
The present invention meets the above needs and more as described in detail below.
In one aspect of the present invention, a method of maintaining a state of a memory cell without interrupting access to the memory cell is provided, including: applying a back bias to the cell to offset charge leakage out of a floating body of the cell, wherein a charge level of the floating body indicates a state of the memory cell; and accessing the cell.
In at least one embodiment, the applying comprises applying the back bias to a terminal of the cell that is not used for address selection of the cell.
In at least one embodiment, the back bias is applied as a constant positive voltage bias.
In at least one embodiment, the back bias is applied as a periodic pulse of positive voltage.
In at least one embodiment, a maximum potential that can be stored in the floating body is increased by the application of back bias to the cell, resulting in a relatively larger memory window.
In at least one embodiment, the application of back bias performs a holding operation on the cell, and the method further comprises simultaneously performing a read operation on the cell at the same time that the holding operation is being performed.
In at least one embodiment, the cell is a multi-level cell, wherein the floating body is configured to indicate more than one state by storing multi-bits, and the method further includes monitoring cell current of the cell to determine a state of the cell.
In another aspect of the present invention, a method of operating a memory array having rows and columns of memory cells assembled into an array of the memory cells is provided, wherein each memory cell has a floating body region for storing data, the method including: performing a holding operation on at least all of the cells not aligned in a row or column of a selected cell; and accessing the selected cell and performing a read or write operation on the selected cell while performing the hold operation on the at least all of the cells not aligned in a row or column of the selected cell.
In at least one embodiment, the performance of a holding operation comprises performing the holding operation on all of the cells and the performing a read or write operation comprises performing a read operation on the selected cell.
In at least one embodiment, the holding operation is performed by applying back bias to a terminal not used for memory address selection.
In at least one embodiment, the terminal is segmented to allow independent control of the applied back bias to a selected portion of the memory array.
In at least one embodiment, the performance of a holding operation comprises performing the holding operation on all of the cells except for the selected cell, and the performing a read or write operation comprises performing a write “0” operation on the selected cell, wherein a write “0” operation is also performed on all of the cells sharing a common source line terminal with the selected cell during the performing a write “0” operation.
In at least one embodiment, an individual bit write “0” operation is performed, wherein the performing a holding operation comprises performing the holding operation on all of the cells except for the selected cell, while the performing a read or write operation comprises performing a write “0” operation on the selected cell.
In at least one embodiment, the performance of a holding operation comprises performing the holding operation on all of the cells except for the selected cell while the performing a read or write operation comprises performing a write “1” operation on the selected cell.
In at least one embodiment, the performance of a holding operation comprises performing the holding operation on all of the cells except for the selected cell while the performing a read or write operation comprises performing a multi-level write operation on the selected cell, using an alternating write and verify algorithm.
In at least one embodiment, the performance of a holding operation comprises performing the holding operation on all of the cells except for the selected cell while the performing a read or write operation comprises performing a multi-level write operation on the selected cell, wherein the multi-level write operation includes: ramping a voltage applied to the selected cell to perform the write operation; reading the state of the selected cell by monitoring a change in current through the selected cell; and removing the ramped voltage applied once the change in cell current reaches a predetermined value.
In at least one embodiment, the performance of a holding operation comprises performing the holding operation on all of the cells except for the selected cell while the performing a read or write operation comprises performing a multi-level write operation on the selected cell, wherein the multi-level write operation includes: ramping a current applied to the selected cell to perform the write operation; reading the state of the selected cell by monitoring a change in voltage across a bit line and a source line of the selected cell; and removing the ramped current applied once the change in cell voltage reaches a predetermined value.
In at least one embodiment, the multi-level write operation permits bit-level selection of a bit portion of memory of the selected cell.
In at least one embodiment, the performance of a holding operation comprises performing the holding operation on all of the cells except for the selected cell while the performing a read or write operation comprises performing a single-level or multi-level write operation on the selected cell, wherein the single-level and each level of the multi-level write operation includes: ramping a voltage applied to the selected cell to perform the write operation; reading the state of the selected cell by monitoring a change in current toward an addressable terminal of the selected cell; and verifying a state of the write operation using a reference memory cell.
In at least one embodiment, the method further includes configuring a state of the reference memory cell using a write-then-verify operation, prior to performing the write operation.
In at least one embodiment, configuring a state of the reference memory cell comprises configuring the state upon power up of the memory array.
In another aspect of the present invention, a method of operating a memory array having rows and columns of memory cells assembled into an array of the memory cells is provided, wherein each memory cell has a floating body region for storing data; and wherein the method includes: refreshing a state of at least one of the memory cells; and accessing at least one other of the memory cells, wherein access of the at least one other of the memory cells in not interrupted by the refreshing, and wherein the refreshing is performed without alternating read and write operations.
In at least one embodiment, at least one of the memory cells is a multi-level memory cell.
In another aspect of the present invention, a method of operating a memory array having rows and columns of memory cells assembled into an array of the memory cells is provided, wherein each memory cell has a floating body region for storing data; and wherein the method includes: accessing a selected memory cell from the memory cells; and performing a simultaneous write and verify operation on the selected memory cell without performing an alternating write and read operation.
In at least one embodiment, the selected memory cell is a multi-level memory cell.
In at least one embodiment, a verification portion of the write and verify operation is performed by sensing a current change in the column direction of the array in a column that the selected cell is connected to.
In at least one embodiment, a verification portion of the write and verify operation is performed by sensing a current change in the row direction of the array in a row that the selected cell is connected to.
In at least one embodiment, a write portion of the write and verify operation employs use of a drain or gate voltage ramp.
In at least one embodiment, a write portion of the write and verify operation employs use of a drain current ramp.
These and other features of the invention will become apparent to those persons skilled in the art upon reading the details of the methods, devices and arrays as more fully described below.
Before the present systems, devices and methods are described, it is to be understood that this invention is not limited to particular embodiments described, as such may, of course, vary. It is also to be understood that the terminology used herein is for the purpose of describing particular embodiments only, and is not intended to be limiting, since the scope of the present invention will be limited only by the appended claims.
Where a range of values is provided, it is understood that each intervening value, to the tenth of the unit of the lower limit unless the context clearly dictates otherwise, between the upper and lower limits of that range is also specifically disclosed. Each smaller range between any stated value or intervening value in a stated range and any other stated or intervening value in that stated range is encompassed within the invention. The upper and lower limits of these smaller ranges may independently be included or excluded in the range, and each range where either, neither or both limits are included in the smaller ranges is also encompassed within the invention, subject to any specifically excluded limit in the stated range. Where the stated range includes one or both of the limits, ranges excluding either or both of those included limits are also included in the invention.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Although any methods and materials similar or equivalent to those described herein can be used in the practice or testing of the present invention, the preferred methods and materials are now described. All publications mentioned herein are incorporated herein by reference to disclose and describe the methods and/or materials in connection with which the publications are cited.
It must be noted that as used herein and in the appended claims, the singular forms “a”, “an”, and “the” include plural referents unless the context clearly dictates otherwise. Thus, for example, reference to “a cell” includes a plurality of such cells and reference to “the terminal” includes reference to one or more terminals and equivalents thereof known to those skilled in the art, and so forth.
The publications discussed herein are provided solely for their disclosure prior to the filing date of the present application. Nothing herein is to be construed as an admission that the present invention is not entitled to antedate such publication by virtue of prior invention. Further, the dates of publication provided may be different from the actual publication dates which may need to be independently confirmed.
A “holding operation”, “standby operation” or “holding/standby operation”, as used herein, refers to a process of sustaining a state of a memory cell by maintaining the stored charge. Maintenance of the stored charge may be facilitated by applying a back bias to the cell in a manner described herein.
A “a multi-level write operation” refers to a process that includes an ability to write more than more than two different states into a memory cell to store more than one bit per cell.
A “write-then-verify” algorithm or operation refers to a process where alternating write and read operations to a memory cell are employed to verify whether a desired memory state of the memory cell has been achieved during the write operation.
A “read verify operation” refers to a process where a read operation is performed to verify whether a desired memory state of a memory cell has been achieved.
A “read while programming” operation refers to a process where simultaneous write and read operations can be performed to write a memory cell state.
A “back bias terminal” refers to a terminal at the back side of a semiconductor transistor device, usually at the opposite side of the gate of the transistor. A back bias terminal is also commonly referred to as a “back gate terminal”. Herein, the back bias terminal refers to the substrate terminal or the buried well terminal, depending upon the embodiment being described.
The term “back bias” refers to a voltage applied to a back bias terminal.
Referring now to
A floating body region 24 having a second conductivity type different from the first conductivity type, such as p-type conductivity type when the first conductivity type is n-type conductivity type, is bounded by surface 14, first and second regions 16, 18, insulating layers 26, and substrate 12. The floating body region 24 can be formed by an implantation process formed on the material making up substrate 12, or can be grown epitaxially. Insulating layers 26 (e.g. shallow trench isolation (STI)), may be made of silicon oxide, for example. Insulating layers 26 insulate cell 50 from neighboring cells 50 when multiple cells 50 are joined in an array 80 to make a memory device as illustrated in
Cell 50 further includes word line (WL) terminal 70 electrically connected to gate 60, source line (SL) terminal 72 electrically connected to one of regions 16 and 18 (connected to 16 as shown, but could, alternatively, be connected to 18), bit line (BL) terminal 74 electrically connected to the other of regions 16 and 18 (connected to 18 as shown, but could, alternatively, be connected to 16 when 72 is connected to 18), and substrate terminal 78 electrically connected to substrate 12. Contact to substrate region can alternatively be made through region 20 having a first conductivity type, and which is electrically connected to substrate region 12, as shown in
In another embodiment, the memory cell 50 has a p-type conductivity type as the first conductivity type and n-type conductivity type as the second conductivity type, as noted above.
The operation of a memory cell 50 has been described for example in “Scaled 1T-Bulk Devices Built with CMOS 90 nm Technology for Low-cost eDRAM Applications”, R. Ranica, et al., pp. 38-41, Tech. Digest, Symposium on VLSI Technology, 2005, which is hereby incorporated herein, in its entirety, by reference thereto. The memory cell states are represented by the charge in the floating body 24. If cell 50 has holes stored in the floating body region 24, then the memory cell 50 will have a lower threshold voltage (gate voltage where transistor is turned on) compared to when cell 50 does not store holes in floating body region 24.
The positive charge stored in the floating body region 24 will decrease over time due to the p-n diode leakage formed by floating body 24 and regions 16, 18, and substrate 12 and due to charge recombination. A unique capability of the invention is the ability to perform the holding operation in parallel to all memory cells 50 of the array 80. The holding operation can be performed by applying a positive back bias to the substrate terminal 78 while grounding terminal 72 and/or terminal 74. The positive back bias applied to the substrate terminal will maintain the state of the memory cells 50 that it is connected to. The holding operation is relatively independent of the voltage applied to terminal 70. As shown in
A fraction of the bipolar transistor current will then flow into floating region 24 (usually referred to as the base current) and maintain the state “1” data. The efficiency of the holding operation can be enhanced by designing the bipolar device formed by substrate 12, floating region 24, and regions 16, 18 to be a low-gain bipolar device, where the bipolar gain is defined as the ratio of the collector current flowing out of substrate terminal 78 to the base current flowing into the floating region 24.
For memory cells in state “0” data, the bipolar devices 30a, 30b will not be turned on, and consequently no base hole current will flow into floating region 24. Therefore, memory cells in state “0” will remain in state “0”.
As can be seen, the holding operation can be performed in mass, parallel manner as the substrate terminal 78 (e.g., 78a, 78b, . . . , 78n) is typically shared by all the cells 50 in the memory array 80. The substrate terminal 78 can also be segmented to allow independent control of the applied bias on the selected portion of the memory array as shown in
In another embodiment, a periodic pulse of positive voltage can be applied to substrate terminal 78, as opposed to applying a constant positive bias, in order to reduce the power consumption of the memory cell 50. The state of the memory cell 50 can be maintained by refreshing the charge stored in floating body 24 during the period over which the positive voltage pulse is applied to the back bias terminal (i.e., substrate terminal 78).
The holding/standby operation also results in a larger memory window by increasing the amount of charge that can be stored in the floating body 24. Without the holding/standby operation, the maximum potential that can be stored in the floating body 24 is limited to the flat band voltage VFB as the junction leakage current to regions 16 and 18 increases exponentially at floating body potential greater than VFB. However, by applying a positive voltage to substrate terminal 78, the bipolar action results in a hole current flowing into the floating body 24, compensating for the junction leakage current between floating body 24 and regions 16 and 18. As a result, the maximum charge VMC stored in floating body 24 can be increased by applying a positive bias to the substrate terminal 78 as shown in
The holding/standby operation can also be used for multi-bit operations in memory cell 50. To increase the memory density without increasing the area occupied by the memory cell 50, a multi-level operation is typically used. This is done by dividing the overall memory window into different levels. In floating body memory, the different memory states are represented by different charges in the floating body 24, as described for example in “The Multistable Charge-Controlled Memory Effect in SOI Transistors at Low Temperatures”, Tack et al., pp. 1373-1382, IEEE Transactions on Electron Devices, vol. 37, May 1990 and U.S. Pat. No. 7,542,345 “Multi-bit memory cell having electrically floating body transistor, and method of programming and reading same”, each of which is hereby incorporated herein, in its entirety, by reference thereto. However, since the state with zero charge in the floating body 24 is the most stable state, the floating body 24 will, over time, lose its charge until it reaches the most stable state. In multi-level operations, the difference of charge representing different states is smaller than that for a single-level operation. As a result, a multi-level memory cell is more sensitive to charge loss, as less charge loss is required to change states.
An example of the bias condition for the holding operation is hereby provided: zero voltage is applied to BL terminal 74, zero voltage is applied to SL terminal 72, zero or negative voltage is applied to WL terminal 70, and a positive voltage is applied to the substrate terminal 78. In one particular non-limiting embodiment, about 0.0 volts is applied to terminal 72, about 0.0 volts is applied to terminal 74, about 0.0 volts is applied to terminal 70, and about +1.2 volts is applied to terminal 78. However, these voltage levels may vary.
The charge stored in the floating body 24 can be sensed by monitoring the cell current of the memory cell 50. If cell 50 is in a state “1” having holes in the floating body region 24, then the memory cell will have a lower threshold voltage (gate voltage where the transistor is turned on), and consequently a higher cell current, compared to if cell 50 is in a state “0” having no holes in floating body region 24. A sensing circuit/read circuitry 90 typically connected to BL terminal 74 of memory array 80 (e.g., see read circuitry 90 in
The read operation can be performed by applying the following bias condition: a positive voltage is applied to the substrate terminal 78, zero voltage is applied to SL terminal 72, a positive voltage is applied to the selected BL terminal 74, and a positive voltage greater than the positive voltage applied to the selected BL terminal 74 is applied to the selected WL terminal 70. The unselected BL terminals will remain at zero voltage and the unselected WL terminals will remain at zero or negative voltage. In one particular non-limiting embodiment, about 0.0 volts is applied to terminal 72, about +0.4 volts is applied to the selected terminal 74, about +1.2 volts is applied to the selected terminal 70, and about +1.2 volts is applied to terminal 78. The unselected terminals 74 remain at 0.0 volts and the unselected terminals 70 remain at 0.0 volts.
The unselected memory cells 50 during read operations are shown in
For memory cells 50 sharing the same row as the selected memory cell, both the SL terminal 72 and BL terminal 74 are at about 0.0 volts (
For memory cells 50 sharing the same column as the selected memory cell, a positive voltage is applied to the BL terminal 74 (
For memory cells 50 not sharing the same row or the same column as the selected memory cell, both the SL terminal 72 and BL terminal 74 are at about 0.0 volts (
From the above description, it can be seen that the holding operation does not interrupt the read operation of the memory cells 50. At the same time, the unselected memory cells 50 during a read operation will remain in a holding operation.
Write operations of memory cell 50 are now described. A write “0” operation of the cell 50 is described with reference to
An example of bias conditions and an equivalent circuit diagram illustrating the intrinsic n-p-n bipolar devices 30a, 30b of unselected memory cells 50 during write “0” operations are illustrated in
The write “0” operation referred to above has a drawback in that all memory cells 50 sharing the same SL terminal will be written to simultaneously and as a result, this does not allow individual bit writing, i.e., writing to a single cell 50 memory bit. To write multiple data to different memory cells 50, write “0” is first performed on all the memory cells, followed by write “1” operations on a selected bit or selected bits.
An alternative write “0” operation that allows for individual bit writing can be performed by applying a positive voltage to WL terminal 70, a negative voltage to BL terminal 74, zero or positive voltage to SL terminal 72, and zero or positive voltage to substrate terminal 78. Under these conditions, the floating body 24 potential will increase through capacitive coupling from the positive voltage applied to the WL terminal 70. As a result of the floating body 24 potential increase and the negative voltage applied to the BL terminal 74, the p-n junction between 24 and 18 is forward-biased, evacuating any holes from the floating body 24. To reduce undesired write “0” disturb to other memory cells 50 in the memory array 80, the applied potential can be optimized as follows: if the floating body 24 potential of state “1” is referred to as VFB1, then the voltage applied to the WL terminal 70 is configured to increase the floating body 24 potential by VFB1/2 while −VFB1/2 is applied to BL terminal 74. A positive voltage can be applied to SI, terminal 72 to further reduce the undesired write “0” disturb on other memory cells 50 in the memory array. The unselected cells will remain at holding state, i.e. zero or negative voltage applied to WL terminal 70 and zero voltage applied to BL terminal 74.
In one particular non-limiting embodiment, the following bias conditions are applied to the selected memory cell 50a: a potential of about 0.0 volts is applied to terminal 72, a potential of about −0.2 volts is applied to terminal 74, a potential of about +0.5 volts is applied to terminal 70, and about +1.2 volts is applied to terminal 78; while about 0.0 volts is applied to terminal 72, about 0.0 volts is applied to terminal 74, about 0.0 volts is applied to terminal 70, and about +1.2 volts is applied to terminal 78 of the unselected memory cells.
The bias conditions of the selected memory cell 50a under write “0” operation are further elaborated and are shown in
The unselected memory cells 50 during write “0” operations are shown in
For memory cells sharing the same row as the selected memory cell, both the SL terminal 72 and BL terminal 74 are at about 0.0 volts (
Accordingly, with careful design concerning the voltage applied to WL terminal 70, the states of the unselected memory cells sharing the same WL terminal (i.e. the same row) as the selected memory cells will be maintained.
For memory cells sharing the same column as the selected memory cell, a negative voltage is applied to the BL terminal 74 (see
As to memory cells not sharing the same row or the same column as the selected memory cell, both the SL terminal 72 and BL terminal 74 are at about 0.0 volts (see
Accordingly, the present invention provides for a write “0” operation that allows for bit selection. The positive bias applied to the substrate terminal 78 of the memory cells 50 is necessary to maintain the states of the unselected cells 50, especially those sharing the same row and column as the selected cells 50, as the bias conditions can potentially alter the states of the memory cells 50 without the intrinsic bipolar devices 30a, 30b (formed by substrate 12, floating body 24, and regions 16, 18, respectively) re-establishing the equilibrium condition. Also, the positive bias applied to the substrate terminal 78 employed for the holding operation does not interrupt the write “0” operation of the selected memory cell(s).
A write “1” operation can be performed on memory cell 50 through impact ionization or band-to-band tunneling mechanism, as described for example in “A Design of a Capacitorless 1T-DRAM Cell Using Gate-Induced Drain Leakage (GIDL) Current for Low-power and High-speed Embedded Memory”, Yoshida et al., pp. 913-918, International Electron Devices Meeting, 2003, which was incorporated by reference above.
An example of the bias condition of the selected memory cell 50 under band-to-band tunneling write “I” operation is illustrated in
In one particular non-limiting embodiment, the following bias conditions are applied to the selected memory cell 50a: a potential of about 0.0 volts is applied to terminal 72, a potential of about +1.2 volts is applied to terminal 74, a potential of about −1.2 volts is applied to terminal 70, and about +1.2 volts is applied to terminal 78, and the following bias conditions are applied to the unselected memory cells 50: about 0.0 volts is applied to terminal 72, about 0.0 volts is applied to terminal 74, about 0.0 volts is applied to terminal 70, and about +1.2 volts is applied to terminal 78.
The unselected memory cells during write “1” operations are shown in
For memory cells sharing the same row as the selected memory cell, both the SL terminal 72 and BL terminal 74 are at about 0.0 volts, with the WL terminal 70 at zero or negative voltage (
For memory cells sharing the same column as the selected memory cell, a positive voltage is applied to the BL terminal 74. As a result, the bipolar device 30b formed by substrate 12, floating body 24, and region 18 connected to BL terminal 74 will be turned off because of the small voltage difference between the substrate terminal 78 and BL terminal 74 (the collector and emitter terminals, respectively). However, the bipolar device 30a formed by substrate 12, floating body 24, and region 16 connected to SL terminal 72 will still generate base hole current for memory cells in state “1” having positive charge in floating body 24. Memory cells in state “0” will remain in state “0” as this bipolar device 30a (formed by substrate 12, floating body 24, and region 16) is off.
For memory cells not sharing the same row or the same column as the selected memory cell, both the SL terminal 72 and BL terminal 74 are at about 0.0 volts (see
Thus the positive bias applied to the substrate terminal 78 employed for the holding operation does not interrupt the write “I” operation of the selected memory cell(s). At the same time, the unselected memory cells during write “I” operation will remain in holding operation.
A multi-level write operation can be performed using an alternating write and verify algorithm, where a write pulse is first applied to the memory cell 50, followed by a read operation to verify if the desired memory state has been achieved. If the desired memory state has not been achieved, another write pulse is applied to the memory cell 50, followed by another read verification operation. This loop is repeated until the desired memory state is achieved.
For example, using band-to-band tunneling hot hole injection, a positive voltage is applied to BL terminal 74, zero voltage is applied to SL terminal 72, a negative voltage is applied to WL terminal 70, and a positive voltage is applied to the substrate terminal 78. Positive voltages of different amplitude are applied to BL terminal 74 to write different states to floating body 24. This results in different floating body potentials 24 corresponding to the different positive voltages or the number of positive voltage pulses that have been applied to BL terminal 74. By applying positive voltage to substrate terminal 78, the resulting floating body 24 potential is maintained through base hole current flowing into floating body 24. In one particular non-limiting embodiment, the write operation is performed by applying the following bias condition: a potential of about 0.0 volts is applied to terminal 72, a potential of about −1.2 volts is applied to terminal 70, and about +1.2 volts is applied to terminal 78, while the potential applied to BL terminal 74 is incrementally raised. For example, in one non-limiting embodiment 25 millivolts is initially applied to BL terminal 74, followed by a read verify operation. If the read verify operation indicates that the cell current has reached the desired state (i.e., cell current corresponding to whichever of 00, 01, 10 or 11 is desired is achieved), then the multi write operation is commenced. If the desired state is not achieved, then the voltage applied to BL terminal 74 is raised, for example, by another 25 millivolts, to 50 millivolts. This is subsequently followed by another read verify operation, and this process iterates until the desired state is achieved. However, the voltage levels described may vary. The write operation is followed by a read operation to verify the memory state.
The write-then-verify algorithm is inherently slow since it requires multiple write and read operations. The present invention provides a multi-level write operation that can be performed without alternate write and read operations. This is accomplished by ramping the voltage applied to BL terminal 74, while applying zero voltage to SL terminal 72, a positive voltage to WL terminal 70, and a positive voltage to substrate terminal 78 of the selected memory cells. The unselected memory cells will remain in holding mode, with zero or negative voltage applied to WL terminal 70 and zero voltage applied to BL terminal 74. These bias conditions will result in a hole injection to the floating body 24 through impact ionization mechanism. The state of the memory cell 50 can be simultaneously read for example by monitoring the change in the cell current through a read circuitry 90 (
As shown in
In a similar manner, a multi-level write operation using an impact ionization mechanism can be performed by ramping the write current applied to BL terminal 74 instead of ramping the BL terminal 74 voltage.
In yet another embodiment, a multi-level write operation can be performed through a band-to-band tunneling mechanism by ramping the voltage applied to BL terminal 74, while applying zero voltage to SL terminal 72, a negative voltage to WL terminal 70, and zero or positive voltage to substrate terminal 78 of the selected memory cells 50. The unselected memory cells 50 will remain in holding mode, with zero or negative voltage applied to WL terminal 70 and zero voltage applied to BL terminal 74. Optionally, multiple BL terminals 74 can be simultaneously selected to write multiple cells in parallel. The potential of the floating body 24 of the selected memory cell(s) 50 will increase as a result of the band-to-band tunneling mechanism. The state of the selected memory cell(s) 50 can be simultaneously read for example by monitoring the change in the cell current through a read circuitry 90 coupled to the source line. Once the change in the cell current reaches the desired level associated with a state of the memory cell, the voltage applied to BL terminal 74 can be removed. If positive voltage is applied to substrate terminal 78, the resulting floating body 24 potential is maintained through base hole current flowing into floating body 24. In this manner, the multi-level write operation can be performed without alternate write and read operations.
Similarly, the multi-level write operation using band-to-band tunneling mechanism can also be performed by ramping the write current applied to BL terminal 74 instead of ramping the voltage applied to BL terminal 74.
In another embodiment, a read while programming operation can be performed by monitoring the change in cell current in the bit line direction through a reading circuitry 90 coupled to the bit line 74 as shown in
In the voltage ramp operation, the resulting cell current of the memory cell 50 being written is compared to the reference cell 50R current by means of the read circuitry 90. During this read while programming operation, the reference cell 50R is also being biased at the same bias conditions applied to the selected memory cell 50 during the write operation. Therefore, the write operation needs to be ceased after the desired memory state is achieved to prevent altering the state of the reference cell 50R. For the current ramp operation, the voltage at the bit line 74 can be sensed instead of the cell current. The bit line voltage can be sensed for example using a voltage sensing circuitry (see
An example of a multi-level write operation without alternate read and write operations, using a read while programming operation/scheme in the bit line direction is given, where two bits are stored per memory cell 50, requiring four states to be storable in each memory cell 50. With increasing charge in the floating body 24, the four states are referred to as states “00”, “01”, “10”, and “11”. To program a memory cell 50 to a state “01”, the reference cell 50R corresponding to state “01” is activated. Subsequently, the bias conditions described above are applied both to the selected memory cell 50 and to the “01” reference cell 50R: zero voltage is applied to the source line terminal 72, a positive voltage is applied to the substrate terminal 78, a positive voltage is applied to the WL terminal 70 (for the impact ionization mechanism), while the BL terminal 74 is being ramped up, starting from zero voltage. Starting the ramp voltage from a low voltage (i.e. zero volts) ensures that the state of the reference cell 50R does not change.
The voltage applied to the BL terminal 74 is then increased. Consequently, holes are injected into the floating body 24 of the selected cell 50 and subsequently the cell current of the selected cell 50 increases. Once the cell current of the selected cell 50 reaches that of the “01” reference cell, the write operation is stopped by removing the positive voltage applied to the BL terminal 74 and WL terminal 70.
As was noted above, a periodic pulse of positive voltage can be applied to substrate terminal 78, as opposed to applying a constant positive bias, to reduce the power consumption of the memory cell 50. The memory cell 50 operations during the period where the substrate terminal 78 is being grounded are now briefly described. During the period when the substrate terminal 78 is grounded, the memory cells 50 connected to a ground substrate terminal 78 are no longer in holding mode. Therefore the period during which the substrate terminal is grounded must be shorter than the charge retention time period of the floating body, to prevent the state of the floating body from changing when the substrate terminal is grounded. The charge lifetime (i.e., charge retention time period) of the floating body 24 without use of a holding mode has been shown to be on the order of milliseconds, for example, see “A Scaled Floating Body Cell (FBC) Memory with High-k+Metal Gate on Thin-Silicon and Thin-BOX for 16-nm Technology Node and Beyond”, Ban et al., pp. 92-92, Symposium on VLSI Technology, 2008, which is hereby incorporated herein, in its entirety, by reference thereto. The state of the memory cell 50 can be maintained by refreshing the charge stored in floating body 24 during the period over which the positive voltage pulse is applied to the back bias terminal (i.e., substrate terminal 78).
A read operation can be performed by applying the following bias conditions: zero voltage is applied to the substrate terminal 78, zero voltage is applied to SL terminal 72, a positive voltage is applied to the selected BL terminal 74, and a positive voltage greater than the positive voltage applied to the selected BL terminal 74 is applied to the selected WL terminal 70. The unselected BL terminals 74 will remain at zero voltage and the unselected WL terminals 70 will remain at zero or negative voltage. If the substrate terminals 78 are segmented (as for example shown in
A write “0” operation of the cell 50 can be performed by applying the following bias conditions: a negative bias is applied to SL terminal 72, zero or negative voltage is applied to WL terminal 70, and zero voltage is applied to substrate terminal 78. The SL terminal 72 for the unselected cells will remain grounded. If the substrate terminals 78 are segmented (as for example shown in
An example of the bias conditions for an alternative write “0” operation which allows for individual bit write is shown in
Still referring to
An example of the bias conditions applied to the memory array 80 under a band-to-band tunneling write “1” operation to cell 50a is shown in
Still referring to
A buried layer 22 of the second conductivity type is also provided in the substrate 12, buried in the substrate 12, as shown. Buried layer 22 may also be formed by an ion implantation process on the material of substrate 12. Alternatively, buried layer 22 can be grown epitaxially. A floating body region 24 of the substrate 12 having a first conductivity type, such as a p-type conductivity type, is bounded by surface, first and second regions 16,18, insulating layers 26 and buried layer 22. Insulating layers 26 (e.g., shallow trench isolation (STI)), may be made of silicon oxide, for example. Insulating layers 26 insulate cell 150 from neighboring cells 150 when multiple cells 150 are joined in an array 180 to make a memory device as illustrated in
Cell 150 further includes word line (WL) terminal 70 electrically connected to gate 60, source line (SL) terminal 72 electrically connected to one of regions 16 and 18 (connected to 16 as shown, but could, alternatively, be connected to 18), bit line (BL) terminal 74 electrically connected to the other of regions 16 and 18, buried well (BW) terminal 76 electrically connected to buried layer 22, and substrate terminal 78 electrically connected to substrate 12 at a location beneath buried layer 22. Contact to buried well region can alternatively be made through region 20 having a second conductivity type, and which is electrically connected to buried well region 22, while contact to substrate region 12 can alternatively be made through region 28 having a first conductivity type, and which is electrically connected to substrate region 12, as shown in
In another embodiment, the memory cell 150 may be provided with p-type conductivity type as the first conductivity type and n-type conductivity type as the second conductivity type.
As shown in
A holding operation can be performed by applying a positive back bias to the BW terminal 76 while grounding terminal 72 and/or terminal 74. If floating body 24 is positively charged (i.e. in a state “1”), the bipolar transistor formed by SL region 16, floating body 24, and buried well region 22 and bipolar transistor formed by BL region 18, floating body 24, and buried well region 22 will be turned on.
A fraction of the bipolar transistor current will then flow into floating region 24 (usually referred to as the base current) and maintain the state “1” data. The efficiency of the holding operation can be enhanced by designing the bipolar devices 130a, 130b formed by buried well layer 22, floating region 24, and regions 16/18 to be a low-gain bipolar device, where the bipolar gain is defined as the ratio of the collector current flowing out of BW terminal 76 to the base current flowing into the floating region 24.
For memory cells in state “0” data, the bipolar devices 130a, 130b will not be turned on, and consequently no base hole current will flow into floating region 24. Therefore, memory cells in state “0” will remain in state “0”.
The holding operation can be performed in mass, parallel manner as the BW terminal 76 (functioning as back bias terminal) is typically shared by all the cells 150 in the memory array 180, or at least by multiple cells 150 in a segment of the array 180. The BW terminal 76 can also be segmented to allow independent control of the applied bias on a selected portion of the memory array 180. Also, because BW terminal 76 is not used for memory address selection, no memory cell access interruption occurs due to the holding operation.
An example of the bias conditions applied to cell 150 to carry out a holding operation includes: zero voltage is applied to BL terminal 74, zero voltage is applied to SL terminal 72, zero or negative voltage is applied to WL terminal 70, a positive voltage is applied to the BW terminal 76, and zero voltage is applied to substrate terminal 78. In one particular non-limiting embodiment, about 0.0 volts is applied to terminal 72, about 0.0 volts is applied to terminal 74, about 0.0 volts is applied to terminal 70, about +1.2 volts is applied to terminal 76, and about 0.0 volts is applied to terminal 78. However, these voltage levels may vary.
A read operation can be performed on cell 150 by applying the following bias conditions: a positive voltage is applied to the BW terminal 76, zero voltage is applied to SL terminal 72, a positive voltage is applied to the selected BL terminal 74, and a positive voltage greater than the positive voltage applied to the selected BL terminal 74 is applied to the selected WL terminal 70, while zero voltage is applied to substrate terminal 78. When cell 150 is in an array 180 of cells 150, the unselected BL terminals 74 (e.g., 74b, . . . , 74n) will remain at zero voltage and the unselected WL terminals 70 (e.g., 70n and any other WL terminals 70 not connected to selected cell 150a) will remain at zero or negative voltage. In one particular non-limiting embodiment, about 0.0 volts is applied to terminal 72, about +0.4 volts is applied to the selected terminal 74a, about +1.2 volts is applied to the selected terminal 70a, about +1.2 volts is applied to terminal 76, and about 0.0 volts is applied to terminal 78, as illustrated in
To write “0” to cell 150, a negative bias is applied to SL terminal 72, zero or negative voltage is applied to WL terminal 70, zero or positive voltage is applied to BW terminal 76, and zero voltage is applied to substrate terminal 78. The SL terminal 72 for the unselected cells 150 that are not commonly connected to the selected cell 150a will remain grounded. Under these conditions, the p-n junctions (junction between 24 and 16 and between 24 and 18) are forward-biased, evacuating any holes from the floating body 24. In one particular non-limiting embodiment, about −2.0 volts is applied to terminal 72, about −1.2 volts is applied to terminal 70, about +1.2 volts is applied to terminal 76, and about 0.0 volts is applied to terminal 78. However, these voltage levels may vary, while maintaining the relative relationships between the charges applied, as described above.
The bias conditions for all the unselected cells are the same since the write “0” operation only involves applying a negative voltage to the SL terminal 72 (thus to the entire row). As can be seen, the unselected memory cells will be in holding operation, with both BL and SL terminals at about 0.0 volts.
Thus, the holding operation does not interrupt the write “0” operation of the memory cells. Furthermore, the unselected memory cells will remain in holding operation during a write “0” operation.
An alternative write “0” operation, which, unlike the previous write “0” operation described above, allows for individual bit write, can be performed by applying a positive voltage to WL terminal 70, a negative voltage to BL terminal 74, zero or positive voltage to SL terminal 72, zero or positive voltage to BW terminal 76, and zero voltage to substrate terminal 78. Under these conditions, the floating body 24 potential will increase through capacitive coupling from the positive voltage applied to the WL terminal 70. As a result of the floating body 24 potential increase and the negative voltage applied to the BL terminal 74, the p-n junction (junction between 24 and 16) is forward-biased, evacuating any holes from the floating body 24. The applied bias to selected WL terminal 70 and selected BL terminal 74 can potentially affect the states of the unselected memory cells 150 sharing the same WL or BL terminal as the selected memory cell 150. To reduce undesired write “0” disturb to other memory cells 150 in the memory array 180, the applied potential can be optimized as follows: If the floating body 24 potential of state “1” is referred to as VFB1, then the voltage applied to the WL terminal 70 is configured to increase the floating body 24 potential by VFB1/2 while −VFB1/2 is applied to BL terminal 74. This will minimize the floating body 24 potential change in the unselected cells 150 in state “1” sharing the same BL terminal as the selected cell 150 from VFB1 to VFB1/2. For memory cells 150 in state “0” sharing the same WL terminal as the selected cell 150, if the increase in floating body 24 potential is sufficiently high (i.e., at least VFB/3, see below), then both n-p-n bipolar devices 130a and 130b will not be turned on or so that the base hold current is low enough that it does not result in an increase of the floating body 24 potential over the time during which the write operation is carried out (write operation time). It has been determined according to the present invention that a floating body 24 potential increase of VFB/3 is low enough to suppress the floating body 24 potential increase. A positive voltage can be applied to SL terminal 72 to further reduce the undesired write “0” disturb on other memory cells 150 in the memory array. The unselected cells will remain at holding state, i.e. zero or negative voltage applied to WL terminal 70 and zero voltage applied to BL terminal 74. The unselected cells 150 not sharing the same WL or BL terminal as the selected cell 150 will remain at holding state, i.e., with zero or negative voltage applied to unselected WL terminal and zero voltage applied to unselected BL terminal 74.
In one particular non-limiting embodiment, for the selected cell 150 a potential of about 0.0 volts is applied to terminal 72, a potential of about −0.2 volts is applied to terminal 74, a potential of about +0.5 volts is applied to terminal 70, about +1.2 volts is applied to terminal 76, and about 0.0 volts is applied to terminal 78. For the unselected cells not sharing the same WL terminal or BL terminal with the selected memory cell 50, about 0.0 volts is applied to terminal 72, about 0.0 volts is applied to terminal 74, about 0.0 volts is applied to terminal 70, about +1.2 volts is applied to terminal 76, and about 0.0 volts is applied to terminal 78.
An example of the bias conditions applied to a selected memory cell 150 during a write “0” operation is illustrated in
During the write “0” operation (individual bit write “0” operation described above) in memory cell 150, the positive back bias applied to the BW terminal 76 of the memory cells 150 is necessary to maintain the states of the unselected cells 150, especially those sharing the same row or column as the selected cell 150a, as the bias condition can potentially alter the states of the memory cells 150 without the intrinsic bipolar device 130 (formed by buried well region 22, floating body 24, and regions 16, 18) re-establishing the equilibrium condition. Furthermore, the holding operation does not interrupt the write “0” operation of the memory cells 150.
A write “1” operation can be performed on memory cell 150 through an impact ionization mechanism or a band-to-band tunneling mechanism, as described for example in “A Design of a Capacitorless 1T-DRAM Cell Using Gate-Induced Drain Leakage (GIDL) Current for Low-power and High-speed Embedded Memory”, Yoshida et al., pp. 913-918, International Electron Devices Meeting, 2003, which was incorporated by reference above.
An example of bias conditions applied to selected memory cell 150a under a band-to-band tunneling write “1” operation is further elaborated and is shown in
A multi-level operation can also be performed on memory cell 150. A holding operation to maintain the multi-level states of memory cell 50 is described with reference to
A multi-level write operation without alternate write and read operations on memory cell 150 is now described. To perform this operation, zero voltage is applied to SL terminal 72, a positive voltage is applied to WL terminal 70, a positive voltage (back bias) is applied to BW terminal 76, and zero voltage is applied to substrate terminal 78, while the voltage of BL terminal 74 is ramped up. These bias conditions will result in a hole injection to the floating body 24 through an impact ionization mechanism. The state of the memory cell 150 can be simultaneously read for example by monitoring the change in the cell current through a read circuitry 90 coupled to the source line 72. The cell current measured in the source line direction (where source line current equals bit line current plus BW current and the currents are measured in the directions from buried well to source line and from bit line to source line) is a cumulative cell current of all memory cells 150 which share the same source line 72 (e.g. see
The applied bias conditions will result in hole injection to floating body 24 through an impact ionization mechanism.
In a similar manner, the multi-level write operation using impact ionization mechanism can also be performed by ramping the write current applied to BL terminal 74 instead of ramping the BL terminal 74 voltage.
In yet another embodiment, a multi-level write operation can be performed through a band-to-band tunneling mechanism by ramping the voltage applied to BL terminal 74, while applying zero voltage to SL terminal 72, a negative voltage to WL terminal 70, a positive voltage to BW terminal 76, and zero voltage to substrate terminal 78. The potential of the floating body 24 will increase as a result of the band-to-band tunneling mechanism. The state of the memory cell 50 can be simultaneously read for example by monitoring the change in the cell current through a read circuitry 90 coupled to the source line 72. Once the change in the cell current reaches the desired level associated with a state of the memory cell, the voltage applied to BL terminal 74 can be removed. If positive voltage is applied to substrate terminal 78, the resulting floating body 24 potential is maintained through base hole current flowing into floating body 24. In this manner, the multi-level write operation can be performed without alternate write and read operations.
Similarly, the multi-level write operation using band-to-band tunneling mechanism can also be performed by ramping the write current applied to BL terminal 74 instead of ramping the voltage applied to BL terminal 74.
Similarly, a read while programming operation can be performed by monitoring the change in cell current in the bit line 74 direction (where bit line current equals SL current plus BW current) through a reading circuitry 90 coupled to the bit line 74, for example as shown in
Another embodiment of memory cell 150 operations, which utilizes the silicon controlled rectifier (SCR) principle has been disclosed in U.S. patent application Ser. No. 12/533,661, filed Jul. 31, 2009, which was incorporated by reference, in its entirety, above.
Memory cell device 50 further includes gates 60 on two opposite sides of the floating substrate region 24 as shown in
Device 50 includes several terminals: word line (WL) terminal 70, source line (SL) terminal 72, bit line (BL) terminal 74, and substrate terminal 78. Terminal 70 is connected to the gate 60. Terminal 72 is connected to first region 16 and terminal 74 is connected to second region 18. Alternatively, terminal 72 can be connected to second region 18 and terminal 74 can be connected to first region 16. Terminal 78 is connected to substrate 12.
Memory cell device 150 further includes gates 60 on two opposite sides of the floating substrate region 24 as shown in
Device 150 includes several terminals: word line (WL) terminal 70, source line (SL) terminal 72, bit line (BL) terminal 74, buried well (BW) terminal 76 and substrate terminal 78. Terminal 70 is connected to the gate 60. Terminal 72 is connected to first region 16 and terminal 74 is connected to second region 18. Alternatively, terminal 72 can be connected to second region 18 and terminal 74 can be connected to first region 16. Terminal 76 is connected to buried layer 22 and terminal 78 is connected to substrate 12.
From the foregoing it can be seen that with the present invention, a semiconductor memory with electrically floating body is achieved. The present invention also provides the capability of maintaining memory states or parallel non-algorithmic periodic refresh operations. As a result, memory operations can be performed in an uninterrupted manner. While the foregoing written description of the invention enables one of ordinary skill to make and use what is considered presently to be the best mode thereof, those of ordinary skill will understand and appreciate the existence of variations, combinations, and equivalents of the specific embodiment, method, and examples herein. The invention should therefore not be limited by the above described embodiment, method, and examples, but by all embodiments and methods within the scope and spirit of the invention as claimed.
This application is a continuation of co-pending application Ser. No. 16/574,069, filed Sep. 17, 2019, which is a continuation of application Ser. No. 16/404,964, filed May 7, 2019, now U.S. Pat. No. 10,453,847, which is a continuation of application Ser. No. 16/200,997, filed Nov. 27, 2018, now U.S. Pat. No. 10,340,276, which is a continuation of application Ser. No. 16/017,692, filed Jun. 25, 2018, now U.S. Pat. No. 10,163,907, which is a continuation of application Ser. No. 15/701,187, filed Sep. 11, 2017, now U.S. Pat. No. 8,208,302, which is a continuation of application Ser. No. 15/485,011, filed Apr. 11, 2017, now U.S. Pat. No. 9,793,277, which is a continuation of application Ser. No. 15/347,048, filed Nov. 9, 2016, now U.S. Pat. No. 9,653,467, which is a continuation of application Ser. No. 14/956,253, filed Dec. 1, 2015, now U.S. Pat. No. 9,514,803, which is a continuation of application Ser. No. 14/688,122, filed Apr. 16, 2015, now U.S. Pat. No. 9,236,382, which is a continuation of application Ser. No. 14/448,757, filed Jul. 31, 2014, now U.S. Pat. No. 9,030,872, which is a continuation of application Ser. No. 13/941,475, filed Jul. 13, 2013, now U.S. Pat. No. 8,937,834, which is a continuation of application Ser. No. 13/478,014, filed May 22, 2012, now U.S. Pat. No. 8,514,623, which is a continuation of application Ser. No. 13/244,855, filed Sep. 26, 2011, now U.S. Pat. No. 8,208,302, which is a continuation of application Ser. No. 12/797,334, filed Jun. 9, 2010, now U.S. Pat. No. 8,130,547, and which claims the benefit of U.S. Provisional Application No. 61/309,589, filed Mar. 2, 2010. We hereby incorporate all of the aforementioned applications and patents herein, in their entireties, by reference thereto, and we claim priority to application Ser. Nos. 16/574,069; 16/404,964; 16/200,997; 16/017,692; 15/701,187; 15/485,011; 15/347,048; 14/956,253; 14/688,122; 14/448,757; 13/941,475; 13/478,014; 13/244,855; and 12/797,334 under 35 USC § 120, and to Application Ser. No. 61/309,589 under 35 USC § 119. This application claims the benefit of U.S. Provisional Application No. 61/309,589, filed Mar. 2, 2010, which application is hereby incorporated herein, in its entirety, by reference thereto and to which application we claim priority under 35 U.S.C. Section 119. This application also hereby incorporates, in its entirety by reference thereto, (application Ser. No. 12/797,320), filed concurrently herewith and titled “Semiconductor Memory Having Electrically Floating Body Transistor”.
| Number | Name | Date | Kind |
|---|---|---|---|
| 4003076 | Polata et al. | Jan 1977 | A |
| 4126899 | Lohstroh et al. | Nov 1978 | A |
| 4300212 | Simko | Nov 1981 | A |
| 4385308 | Uchida | May 1983 | A |
| 4393481 | Owen et al. | Jul 1983 | A |
| 4404662 | Masenas, Jr. | Sep 1983 | A |
| 4480318 | Chong | Oct 1984 | A |
| 4521873 | Heuber et al. | Jun 1985 | A |
| 4536858 | Ueno | Aug 1985 | A |
| 4611303 | Kitano | Sep 1986 | A |
| 4651302 | Kimmel et al. | Mar 1987 | A |
| 4821236 | Hayashi et al. | Apr 1989 | A |
| 4841484 | Watanabe et al. | Jun 1989 | A |
| 4959812 | Momodomi et al. | Sep 1990 | A |
| 4984211 | Tran | Jan 1991 | A |
| 5091879 | Tran | Feb 1992 | A |
| 5350938 | Matsukawa et al. | Sep 1994 | A |
| 5371703 | Miyamoto | Dec 1994 | A |
| 5410507 | Tazunoki et al. | Apr 1995 | A |
| 5465249 | Cooper, Jr. et al. | Nov 1995 | A |
| 5485425 | Iwai et al. | Jan 1996 | A |
| 5511022 | Yim et al. | Apr 1996 | A |
| 5519831 | Holzhammer | May 1996 | A |
| 5581504 | Chang et al. | Dec 1996 | A |
| 5670906 | Roohparvar | Sep 1997 | A |
| 5734616 | Kazama et al. | Mar 1998 | A |
| 5767549 | Chen et al. | Jun 1998 | A |
| 5877978 | Morishita et al. | Mar 1999 | A |
| 5896313 | Kao et al. | Apr 1999 | A |
| 5999444 | Fujiwara et al. | Dec 1999 | A |
| 6005818 | Ferrant | Dec 1999 | A |
| 6064100 | Wen | May 2000 | A |
| 6141248 | Forbes et al. | Oct 2000 | A |
| 6163048 | Hirose et al. | Dec 2000 | A |
| 6166407 | Ohta | Dec 2000 | A |
| 6337824 | Kono et al. | Jan 2002 | B1 |
| 6341087 | Kunikyo | Jan 2002 | B1 |
| 6356485 | Proebsting | Mar 2002 | B1 |
| 6373325 | Kuriyama | Apr 2002 | B1 |
| 6376876 | Shin et al. | Apr 2002 | B1 |
| 6542411 | Tanikawa et al. | Apr 2003 | B2 |
| 6614684 | Shukuri et al. | Sep 2003 | B1 |
| 6686624 | Hsu | Feb 2004 | B2 |
| 6724657 | Shukuri et al. | Apr 2004 | B2 |
| 6734490 | Esseni et al. | May 2004 | B2 |
| 6791882 | Seki et al. | Sep 2004 | B2 |
| 6801452 | Miwa et al. | Oct 2004 | B2 |
| 6849501 | Rudeck | Feb 2005 | B2 |
| 6870751 | Van Brocklin et al. | Mar 2005 | B2 |
| 6885581 | Nemati et al. | Apr 2005 | B2 |
| 6913964 | Hsu | Jul 2005 | B2 |
| 6925006 | Fazan et al. | Aug 2005 | B2 |
| 6954377 | Choi et al. | Oct 2005 | B2 |
| 6969662 | Fazan et al. | Nov 2005 | B2 |
| 7085156 | Ferrant et al. | Aug 2006 | B2 |
| 7118986 | Steigerwalt et al. | Oct 2006 | B2 |
| 7170807 | Fazan et al. | Jan 2007 | B2 |
| 7224019 | Hieda et al. | May 2007 | B2 |
| 7259420 | Anderson et al. | Aug 2007 | B2 |
| 7259992 | Shirota | Aug 2007 | B2 |
| 7285820 | Park et al. | Oct 2007 | B2 |
| 7301803 | Okhonin et al. | Nov 2007 | B2 |
| 7329580 | Cho et al. | Feb 2008 | B2 |
| 7440333 | Hsia et al. | Oct 2008 | B2 |
| 7447068 | Tsai et al. | Nov 2008 | B2 |
| 7450423 | Lai et al. | Nov 2008 | B2 |
| 7473611 | Cho et al. | Jan 2009 | B2 |
| 7504302 | Matthew et al. | Mar 2009 | B2 |
| 7541636 | Ranica et al. | Jun 2009 | B2 |
| 7542345 | Okhonin et al. | Jun 2009 | B2 |
| 7579241 | Hieda et al. | Aug 2009 | B2 |
| 7609551 | Shino et al. | Oct 2009 | B2 |
| 7622761 | Park et al. | Nov 2009 | B2 |
| 7633801 | Hanafi et al. | Dec 2009 | B2 |
| 7701763 | Roohparvar | Apr 2010 | B2 |
| 7733693 | Ferrant et al. | Jun 2010 | B2 |
| 7759715 | Bhattacharyya | Jul 2010 | B2 |
| 7760548 | Widjaja | Jul 2010 | B2 |
| 7847338 | Widjaja | Dec 2010 | B2 |
| 7924630 | Carman | Apr 2011 | B2 |
| 7933140 | Wang et al. | Apr 2011 | B2 |
| 8014200 | Widjaja | Sep 2011 | B2 |
| 8036033 | Widjaja | Oct 2011 | B2 |
| 8059459 | Widjaja | Nov 2011 | B2 |
| 8077536 | Widjaja et al. | Dec 2011 | B2 |
| 8130547 | Widjaja | Mar 2012 | B2 |
| 8130548 | Widjaja et al. | Mar 2012 | B2 |
| 8159878 | Widjaja | Apr 2012 | B2 |
| 8174886 | Widjaja et al. | May 2012 | B2 |
| 8194451 | Widjaja | Jun 2012 | B2 |
| 8208302 | Widjaja | Jun 2012 | B2 |
| 8243499 | Widjaja | Aug 2012 | B2 |
| 8294193 | Widjaja | Oct 2012 | B2 |
| 8305803 | Mazure et al. | Nov 2012 | B2 |
| 8379458 | Or-Bach et al. | Feb 2013 | B1 |
| 8514623 | Widjaja et al. | Aug 2013 | B2 |
| 8531881 | Widjaja | Sep 2013 | B2 |
| 8559257 | Widjaja | Oct 2013 | B2 |
| 8570803 | Widjaja | Oct 2013 | B2 |
| 8654583 | Widjaja | Feb 2014 | B2 |
| 8787085 | Widjaja | Jul 2014 | B2 |
| 8837247 | Widjaja | Sep 2014 | B2 |
| 8902663 | Or-Bach et al. | Dec 2014 | B1 |
| 8923052 | Widjaja | Dec 2014 | B2 |
| 8937834 | Widjaja et al. | Jan 2015 | B2 |
| 8995186 | Widjaja | Mar 2015 | B2 |
| 9030872 | Widjaja et al. | May 2015 | B2 |
| 9087580 | Widjaja | Jul 2015 | B2 |
| 9117749 | Or-Bach | Aug 2015 | B1 |
| 9153309 | Widjaja et al. | Oct 2015 | B2 |
| 9153333 | Widjaja | Oct 2015 | B2 |
| 9218864 | Yi et al. | Dec 2015 | B1 |
| 9230965 | Widjaja | Jan 2016 | B2 |
| 9236382 | Widjaja et al. | Jan 2016 | B2 |
| 9257179 | Widjaja | Feb 2016 | B2 |
| 9460790 | Widjaja | Oct 2016 | B2 |
| 9484082 | Widjaja | Nov 2016 | B2 |
| 9490012 | Widjaja | Nov 2016 | B2 |
| 9514803 | Widjaja et al. | Dec 2016 | B2 |
| 9614080 | Widjaja | Apr 2017 | B2 |
| 9646693 | Widjaja | May 2017 | B2 |
| 9653467 | Widjaja et al. | May 2017 | B2 |
| 9679648 | Widjaja | Jun 2017 | B2 |
| 9715932 | Widjaja | Jul 2017 | B2 |
| 9747983 | Widjaja | Aug 2017 | B2 |
| 9761311 | Widjaja | Sep 2017 | B2 |
| 9761589 | Widjaja | Sep 2017 | B2 |
| 9793277 | Widjaja et al. | Oct 2017 | B2 |
| 9812203 | Widjaja | Nov 2017 | B2 |
| 9847131 | Widjaja | Dec 2017 | B2 |
| 9928910 | Widjaja | Mar 2018 | B2 |
| 9960166 | Widjaja | May 2018 | B2 |
| 9978450 | Widjaja | May 2018 | B2 |
| 10008266 | Widjaja | Jun 2018 | B1 |
| 10032514 | Widjaja | Jul 2018 | B2 |
| 10032776 | Widjaja et al. | Jul 2018 | B2 |
| 10109349 | Widjaja | Oct 2018 | B2 |
| 10163907 | Widjaja et al. | Dec 2018 | B2 |
| 10204684 | Widjaja | Feb 2019 | B2 |
| 10210934 | Widjaja | Feb 2019 | B2 |
| 10211209 | Widjaja | Feb 2019 | B2 |
| 10242739 | Widjaja | Mar 2019 | B2 |
| 10340006 | Widjaja | Jul 2019 | B2 |
| 10340276 | Widjaja et al. | Jul 2019 | B2 |
| 10388378 | Widjaja | Aug 2019 | B2 |
| 10403361 | Widjaja | Sep 2019 | B2 |
| 10453847 | Widjaja et al. | Oct 2019 | B2 |
| 10468102 | Widjaja | Nov 2019 | B2 |
| 10497443 | Widjaja | Dec 2019 | B2 |
| 10553281 | Widjaja | Feb 2020 | B2 |
| 20020018366 | Schwerin et al. | Feb 2002 | A1 |
| 20020033499 | Esseni et al. | Mar 2002 | A1 |
| 20020054514 | Kajigaya et al. | May 2002 | A1 |
| 20020097603 | Tanaka et al. | Jul 2002 | A1 |
| 20020176303 | Shore | Nov 2002 | A1 |
| 20030168680 | Hsu | Sep 2003 | A1 |
| 20040104407 | Hsu et al. | Jun 2004 | A1 |
| 20040223392 | Ikehashi | Nov 2004 | A1 |
| 20040228168 | Ferrant et al. | Nov 2004 | A1 |
| 20050002219 | Choi et al. | Jan 2005 | A1 |
| 20050024968 | Lee et al. | Feb 2005 | A1 |
| 20050032313 | Forbes | Feb 2005 | A1 |
| 20050110073 | Spadea | May 2005 | A1 |
| 20050124120 | Du et al. | Jun 2005 | A1 |
| 20060044915 | Park et al. | Mar 2006 | A1 |
| 20060046408 | Ohsawa | Mar 2006 | A1 |
| 20060056234 | Lowrey | Mar 2006 | A1 |
| 20060125010 | Bhattacharyya | Jun 2006 | A1 |
| 20060146606 | Bhattacharyya et al. | Jul 2006 | A1 |
| 20060157679 | Scheuerlein | Jul 2006 | A1 |
| 20060193174 | Choi et al. | Aug 2006 | A1 |
| 20060227601 | Bhattacharyya | Oct 2006 | A1 |
| 20060237770 | Huang et al. | Oct 2006 | A1 |
| 20060278915 | Lee et al. | Dec 2006 | A1 |
| 20070004149 | Tews | Jan 2007 | A1 |
| 20070090443 | Choi et al. | Apr 2007 | A1 |
| 20070133259 | Kim | Jun 2007 | A1 |
| 20070164351 | Hamamoto | Jul 2007 | A1 |
| 20070164352 | Padilla | Jul 2007 | A1 |
| 20070183191 | Kim | Aug 2007 | A1 |
| 20070210338 | Orlowski | Sep 2007 | A1 |
| 20070211535 | Kim | Sep 2007 | A1 |
| 20070215954 | Mouli | Sep 2007 | A1 |
| 20070284648 | Park et al. | Dec 2007 | A1 |
| 20080048239 | Huo et al. | Feb 2008 | A1 |
| 20080056010 | Horch | Mar 2008 | A1 |
| 20080080248 | Lue et al. | Apr 2008 | A1 |
| 20080111154 | Voldman | May 2008 | A1 |
| 20080123418 | Widjaja | May 2008 | A1 |
| 20080180995 | Okhonin | Jul 2008 | A1 |
| 20080224202 | Young et al. | Sep 2008 | A1 |
| 20080265305 | He et al. | Oct 2008 | A1 |
| 20080303079 | Cho et al. | Dec 2008 | A1 |
| 20080316828 | Hanafi et al. | Dec 2008 | A1 |
| 20090016101 | Okhonin | Jan 2009 | A1 |
| 20090020754 | Suryagandh et al. | Jan 2009 | A1 |
| 20090034320 | Ueda | Feb 2009 | A1 |
| 20090065853 | Hanafi | Mar 2009 | A1 |
| 20090081835 | Kim et al. | Mar 2009 | A1 |
| 20090085089 | Chang et al. | Apr 2009 | A1 |
| 20090108322 | Widjaja | Apr 2009 | A1 |
| 20090108351 | Yang et al. | Apr 2009 | A1 |
| 20090109750 | Widjaja | Apr 2009 | A1 |
| 20090140317 | Rosmeulen | Jun 2009 | A1 |
| 20090173983 | Kusunoki et al. | Jul 2009 | A1 |
| 20090173985 | Lee et al. | Jul 2009 | A1 |
| 20090190402 | Hsu et al. | Jul 2009 | A1 |
| 20090201723 | Okhonin et al. | Aug 2009 | A1 |
| 20090230447 | Hwang | Sep 2009 | A1 |
| 20090242996 | Van Bentrum et al. | Oct 2009 | A1 |
| 20090251966 | Widjaja | Oct 2009 | A1 |
| 20090316492 | Widjaja | Dec 2009 | A1 |
| 20100008139 | Bae | Jan 2010 | A1 |
| 20100034041 | Widjaja | Feb 2010 | A1 |
| 20100046287 | Widjaja | Feb 2010 | A1 |
| 20100046310 | Joo et al. | Feb 2010 | A1 |
| 20100096701 | Yoo | Apr 2010 | A1 |
| 20100149882 | Shum et al. | Jun 2010 | A1 |
| 20100149886 | Song | Jun 2010 | A1 |
| 20100157664 | Chung | Jun 2010 | A1 |
| 20100202202 | Roohparvar | Aug 2010 | A1 |
| 20100246277 | Widjaja | Sep 2010 | A1 |
| 20100246284 | Widjaja | Sep 2010 | A1 |
| 20110007578 | Okhonin et al. | Jan 2011 | A1 |
| 20110032756 | Widjaja | Feb 2011 | A1 |
| 20110042736 | Widjaja | Feb 2011 | A1 |
| 20110044110 | Widjaja | Feb 2011 | A1 |
| 20110211399 | Son et al. | Sep 2011 | A1 |
| 20110228591 | Widjaja | Sep 2011 | A1 |
| 20110305085 | Widjaja | Dec 2011 | A1 |
| 20120012915 | Widjaja et al. | Jan 2012 | A1 |
| 20120014180 | Widjaja | Jan 2012 | A1 |
| 20120014188 | Widjaja et al. | Jan 2012 | A1 |
| 20120069652 | Widjaja | Mar 2012 | A1 |
| 20120106234 | Widjaja | May 2012 | A1 |
| 20120113712 | Widjaja | May 2012 | A1 |
| 20120120752 | Widjaja | May 2012 | A1 |
| 20120129301 | Or-Bach et al. | May 2012 | A1 |
| 20120217549 | Widjaja | Aug 2012 | A1 |
| 20120230123 | Widjaja et al. | Sep 2012 | A1 |
| 20130015517 | Widjaja et al. | Jan 2013 | A1 |
| 20130148422 | Widjaja | Jun 2013 | A1 |
| 20130250685 | Widjaja | Sep 2013 | A1 |
| 20130292635 | Widjaja | Nov 2013 | A1 |
| 20140021549 | Widjaja | Jan 2014 | A1 |
| 20140085981 | Takeuchi | Mar 2014 | A1 |
| 20140160868 | Widjaja et al. | Jun 2014 | A1 |
| 20140332899 | Widjaja | Nov 2014 | A1 |
| 20140340972 | Widjaja et al. | Nov 2014 | A1 |
| 20140355343 | Widjaja | Dec 2014 | A1 |
| 20150109860 | Widjaja | Apr 2015 | A1 |
| 20150170743 | Widjaja | Jun 2015 | A1 |
| 20150221650 | Widjaja et al. | Aug 2015 | A1 |
| 20150310917 | Widjaja | Oct 2015 | A1 |
| 20150371707 | Widjaja | Dec 2015 | A1 |
| 20160005750 | Widjaja | Jan 2016 | A1 |
| 20160078921 | Widjaja et al. | Mar 2016 | A1 |
| 20160086655 | Widjaja | Mar 2016 | A1 |
| 20160111158 | Widjaja | Apr 2016 | A1 |
| 20160365444 | Widjaja | Dec 2016 | A1 |
| 20170025534 | Widjaja | Jan 2017 | A1 |
| 20170032842 | Widjaja | Feb 2017 | A1 |
| 20170040326 | Widjaja | Feb 2017 | A1 |
| 20170053919 | Widjaja et al. | Feb 2017 | A1 |
| 20170092648 | Widjaja | Mar 2017 | A1 |
| 20170133091 | Widjaja | May 2017 | A1 |
| 20170169887 | Widjaja | Jun 2017 | A1 |
| 20170213593 | Widjaja | Jul 2017 | A1 |
| 20170221900 | Widjaja et al. | Aug 2017 | A1 |
| 20170294230 | Widjaja | Oct 2017 | A1 |
| 20170365340 | Widjaja | Dec 2017 | A1 |
| 20170365607 | Widjaja | Dec 2017 | A1 |
| 20180012893 | Widjaja et al. | Jan 2018 | A1 |
| 20180025780 | Widjaja | Jan 2018 | A1 |
| 20180075907 | Widjaja | Mar 2018 | A1 |
| 20180174654 | Widjaja | Jun 2018 | A1 |
| 20180182458 | Widjaja | Jun 2018 | A1 |
| 20180219013 | Widjaja | Aug 2018 | A1 |
| 20180233199 | Widjaja | Aug 2018 | A1 |
| 20180301191 | Widjaja | Oct 2018 | A1 |
| 20180308848 | Widjaja et al. | Oct 2018 | A1 |
| 20180330790 | Widjaja | Nov 2018 | A1 |
| 20190027220 | Widjaja | Jan 2019 | A1 |
| 20190043554 | Widjaja et al. | Feb 2019 | A1 |
| 20190096889 | Widjaja et al. | Mar 2019 | A1 |
| 20190156889 | Widjaja | May 2019 | A1 |
| 20190156890 | Widjaja | May 2019 | A1 |
| 20190164974 | Widjaja | May 2019 | A1 |
| 20190189212 | Widjaja | Jun 2019 | A1 |
| 20190259763 | Widjaja et al. | Aug 2019 | A1 |
| 20190267089 | Widjaja | Aug 2019 | A1 |
| 20190295646 | Widjaja | Sep 2019 | A1 |
| 20190355419 | Widjaja | Nov 2019 | A1 |
| 20200013781 | Widjaja et al. | Jan 2020 | A1 |
| 20200051633 | Widjaja | Feb 2020 | A1 |
| Entry |
|---|
| Almeida, et al., “Comparison between low and high read bias in FB-RAM on UTBOX FDSOI devices”, Ultimate Integration on Silicon (ULIS), 2012 13th International Conference on, Mar. 6, 2012, pp. 61-64. |
| Andrade, et al., “The Impact of Back Bias on the Floating Body Effect in UTBOX SOI Devices for 1T-FBRAM Memory Applications”, Devices, Circuits and Systems (ICCDCS), 2012 8th International Caribbean Conference on. IEEE, 2012, pp. 1-4. |
| Aoulaiche, et al. “Junction Field Effect on the Retention Time for One-Transistor Floating-Body RAM.” Electron Devices, IEEE Transactions on, vol. 59, No. 8, 2012, pp. 2167-2172. |
| Aoulaiche, et al. “Hot hole induced damage in 1T-FBRAM on bulk FinFET.” Reliability Physics Symposium (IRPS), 2011 IEEE International. IEEE, 2011, pp. 99-104. |
| Avci, et al. “Floating-Body Diode—A Novel DRAM Device.” Electron Device Letters, IEEE, vol. 33, No. 2, 2012, pp. 161-163. |
| Bawedin, et al., “Floating-Body SOI Memory: Concepts, Physics, and Challenges”, ECS Transactions 19.4 (2009), pp. 243-256. |
| Ban, et al. “Integration of Back-Gate doping for 15-nm node floating body cell (FBC) memory.” VLSI Technology (VLSIT), 2010 Symposium on. IEEE, 2010, pp. 159-160. |
| Cho, et al. “Variation-aware study of BJT-based capacitorless DRAM cell scaling limit.” Silicon Nanoelectronics Workshop (SNW), 2012 IEEE. IEEE, 2012, pp. 1-2. |
| Cho, et al. “Variation Study and Implications for BJT-Based Thin-Body Capacitorless DRAM.” Electron Device Letters, IEEE, vol. 33, No. 3, 2012, pp. 312-314. |
| Chiu, et al. “Characteristics of a new trench-oxide thin-film transistor and its 1T-DRAM applications.” Solid-State and Integrated Circuit Technology (ICSICT), 2010 10th IEEE International Conference on. IEEE, 2010, pp. 1106-1108. |
| Chiu, et al. “A simple process of thin-film transistor using the trench-oxide layer for improving 1T-DRAM performance.” Next-Generation Electronics (ISNE), 2010 International Symposium on. IEEE, 2010, pp. 254-257. |
| Chun, et al. “A 1.1 V, 667MHz random cycle, asymmetric 2T gain cell embedded Dram with a 99.9 percentile retention time of 110μsec.” VLSI Circuits (VLSIC), 2010 IEEE Symposium on. IEEE, 2010, pp. 191-192. |
| Chun, et al. “A 667 MHz Logic-Compatible Embedded Dram Featuring an Asymmetric 2T Gain Cell for High Speed On-Die Caches.” Solid-State Circuits, IEEE Journal of, vol. 47, No. 2, 2012, pp. 547-559. |
| Cao, et al. “A Novel 1T-1D DRAM Cell for Embedded Application.” Electron Devices, IEEE Transactions on, vol. 59, No. 5, 2012, pp. 1304-1310. |
| Collaert, et al. “Substrate bias dependency of sense margin and retention in bulk FinFET 1T-DRAM cells.” Solid-State Electronics 65 (2011, pp. 205-210. |
| Collaert, et al. “A low-voltage biasing scheme for aggressively scaled bulk FinFET 1T-DRAM featuring 10s retention at 85 C” VLSI Technology (VLSIT), 2010 Symposium on. IEEE, 2010, pp. 161-162. |
| Chatterjee, et al. “Taper isolated dynamic gain RAM cell.” Electron Devices Meeting, 1978 International. vol. 24. IEEE, 1978, pp. 698-699. |
| Chatterjee, et al. Circuit Optimization of the Paper Isolated Dynamic Gain Ram Cell for VLSI Memories, pp. 22-23, 1979. |
| Chatterjee, et al. “A survey of high-density dynamic RAM cell concepts.” Electron Devices, IEEE Transactions on 26.6 (1979): 827-839. |
| Erb, D. “Stratified charge memory.” Solid-State Circuits Conference. Digest of Technical Papers. 1978 IEEE International. vol. 21. IEEE, 1978, pp. 24-25. |
| Galeti, M., et al. “BJT effect analysis in p-and n-SOI MuGFETs with high-k gate dielectrics and TiN metal gate electrode for a 1T-DRAM application.” SOI Conference (SOI), 2011 IEEE International. IEEE, 2011, pp. 1-2. |
| Gamiz, et al. “3D Trigate 1T-DRAM Memory Cell for 2x nm Nodes.” Memory Workshop (IMW), 2012 4th IEEE International. IEEE, 2012, pp. 1-4. |
| Gamiz, et al. “A 20nm low-power triple-gate multibody 1T-DRAM cell.” VLSI Technology, Systems, and Applications (VLSI-TSA), 2012 International Symposium on. IEEE, 2012, pp. 1-2. |
| Giusi, et al. “Bipolar mode operation and scalability of double-gate capacitorless 1T-DRAM cells.” Electron Devices, IEEE Transactions on, vol. 57, No. 8 (2010), pp. 1743-1750. |
| Gupta, et al. “32nm high-density high-speed T-RAM embedded memory technology.” Electron Devices Meeting (IEDM), 2010 IEEE International. IEEE, 2010, pp. 12-1. |
| Han, et al. “Bistable resistor (biristor)-gateless silicon nanowire memory.” Vlsi Technology (VLSIT), 2010 Symposium on. IEEE, 2010, pp. 171-172. |
| Han, et al. “Biristor—Bistable resistor based on a silicon nanowire.” Electron Device Letters, IEEE 31.8 (2010): 797-799. |
| Hubert, et al., “Experimental comparison of programming mechanisms in 1T-DRAM cells with variable channel length”, Solid-State Device Research Conference (ESSDERC), 2010 Proceedings of the European, pp. 150-153, Sep. 14-16, 2010. |
| Hwang, et al. “Offset buried metal gate vertical floating body memory technology with excellent retention time for DRAM application.” VLSI Technology (VLSIT), 2011 Symposium on. IEEE, 2011, pp. 172-173. |
| Kim, et al. “Investigation of 1T DRAM cell with non-overlap structure and recessed channel.” Silicon Nanoelectronics Norkshop (SNW), 2010. IEEE, 2010, pp. 1-2. |
| Kim, et al. “Optical charge-pumping: A universal trap characterization technique for nanoscale floating body devices.” VLSI Technology (VLSIT), 2011 Symposium on. IEEE, 2011, pp. 190-191. |
| Leiss et al, “dRAM Design Using the Taper-Isolated Dynamic RAM Cell.” Solid-State Circuits, IEEE Journal of 17.2 (1982): 337-344. |
| Lee' et al.“A Novel Capacitorless 1T DRAM Cell for Data Retention Time Improvement.” Nanotechnology, IEEE Transactions on, vol. 10, No. 3, 2011, pp. 462-466. |
| Lu, et al., “A Simplified Superior Floating-Body/Gate DRAM Cell”, IEEE Elec. Dev. Letters, vol. 30, No. 3, Mar. 2009, pp. 282-284. |
| Lu, et al., “A Floating-Body/Gate DRAM Cell Upgraded for Long Retention Time”, IEEE Elec. Dev. Letters, vol. 32, No. 6, pp. 731-733, Jun. 2011. |
| Liu, Xuelian, et al. “A three-dimensional DRAM using floating body cell in FDSOI devices.” Design and Diagnostics of Electronic Circuits & Systems (DDECS), 2012 IEEE 15th International Symposium on. IEEE, 2012, pp. 159-162. |
| Lin, et al., A new 1T DRAM Cell with enhanced Floating Body Effect, pp. 1-5, 2006. |
| Lanyon, et al., “Bandgap Narrowing in Moderately to Heavily Doped Silicon”, ppl 1014-1018, No. 7, vol. ED-26, 1979. |
| Mahatme, et al. “Total ionizing dose effects on ultra thin buried oxide floating body memories.” Reliability Physics Symposium (IRPS), 2012 IEEE International, 2012, pp. 1-5. |
| Moon, et al. “Fin-width dependence of BJT-based 1T-DRAM implemented on FinFET.” Electron Device Letters, vol. 31, No. 9 (2010): 909-911. |
| Moon, et al. “An optically assisted program method for capacitorless 1T-DRAM.” Electron Devices, IEEE Transactions on, vol. 57, No. 7, 2010, pp. 1714-1718. |
| Moon, et al. “Multi-functional universal device using a band-engineered vertical structure.” Electron Devices Meeting (IEDM), 2011 IEEE International. IEEE, 2011, pp. 24-6. |
| Moon, et al. “Ultimately scaled 20nm unified-RAM.” Electron Devices Meeting (IEDM), 2010 IEEE International. IEEE, 2010, pp. 12-2. |
| Nicoletti, et al. “The Dependence of Retention Time on Gate Length in UTBOX FBRAM With Different Source/Drain Junction Engineering.” Electron Device Letters, vol. 33, No. 7, 2012, pp. 940-942. |
| Ohsawa, et al, “A Novel Capacitor-less DRAM Cell: Floating Body Cell”, CRC Press, Taylor & Francis Group, 2012, pp.- 1-7-. |
| Ohsawa, et al. Autonomous refresh of floating body cell (FBC). IEEE, 2008, pp. 801-804. |
| Ohsawa, et al. Autonomous refresh of floating-body cell due to Current Anomaly of Impact Ionization, IEEE Transactions on Electron Devices, vol. 56 No. 10, 2009, pp. 2302-2311. |
| Pulicani, R., et al. “Simulation of intrinsic bipolar transistor mechanisms for future capacitor-less eDRAM on bulk substrate.” Electronics, Circuits, and Systems (ICECS), 2010 17th IEEE International Conference on. IEEE, 2010, pp. 366-969. |
| Ranica, et al. “Scaled It-Bulk devices built with CMOS 90nm technology for low-cost eDRAM applications.” Vlsi Technology, 2005. Digest of Technical Papers. 2005 Symposium on. IEEE, 2005, pp. 38-39. |
| Ranica, et al., a one transistor cell on bulk substrate (1T-Bulk) for low-cost and high density eDRAM. VLSI Technology, 2004, pp. 128-129. |
| Rodriguez et al., “A-RAM: Novel capcitor-less DRAM memory.” in SOI Conference, 2009 IEEE International, pp. 1-2, IEEE, 2009. |
| Rodriguez et al., “Novel capacitorless 1T-DRAM cell for 22-nm node compatible with bulk and SOI substrates.” Electron devices, IEEE Transactions on Electron Devices, vol. 58, No. 8 (2011), pp. 2371-2377. |
| Rodriguez et al., “A-RAM memory cell: concept and operation.” Electron Device Letters, IEEE, vol. 31, No. 9 (2010), pp. 972-974. |
| Romanjek et al., “Compact (Wg/Lg+80/85nm) FDSOI 1T-DRAM programmed by Meta Stable Dip”, Ultimate Integration on Silicon (ULIS), 2012 13th International Conference on, Mar. 6, 2012, pp. 199-202. |
| Rothemund et al., “The importance of being modular”, Nature, vol. 485, May 2012, pp. 584-585. |
| Reisch, “On bistable behavior and open-base breakdown of bipolar transistors in the avalanche regime-modeling and applications.” Electron Devices, IEEE Transactions on, 39.6 (1992): 1398-1409. |
| Sakui et al., “A new static memory cell based on the reverse base current effect of bipolar transistor.” Electron Devices, IEEE Transactions on, 36.6 (1989): 1215-1217. |
| Sakui et al, “A new static memory cell based on reverse base current (RBC) effect of bipolar transistor.” Electron Devices Meeting, 1988. IEDM'88. Technical digest, International IEEE, 1988, pp. 44-47. |
| Shim et al., “A BJT-Based heterostructure 1T-DRAM for Low-voltage Operation.” Electron Device Letters, vol. 33, No. 1, 2012, pp. 14-16. |
| Shin et al., “A novel double HBT-based capacitorless 1T DRAM cell with Si/SiGe heterojunctions.” Electron Device Letters, vol. 32, No. 7, 2011, pp. 850-852. |
| Shin et al., “Vertical-Gate Si/SiGe Double-HBT-Based Capacitorless 1T-DRAM Cell for Extended Retention Time at Low Latch Voltage.” Electron Device Letters, vol. 33, No. 2, 2012, pp. 134-136. |
| Sze et al., Physics of Semiconductor Devices, Wiley Intersciences, John Wiley & Sons, 2007, pp. 1-4. |
| Terada et al., “A new VLSI memory cell using capacitance coupling (CC cell).” Electron Devices, IEEE Transactions on, 31.9 (1984): pp. 1319-1324. |
| Ventrice et al., “Analytical model of deeply-scaled thyristors for memory applications.” Microelectronics and Electron Devices (WMED), 2012 IEEE Workshop on. IEEE, 2012, pp. 1-4. |
| Villaret et al., “Further insight into the physics and modeling of floating-body capacitorless DRAMs.” Electron Devices, IEEE Transaction on, 52.11 (2005); pp. 2447-2454. |
| Wu et al., “Experimental Demonstration of the High-Performance Floating-Body/Gate DRAM Cell for Embedded Memories”, IEEE Elec. Dev. Letters, vol. 33, No. 6, Jun. 2012, pp. 743-745. |
| Zhang et al., “Total Ionizing Dose Effects on FinFET-Based Capacitor-Less 1T-DRAMSs.” Nuclear Science, IEEE T-ransactions on, vol. 57, No. 6, 2010, pp. 3298-3304. |
| Ban et al., “A Scaled Floating Body Cell (FBC) Memory with High-k+Metal Gate on Thin-Silicon and Thin-Box for 16-nm Technology Node and Beyond”, Symposium on VLSI Technology, 2008, pp. 92-93. |
| Campardo et al., “VLSI Design of Non-Volatile Memories”, ISBN3-540-20198-X, Springer Berlin Heidelberg New York, 2005, pp. 94-95. |
| Han et al., “Programming/erasing Characteristics of 45 nm NOR-Type Flash Memory Based on SOI FinFET Structure.” J Korean Phys. Society, vol. 47, Nov. 2005, pp. S564-S567. |
| Headland, “Hot electron injection”, Feb. 19, 2004. |
| Kim et al., “Silicon on Replacement Insulator (SRI) Floating Body Cell (FBC) Memory”, Tech Digest, Symposium on VLSI Technology, 2010, pp. 165-166. |
| Kim et al., “Vertical Double Gate Z-RAM Technology with Remarkable low voltage operation for DRAW application,” Symposium on VLSI Technology, 2010, pp. 163-164. |
| Lin et al., “A New 1T DRAM Cell with Enhanced Floating Body Effect”, IEEE International Workshop on Memory Technology, Design and Testing, 2006, pp. 23-27. |
| Oh et al., “A 4-bit Double SONOS memory (DSM) with 4 Storage Nodes per Cell for Ultimate Multi-Bit Operation.” Tech Digest, Symposium on VLSI Technology, 2006, pp. 58-59. |
| Ohsawa et al., “An 18.5ns, 128Mb SOI DRAM with a Floating Body Cell”, IEEE International Solid-State Circuits Conference, 2005, pp. 458-459, 609. |
| Ohsawa et al., “Memory Design Using One-Transistor Gain Cell on SOI”, Tech. Digest, IEEE International Solid-State L'Arcuits, vol. 37, No. 11, 2002, pp. 1510-1522. |
| Okhonin et al., “A SOI Capacitor-less 1T-DRAM Concept.” IEEE International SOI Conference, 2001, pp. 153-154. |
| Okhonin et al., “Principles of Transient Charge Pumping on partially Depleted SOI MOSFETs.” IEEE Electron Device Letters, vol. 23, No. 5, May, 2002, pp. 279-281. |
| Okhonin et al., “A Capacitor-less 1T-DRAM Cell”, IEEE Electron Device Letters, vol. 23, No. 2, Feb. 2002, pp. 35087. |
| Pelizzer et al., “A 90nm Phase Change Memory Technology for Stand-Alone Non-Volatile memory Applications”, Sympsoium on VLSI Technology Digest of Technical Papers, 2006, pp. 1-2. |
| Ranica et al., “Scaled 1-T Bulk devices built with CMOS 90nm technology for low-cost eDRAM applications.” 2005 Symposium on VLSI Technology Digest of Technical Papers, 2005, pp. 38-39. |
| Pierret, “Semiconductor Device Fundamentals”, ISBN: 0-201-54393-1, 1996, by Addison-Wesley Publishing Company, Inc. PNPN Devices 463-476. |
| Tack et al., “The Multistable Charge-Controlled memory Effect in SOI Transistors at Low Temperatures”, IEEE Transactions on Electron Devices, vol. 37, May 1990, pp. 1373-1382. |
| Yoshida et al., “A Design of a Capacitorless 1T-DRAM Cell Using Gate-Induced Drain Leakage (GIDL) Current for Low-power and High-speed Embedded Memory”, International Electron Devices Meeting, 2003, pp. 1-4. |
| Villaret et al., “Mechanism of charge modulation in the floating body of triple-well nMOSFET capacitor-less DRAMs”, Microelectronic Engineering 72 (2004) 434-439. |
| Number | Date | Country | |
|---|---|---|---|
| 20200168609 A1 | May 2020 | US |
| Number | Date | Country | |
|---|---|---|---|
| 61309589 | Mar 2010 | US |
| Number | Date | Country | |
|---|---|---|---|
| Parent | 16574069 | Sep 2019 | US |
| Child | 16775808 | US | |
| Parent | 16404964 | May 2019 | US |
| Child | 16574069 | US | |
| Parent | 16200997 | Nov 2018 | US |
| Child | 16404964 | US | |
| Parent | 16017692 | Jun 2018 | US |
| Child | 16200997 | US | |
| Parent | 15701187 | Sep 2017 | US |
| Child | 16017692 | US | |
| Parent | 15485011 | Apr 2017 | US |
| Child | 15701187 | US | |
| Parent | 15347048 | Nov 2016 | US |
| Child | 15485011 | US | |
| Parent | 14956253 | Dec 2015 | US |
| Child | 15347048 | US | |
| Parent | 14688122 | Apr 2015 | US |
| Child | 14956253 | US | |
| Parent | 14448757 | Jul 2014 | US |
| Child | 14688122 | US | |
| Parent | 13941475 | Jul 2013 | US |
| Child | 14448757 | US | |
| Parent | 13478014 | May 2012 | US |
| Child | 13941475 | US | |
| Parent | 13244855 | Sep 2011 | US |
| Child | 13478014 | US | |
| Parent | 12797334 | Jun 2010 | US |
| Child | 13244855 | US |
