Patent Grant
12009362
As technology nodes continue to shrink routing for interconnect structures becomes more difficult. Three dimensional integrated circuits (3DICs) involve stacking devices in a vertical direction and electrically connecting the devices together, for example, using a through silicon via (TSV). In a 3DIC structure, a device is formed on one side of a substrate. The 3DIC reduces an area for the IC in a planar direction.
In another approach, interconnect structures, such as routing lines and power lines are formed on one side of a substrate and connected to a device on an opposite side of the substrate, for example using a TSV. The interconnect structures on an opposite side of the substrate from the device increases an area usable for routing, which increases routing options and reduces an area of the IC in the planar direction.
Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components, values, operations, materials, arrangements, or the like, are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. Other components, values, operations, materials, arrangements, or the like, are contemplated. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.
As technology nodes continue to shrink, three dimensional integrated circuits (3DICs), fin field effect transistors (FinFETs), gate all around (GAA) transistors, and backside routing structures alone are unable to keep up with the demand for reduced device area. Amphi-field effect transistors (amphi-FETs) are usable to improve routing options for interconnect structures, which permits further device size reduction. An amphi-FET includes active devices formed on both sides of a substrate. In contrast, a 3DIC includes two devices formed on separate substrates; and the separate substrates are then bonded together. The improved routing options in an amphi-FET means that increasing device size unnecessarily to accommodate connections between elements in the device is reduced or avoided.
The active devices in the amphi-FET are electrically connected using conductive elements extending through the substrate. For example, a gate structure on a first side of the substrate is electrically connected to a gate structure on a second side of the substrate by a gate via extending through the substrate. Similarly, a source/drain (S/D) contact on the first side of the substrate is electrically connected to an S/D contact on the second side of the substrate by an S/D connect via extending through the substrate. Due to these connections through the substrate, a signal, such as a power signal applied on one side of the substrate is able to transfer to the other side of the substrate without including additional routing or through substrate via (TSV) structures. For example, a ground signal connected to an S/D contact on the first side of the substrate is transferred to the second side of the substrate by the S/D connect via to the S/D contact on the second side of the substrate. The ground voltage is then usable on the second side of the substrate without providing a power rail for the ground voltage (or a TSV structure) on the second side of the substrate.
Integrated circuits (ICs) are often designed using cells, which include active devices and connection structures in order to implement an intended function. In some embodiments, a cell includes a single active device. In some embodiments, a cell includes multiple active devices. The ability to efficiently share signals and power from one side of the substrate to the other side of the substrate makes more routing tracks in a cell available for routing signals within the cell and into and out of the cell. Thus, a size of the cell is not unnecessarily increased merely to provide sufficient connections for the cell to function properly. In some instances, a gate density of a device including amphi-FETs is greater than 1.5 times a gate density of a device including active devices on a single side of the substrate. Gate density is a measure of how closely gate structures in a cell are spaced from one another. Gate density is commonly used to describe how efficiently the space within the cell is utilized. Increasing the cell size merely to provide routing options reduces gate density. In some instances, the gate density increase due to the use of amphi-FETs is more than 1.6 times the gate density of a device including active devices on a single side of the substrate.
This significant size reduction helps to keep pace with Moore's Law and also helps with reduced power consumption and increased device speed. The reduced power consumption is a result of having shorter distances between elements, so less power is lost to resistance and heating of conductive lines and vias in the amphi-FET device. The increased device speed results from being able to increase a size of active regions of the cell because less space within the cell is occupied by interconnect elements.
The first cell 220 includes a first active region 242. In some embodiments, the first active region 242 includes nanosheets (NS) for forming a gate all around (GAA) transistor. A first gate contact 250 is electrically connected to a gate structure associated with the first active region 242. A first via 252 electrically connects the first gate contact 250 to a first conductive line 254 of a first side interconnect structure. In some embodiments, the first conductive line 254 is usable to carry a signal or power to the gate structure in the first active region 242 through the first via 252 and the first gate contact 250.
The first cell 220 further includes a first S/D contact 260 electrically connected to an S/D electrode associated with the first active region 242. A second via 262 electrically connects the first S/D contact 260 to a second conductive line 264 of the first side interconnect structure. In some embodiments, the second conductive line 264 is usable to carry a signal or power to the S/D electrode in the first active region 242 through the second via 262 and the first S/D contact 260.
The second cell 230 includes a second active region 244. In some embodiments, the second active region 244 includes NS for forming a GAA transistor. A second gate contact 270 is electrically connected to a gate structure associated with the second active region 244. A third via 272 electrically connects the second gate contact 270 to a third conductive line 274 of a second side interconnect structure. In some embodiments, the third conductive line 274 is usable to carry a signal or power to the gate structure in the second active region 244 through the third via 272 and the second gate contact 270.
The second cell 230 further includes a second S/D contact 280 electrically connected to an S/D electrode associated with the second active region 244. A fourth via 282 electrically connects the second S/D contact 280 to a fourth conductive line 284 of the second side interconnect structure. In some embodiments, the fourth conductive line 284 is usable to carry a signal or power to the S/D electrode in the second active region 244 through the fourth via 282 and the second S/D contact 280.
The third conductive line 274 is electrically connected to the first conductive line 254 through the third via 272, the second gate contact 270, the gate structure in the second active region 244, the gate via 214, the gate structure in the first active region 242, the first gate contact 250 and the first via 252. This connection path is more direct than routing a connection path around the first active region 242 and the second active region 244. As a result, resistance of the amphi-FET 200 is reduced and a size of each of the first cell 220 and the second cell 230 is reduced in comparison with other structures that do not include the gate via 214.
The fourth conductive line 284 is electrically connected to the second conductive line 264 through the fourth via 282, the second S/D contact 280, the S/D electrode in the second active region 244, the S/D connect via 212, the S/D electrode in the first active region 242, the first S/D contact 260 and the second via 262. This connection path is more direct than routing a connection path around the first active region 242 and the second active region 244. As a result, resistance of the amphi-FET 200 is reduced and a size of each of the first cell 220 and the second cell 230 is reduced in comparison with other structures that do not include the S/D connect via 212.
In some embodiments, substrate 210 includes an elementary semiconductor including silicon or germanium in crystal, polycrystalline, or an amorphous structure; a compound semiconductor including silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and indium antimonide; an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GalnAs, GaInP, and GaInAsP; any other suitable material; or combinations thereof. In some embodiments, the alloy semiconductor substrate has a gradient SiGe feature in which the Si and Ge composition changes from one ratio at one location to another ratio at another location of the gradient SiGe feature. In some embodiments, the alloy SiGe is formed over a silicon substrate. In some embodiments, substrate 210 is a strained SiGe substrate. In some embodiments, the semiconductor substrate has a semiconductor on insulator structure, such as a silicon on insulator (SOI) structure. In some embodiments, the semiconductor substrate includes a doped epi layer or a buried layer. In some embodiments, the compound semiconductor substrate has a multilayer structure or the substrate includes a multilayer compound semiconductor structure.
In some embodiments, a number of NS in the first active region 242 is equal to a number of NS in the second active region 244. In some embodiments, the number of NS in the first active region 242 is different from the number of NS in the second active region 244. In some embodiments, at least one of the first active region 242 or the second active region 244 includes a transistor structure different from a GAA transistor, such as a FinFET or metal-oxide-semiconductor FET (MOSFET). While the cross-sectional view of
In some embodiments, the S/D connect via 212 and the gate via 214 independently include a fill material including cobalt (Co), tungsten (W), copper (Cu), ruthenium (Ru), titanium (Ti), tantalum (Ta), or alloys thereof, or other conductive materials. In some embodiments, the S/D connect via 212 and the gate via 214 include a liner surrounding the fill material. In some embodiments, the liner includes titanium nitride (TiN), titanium (Ti), ruthenium (Ru), cobalt (Co), tantalum (Ta), tantalum nitride (TaN), or alloys thereof, or other liner materials. In some embodiments, a composition of the S/D connect via 212 is a same composition as the gate via 214. In some embodiments, the composition of the S/D connect via 212 is different from the composition of the gate via 214. In some embodiments, the S/D connect via 212 connects to the S/D electrode of the first active region 242 and the second active region 244 through a silicide layer (not shown). In some embodiments, the gate via 214 connects to the gate structure of the first active region 242 and the second active region 244 through a silicide layer (not shown).
In some embodiments, the first gate contact 250 and the second gate contact 270 independently include a fill material including cobalt (Co), tungsten (W), copper (Cu), ruthenium (Ru), titanium (Ti), tantalum (Ta), or alloys thereof, or other conductive materials. In some embodiments, the first gate contact 250 and the second gate contact 270 include a liner surrounding the fill material. In some embodiments, the liner includes titanium nitride (TiN), titanium (Ti), ruthenium (Ru), cobalt (Co), tantalum (Ta), tantalum nitride (TaN), or alloys thereof, or other liner materials. In some embodiments, a composition of the first gate contact 250 is a same composition as the second gate contact 270. In some embodiments, the composition of the first gate contact 250 is different from the composition of the second gate contact 270. In some embodiments, each of the first gate contact 250 and the second gate contact 270 have a same composition as both the S/D connect via 212 and the gate via 214. In some embodiments, at least one of the first gate contact 250 or the second gate contact 270 has a different composition from at least one of the S/D connect via 212 or the gate via 214. In some embodiments, the first gate contact 250 and the second gate contact 270 independently connect to the gate structure of the corresponding first active region 242 and the second active region 244, through a silicide layer (not shown).
In some embodiments, the first S/D contact 260 and the second S/D contact 280 independently include a fill material including cobalt (Co), tungsten (W), copper (Cu), ruthenium (Ru), titanium (Ti), tantalum (Ta), or alloys thereof, or other conductive materials. In some embodiments, the first S/D contact 260 and the second S/D contact 280 include a liner surrounding the fill material. In some embodiments, the liner includes titanium nitride (TiN), titanium (Ti), ruthenium (Ru), cobalt (Co), tantalum (Ta), tantalum nitride (TaN), or alloys thereof, or other liner materials. In some embodiments, a composition of the first S/D contact 260 is a same composition as the second S/D contact 280. In some embodiments, the composition of the first S/D contact 260 is different from the composition of the second S/D contact 280. In some embodiments, each of the first S/D contact 260 and the second S/D contact 280 have a same composition as the S/D connect via 212, the gate via 214, the first gate contact 250 and the second gate contact 270. In some embodiments, at least one of the first S/D contact 260 or the second S/D contact 280 has a different composition from at least one of the S/D connect via 212, the gate via 214, the first gate contact 250 or the second gate contact 270. In some embodiments, the first S/D contact 260 and the second S/D contact 280 independently connect to the S/D electrode of the first active region 242 and the second active region 244, respectively, through a silicide layer (not shown).
In some embodiments, the first via 252, the second via 262, the third via 272 and the fourth via 282 independently include a fill material including cobalt (Co), tungsten (W), copper (Cu), ruthenium (Ru), titanium (Ti), tantalum (Ta), or alloys thereof, or other conductive materials. In some embodiments, the first via 252, the second via 262, the third via 272 and the fourth via 282 include a liner surrounding the fill material. In some embodiments, the liner includes titanium nitride (TiN), titanium (Ti), ruthenium (Ru), cobalt (Co), tantalum (Ta), tantalum nitride (TaN), or alloys thereof, or other liner materials. In some embodiments, a composition of the first via 252 is a same composition as each of the second via 262, the third via 272 and the fourth via 282. In some embodiments, the composition of the first via 252 is different from the composition of at least one of the second via 262, the third via 272 or the fourth via 282. In some embodiments, each of the first via 252, the second via 272, the third via 272 and the fourth via 282 have a same composition as the S/D connect via 212, the gate via 214, the first gate contact 250, the second gate contact 270, the first S/D contact 260 and the second S/D contact 280. In some embodiments, at least one of the first via 252, the second via 262, the third via 272 or the fourth via 282 has a different composition from at least one of the S/D connect via 212, the gate via 214, the first gate contact 250, the second gate contact 270, the first S/D contact 260 or the second S/D contact 280.
In some embodiments, the first conductive line 254, the second conductive line 264, the third conductive line 274 and the fourth conductive line 284 independently include a fill material including cobalt (Co), tungsten (W), copper (Cu), ruthenium (Ru), titanium (Ti), tantalum (Ta), or alloys thereof, or other conductive materials. In some embodiments, the first conductive line 254, the second conductive line 264, the third conductive line 274 and the fourth conductive line 284 include a liner surrounding the fill material. In some embodiments, the liner includes titanium nitride (TiN), titanium (Ti), ruthenium (Ru), cobalt (Co), tantalum (Ta), tantalum nitride (TaN), or alloys thereof, or other liner material. In some embodiments, a composition of the first conductive line 254 is a same composition as each of the second conductive line 264, the third conductive line 274 and the fourth conductive line 284. In some embodiments, the composition of the first conductive line 254 is different from the composition of at least one of the second conductive line 264, the third conductive line 274 or the fourth conductive line 284. In some embodiments, each of the first conductive line 254, the second conductive line 264, the third conductive line 274 and the fourth conductive line 284 have a same composition as the S/D connect via 212, the gate via 214, the first gate contact 250, the second gate contact 270, the first S/D contact 260, the second S/D contact 280, the first via 252, the second via 262, the third via 272 and the fourth via 282. In some embodiments, at least one of the first conductive line 254, the second conductive line 264, the third conductive line 274 or the fourth conductive line 284 has a different composition from at least one of the S/D connect via 212, the gate via 214, the first gate contact 250, the second gate contact 270, the first S/D contact 260, the second S/D contact 280, the first via 252, the second via 262, the third via 272 or the fourth via 282.
Method 300 includes operation 305, in which a first cell is formed on a first side of substrate. The first cell is formed using a series of deposition and patterning processes. In some embodiments, the deposition processes include chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), sputtering or another suitable deposition process. In some embodiments, the patterning processes include lithographic and etching processes, such as dry or wet etching. In some embodiments, the first cell includes NS and an interconnect structure, similar to the first cell 220 (
In operation 310, an S/D connect via is formed through the substrate. The S/D connect via is formed by depositing a sacrificial layer, such as a dielectric layer over at least one side of the substrate. In some embodiments where the S/D connect via is formed after the first cell, the sacrificial layer is formed on a single side of the substrate. In some embodiments where the first cell is formed after the S/D connect via, the sacrificial layer is formed on both sides of the substrate. The sacrificial layer and the substrate are etched to form an opening extending through the substrate. In embodiments that include forming the first cell prior to forming the S/D connect via, the opening exposes a portion of an S/D electrode of the first cell. The opening is then filled by one or more deposition processes in order to form the S/D connect. In some embodiments, the deposition processes include CVD, PVD, ALD, sputtering or another suitable deposition process. In some embodiments, the S/D connect via is similar to the S/D connect via 212 (
In operation 315, a gate via is formed through the substrate. In some embodiments, the gate via is formed simultaneously with the formation of the S/D connect via. The gate via is formed by depositing a sacrificial layer, such as a dielectric layer over at least one side of the substrate. In some embodiments where the gate via is formed after the first cell, the sacrificial layer is formed on a single side of the substrate. In some embodiments where the first cell is formed after the gate via, the sacrificial layer is formed on both sides of the substrate. The sacrificial layer and the substrate are etched to form an opening extending through the substrate. In embodiments that include forming the first cell prior to forming the gate via, the opening exposes a portion of a gate structure of the first cell. The opening is then filled by one or more deposition processes in order to form the S/D connect. In some embodiments, the deposition processes include CVD, PVD, ALD, sputtering or another suitable deposition process. In some embodiments, the gate via is similar to the gate via 214 (
In operation 320, the substrate is flipped. In some embodiments, the substrate is flipped using a robot arm and/or a vacuum chuck. Flipping the substrate exposes a second side of the substrate for processes. In some embodiments where the S/D connect via and/or the gate via is formed after the first cell, the substrate is flipped prior to forming the S/D connect via and/or the gate via. In some embodiments wherein the S/D connect via and/or the gate via is formed prior to the first cell, the substrate is flipped after forming the first cell.
In operation 325, a second cell is formed on the second side of the substrate. The second cell is formed using a series of deposition and patterning processes. In some embodiments, the deposition processes include CVD, PVD, ALD, sputtering or another suitable deposition process. In some embodiments, the patterning processes include lithographic and etching processes, such as dry or wet etching. In some embodiments, the second cell includes NS and an interconnect structure, similar to the second cell 230 (
In the first production track 402, the first cell 220 is formed on a first side of the substrate 210. The substrate 210 is then flipped and the S/D connect via 212 and the gate via 214 are formed to electrically connect to the first cell 220 through the substrate 210. The second cell 230 is then formed on the second side of the substrate 210 to electrically connect to the first cell 220 through the S/D connect via 212 and the gate via 214. In some embodiments, the first production track 402 is implemented by performing operations 305, 320, 310, 315 and 325 of method 300 (
In the second production track 404, the S/D connect via 212 and the gate via 214 are formed through the substrate 210. The first cell 220 is then formed on the first side of the substrate 210 to electrically connect to the S/D connect via 212 and the gate via 214. The substrate 210 is then flipped and the second cell 230 is formed on the second side of the substrate 210 to electrically connect to the first cell 220 through the S/D connect via 212 and the gate via 214. In some embodiments, the second production track 404 is implemented by performing operations 310, 315, 305, 320 and 325 of method 300 (
A first via 540 electrically connects the first S/D electrode 520 to a first power rail 550. In some embodiments, the first power rail 550 carries a reference voltage, e.g., ground. In some embodiments, the first power rail 550 carries a source voltage, e.g., VDD. In some embodiments, the first via 540 is omitted and the first power rail 550 is not directly connected to the first S/D electrode 520. A second via 545 electrically connects the first S/D electrode 520 to a second conductive line 555b. The second conductive line 555b is able to carry a signal to or from the first S/D electrode 520. In some embodiments, the second via 545 is omitted and the second conductive line 555b is not directly connected to the first S/D electrode 520. A first conductive line 555a is between the first power rail 550 and the second conductive line 555b. In some embodiments, the first conductive line 555a is connected to the first S/D electrode 520 by a via to carry a signal to or from the first S/D electrode 520. In some embodiments, the first S/D electrode 520 is electrically connected to the first power rail 550 and the second S/D electrode 520′ is electrically connected to the second power rail 550′.
A third via 545′ electrically connects the second S/D electrode 520′ to a third conductive line 555a′. The third conductive line 555a′ is able to carry a signal to or from the second S/D electrode 520′. In some embodiments, the third via 545′ is omitted and the third conductive line 555a′ is not directly connected to the second S/D electrode 520′. The third conductive line 555a′ is between a second power rail 550′ and a fourth conductive line 555b′. In some embodiments, the fourth conductive line 555b′ is connected to the second S/D electrode 520′ by a via to carry a signal to or from the second S/D electrode 520′.
In some embodiments, the second power rail 550′ carries a reference voltage, e.g., ground. In some embodiments, the second power rail 550′ carries a source voltage, e.g., VDD. In some embodiments, the second power rail 550′ is connected to the second S/D electrode 520′ by a via.
The material and formation method of the first via 540, the second via 545, the third via 545′, the first power rail 550, the first conductive line 555a, the second conductive line 555b, the second power rail 550′, the third conductive line 555a′ and the fourth conductive line 555b′ are similar to materials and formation methods for similar elements described above with respect to amphi-FET 200 (
The first S/D electrode 520 and the second S/D electrode 520′ conductive material surround S/D regions of the corresponding active regions. In some embodiments, the S/D regions include doped semiconductor materials. In some embodiments, the S/D regions include silicon. In some embodiments, the S/D regions include a strained material, such as silicon-germanium (SiGe). In some embodiments, the S/D regions are formed by epitaxial processes. In some embodiments, the S/D regions are formed by ion implantation. In some embodiments, the first S/D electrode 520 and the second S/D electrode 520′ are formed by deposition. In some embodiments, the first S/D electrode 520 and the second S/D electrode 520′ independently include cobalt (Co), tungsten (W), copper (Cu), ruthenium (Ru), titanium (Ti), tantalum (Ta), or alloys thereof, or other conductive materials. In some embodiments, a composition of the first S/D electrode 520 is a same composition as the second S/D electrode 520′. In some embodiments, the composition of the first S/D electrode 520 is different from the composition of the second S/D electrode 520′. In some embodiments, the first S/D electrode 520 and the second S/D electrode 520′ include a silicide layer.
A width of the S/D connect via 512 in the substrate 510 is equal to a width of the second S/D electrode 520′. The width is measured in a direction parallel to a top surface of the substrate 510. Maximizing a size of the S/D connect via 512 helps to minimize resistance in the S/D connect via 512, which improves power consumption. The width of the second S/D electrode 520′ is less than a width of the first S/D electrode 520. In some embodiments, the width of the second S/D electrode 520′ is equal to the width of the first S/D electrode 520.
A first dimension D1 of the active region 515 in a first direction perpendicular to the top surface of the substrate 510 ranges from about 0.8 times to about 15 times a minimum gate width. If the first dimension D1 is too small, then resistance within a channel of the amphi-FET 500 increases and impacts device performance, in some instances. If the first dimension D1 is too large, then a size of the amphi-FET 500 is increased without significant improvement in device performance, in some instances. The minimum gate width is also referred to as a critical dimension (CD), in some instances. The minimum gate width is a smallest size that is reliably produced during a manufacturing process. One of ordinary skill in the art would recognize that different technology nodes have different manufacturing processes and are able to produce different minimum gate widths.
A ratio of the first dimension D1 and a second dimension D2 of the first power rail 550 in a second direction parallel to the top surface of the substrate 510 ranges from about 1 to about 5. If the second dimension D2 is too small, then resistance in the first power rail 550 increases to a level that negatively impacts power consumption and uniform power distribution within the device, in some instances. If the second dimension D2 is too large, then a size of the amphi-FET 500 is increased without a significant improvement in performance, in some instances. In some embodiments, the second power rail 550′ has a same dimension as the first power rail 550.
A ratio of the first dimension D1 and a third dimension D3 of the second conductive line 555b in the second direction ranges from about 0.5 to about 3. If the third dimension D3 is too small, then resistance in the second conductive line 555b increases to a level that negatively impacts power consumption and signal reliability within the device, in some instances. If the third dimension D3 is too large, then a size of the amphi-FET 500 is increased without a significant improvement in performance, in some instances. In some embodiments, at least one of the first conductive line 555a, the third conductive line 555a′ or the fourth conductive line 555b′ has a same dimension as the second conductive line 555b.
A ratio of the first dimension D1 and a fourth dimension D4 of the first via 540 in the first direction ranges from about 2 to about 6. If the fourth dimension D4 is too small, then spacing between the first power rail 550 and the first S/D electrode 520 increases a risk of short circuiting within the device, in some instances. If the fourth dimension D4 is too large, then a size of the amphi-FET 500 is increased without a significant improvement in performance, in some instances. In some embodiments, at least one of the second via 545 or the third via 545′ has a same dimension as the first via 540. In some embodiments, a sixth dimension D6 is equal to the fourth dimension D4. In some embodiments, the sixth dimension D6 is different from the fourth dimension D4.
A ratio of the first dimension D1 and a fifth dimension D5 from a surface of the first S/D electrode 520 farthest from the substrate 510 to a surface of the second S/D electrode 520′ farthest from the substrate in the first direction ranges from about 10 to about 60. If the fifth dimension D5 is too small, then reliability of manufacturing the amphi-FET 500 is negatively impacted, in some instances. If the fifth dimension D5 is too large, then a size of the amphi-FET 500 is increased without a significant improvement in performance, in some instances.
A ratio of the first dimension D1 and a seventh dimension D7 of a space between the third conductive line 555a′ and the fourth conductive line 555b′ in the second direction ranges from about 0.5 to about 3. If the seventh dimension D7 is too small, then a risk of short circuit within the device or negative impacts from parasitic capacitance impact device performance, in some instances. If the seventh dimension D7 is too large, then a size of the amphi-FET 500 is increased without a significant improvement in performance, in some instances. In some embodiments, a spacing between other combinations of adjacent conductive lines and/or power rails has a same dimension as the seventh dimension D7.
In some embodiments, a size of the gate via 514 is a same size as the first via 560. Having the gate via 514 have a same size as the first via 560 reduces production cost by minimizing a number of masks used to produce the amphi-FET 500. Having the gate via 514 have the same size as the first via 560 also helps to reduce manufacturing error because the openings for forming the first via 560 and the gate via 514 are self-aligned.
The first gate structure 530 and the second gate structure 530′ independently include a gate dielectric layer and a gate electrode. The gate dielectric layer is between the corresponding active region and the corresponding gate electrode. In some embodiments, the gate dielectric layer includes silicon oxide and is formed by oxidizing an outer surface of the corresponding active region. In some embodiments, the gate dielectric layer includes silicon nitride or a high-k dielectric material. In some embodiments, the gate dielectric layer is formed by deposition, such as CVD, PVD, ALD or another suitable deposition process. The gate electrode includes a conductive material. In some embodiments, the gate electrode includes polysilicon. In some embodiments, the gate electrode comprises a metal, such as copper (Cu), cobalt (Co), aluminum (Al), tungsten (W), alloys or another suitable metal. In some embodiments, the gate electrode is formed by deposition, such as CVD, PVD, ALD or another suitable deposition process. In some embodiments, the first gate structure 530 and the second gate structure 530′ independently include an interfacial layer between the gate dielectric layer and the corresponding active region. In some embodiments, the first gate structure 530 and the second gate structure 530′ independently include a silicide layer.
A FET layout 605 is received. The FET layout 605 is a layout for a structure designed to be formed on a single side of a substrate. In some embodiments, the FET layout 605 is for a GAA device, a FinFET device or a MOSFET device. In some embodiments, the FET layout 605 is received from a cell library. In some embodiments, the FET layout 605 is received from a user input. The FET layout 605 includes a plurality of routing tracks 606. In some embodiments, at least one of the routing tracks 606 is a power rail. The FET layout 605 further includes a plurality of S/D electrodes including a first S/D electrode 608a, a second S/D electrode 608b, a third S/D electrode 608c and a fourth S/D electrode 608d. The FET layout 605 includes a first gate structure 609a and a second gate structure 609b.
A vertical cut line 615 is added to the FET layout 605. The vertical cut line 615 extends through the FET layout 605 in a direction perpendicular to the plurality of routing tracks 606. The vertical cut line 615 is between the first S/D electrode 608a and the third S/D electrode 608c.
The FET layout 605 is then divided into two cells. A first cell 620 includes the first S/D electrode 608a, the second S/D electrode 608b and the first gate structure 609a. The location of routing tracks 606 in the first cell 620 is the same as the location of the routing tracks 606 in the FET layout 605. A second cell 630 includes the third S/D electrode 608c, the fourth S/D electrode 608d and the second gate structure 609b. The location of routing tracks 606 in the second cell 630 is the same as the location of the routing tracks 606 in the FET layout 605. Maintaining the same location of the routing tracks 606 in the first cell 620 and the second cell 630 helps to simplify routing operations, such as automatic placement and routing (APR).
The first cell 620 is then processed to be formed on a first side of a substrate 610 and the second cell 630 is processed to be formed on a second side of the substrate 610 opposite to the first side. In some embodiments, the substrate 610 is similar to the substrate 210 (
A FET layout 705 is received. The FET layout 705 is a layout for a structure designed to be formed on a single side of a substrate. In some embodiments, the FET layout 705 is for a GAA device, a FinFET device or a MOSFET device. In some embodiments, the FET layout 705 is received from a cell library. In some embodiments, the FET layout 705 is received from a user input. The FET layout 705 includes a plurality of routing tracks 706. In some embodiments, at least one of the routing tracks 706 is a power rail. The FET layout 705 further includes a plurality of S/D electrodes includes a first S/D electrode 708a, a second S/D electrode 708b and a third S/D electrode 708c. The FET layout 705 includes a gate structure 709.
A horizontal cut line 715 is added to the FET layout 705. The horizontal cut line 715 extends through the FET layout 705 in a direction parallel to the plurality of routing tracks 706. The horizontal cut line 715 is between the second S/D electrode 708b and the third S/D electrode 708c. The horizontal cut line 715 passes through the gate structure 709.
The FET layout 705 is then divided into two cells. A first cell 720 includes a first portion 708a′ of the first S/D electrode 708a, the third S/D electrode 708c and a first portion 709′ of the gate structure 709. The location of routing tracks 706 in the first cell 720 are the same as the location of the routing tracks 706 in the FET layout 705. A second cell 730 includes a second portion 708a″ of the first S/D electrode 708a, the second S/D electrode 708b and a second portion 709″ of the gate structure 709. The location of routing tracks 706 in the second cell 730 are the same as the location of the routing tracks 706 in the FET layout 705. Maintaining the same location of the routing tracks 706 in the first cell 720 and the second cell 730 helps to simplify routing operations, such as automatic placement and routing (APR).
The first cell 720 is then processed to be formed on a first side of a substrate 710 and the second cell 730 is processed to be formed on a second side of the substrate 710 opposite to the first side. In some embodiments, the substrate 710 is similar to the substrate 210 (
The layout of the amphi-FET structure 800B includes the first cell 820 on a first side of a substrate 810 and the second cell 830 on the second side of the substrate 810 with cell boundaries 802′ for both cells aligned. When the layout of the FET structure 800A is converted to a layout of an amphi-FET structure 800B, the shared power rail is duplicated so that a first power rail 845a is in the first cell 820 and a second power rail 845b is in the second cell 830. The shared power rail is duplicated instead of being cut in half in order to avoid the increase in resistance that would result from reducing the size of the power rail. While the duplication of the shared power rail means a magnitude of the size reduction for the amphi-FET structure 800B is not as significant as if the shared power rail is cut in half, the amphi-FET structure 800B is still smaller than the FET structure 800A. In addition, the power consumption of the amphi-FET structure 800B will be similar to the power consumption of the FET structure 800A due to the similar sizes of the power rails in both structures.
The first cell 920 further includes a first conductive line 930a completely within the cell boundaries 902 and a first shielding line 940a on the cell boundary 902. The second cell 930 further includes a second conductive line 930b completely within the cell boundaries 902 and a second shielding line 940b on the cell boundary 902. A shielding line is usable to reduce coupling noise between adjacent conductive lines in an interconnect structure. In a structure formed entirely on a same side of the substrate, the shielding line is not usable because using the shielding line to carry a signal would negate the shielding effect. However, when used in an amphi-FET structure, one of the first shielding line 940a or the second shielding line 940b is usable to carry a signal. Thus, by using the amphi-FET structure, an additional line within the interconnect structure becomes usable for routing. The additional routing options helps to reduce or avoid increases in size of the amphi-FET in order to accommodate routing of signals to the amphi-FET. In some instances, the layout of the amphi-FET 900 is called a 2.5T horizontal cut mirror because there are five usable tracks (power rails are excluded from usable track determinations) between two cells. That is, each of the first cell 920 and the second cell 930 is considered to have 2.5 usable tracks.
The first cell 1120 includes a plurality of routing tracks 1106. The routing tracks 1106 are locations where conductive lines are able to be formed one level farther away from the substrate than the elements in the layout of the amphi-FET structure 1100. The first cell 1120 further includes a first active region 1115a and a second active region 1115b spaced from the first active region 1115a. In some embodiments, the first active region 1115a and the second active region 1115b include one or more NS. The first cell 1120 further includes a first S/D electrode 1122 associated with the first active region 1115a. The first cell 1120 further includes a first gate structure 1132a and a second gate structure 1132b, each of which are associated with both the first active region 1115a and the second active region 1115b.
The second cell 1130 includes the plurality of routing tracks 1106. The routing tracks 1106 are locations where conductive lines are able to be formed one level farther away from the substrate than the elements in the layout of the amphi-FET structure 1100. The second cell 1130 further includes a third active region 1115a′ and a fourth active region 1115b′ spaced from the third active region 1115a′. In some embodiments, the third active region 1115a′ and the fourth active region 1115b′ include one or more NS. The second cell 1130 further includes a second S/D electrode 1122′ associated with the third active region 1115a′. The second cell 1130 further includes a third gate structure 1132a′ and a fourth gate structure 1132b′, each of which are associated with both the third active region 1115a′ and the fourth active region 1115b′. The second cell 1130 further includes a connector 1140 electrically connecting an S/D electrode associated with the third active region 1115a′ to an S/D electrode associated with the fourth active region 1115b′.
An S/D connect via 1112 electrically connects the first S/D electrode 1122 to the second S/D electrode 1122′ through the substrate. A gate via 1114 electrically connects the first gate structure 1132a to the third gate structure 1132a′ through the substrate. One of ordinary skill in the art would understand that the components of the layout of the amphi-FET 1100 are formed using materials and processes described above, which are not repeated here for the sake of brevity.
The first cell 1220 includes a plurality of routing tracks 1206. The routing tracks 1206 are locations where conductive lines are able to be formed one level farther away from the substrate than the elements in the layout of the amphi-FET structure 1200. The first cell 1220 further includes a first active region 1215a and a second active region 1215b spaced from the first active region 1215a. In some embodiments, the first active region 1215a and the second active region 1215b include one or more NS. The first cell 1220 further includes a first S/D electrode 1222 associated with the first active region 1215a. The first cell 1220 further includes a first gate structure 1232a and a second gate structure 1232b, each of which are associated with both the first active region 1215a and the second active region 1215b.
The second cell 1230 includes the plurality of routing tracks 1206. The routing tracks 1206 are locations where conductive lines are able to be formed one level farther away from the substrate than the elements in the layout of the amphi-FET structure 1200. The second cell 1230 further includes a third active region 1215a′ and a fourth active region 1215b′ spaced from the third active region 1215a′. In some embodiments, the third active region 1215a′ and the fourth active region 1215b′ include one or more NS. The second cell 1230 further includes a second S/D electrode 1222′ associated with the third active region 1215a′. The second cell 1230 further includes a third gate structure 1232a′ and a fourth gate structure 1232b′, each of which are associated with both the third active region 1215a′ and the fourth active region 1215b′. The second cell 1230 further includes a connector 1240 electrically connecting an S/D electrode associated with the third active region 1215a′ to an S/D electrode associated with the fourth active region 1215b′.
An S/D connect via 1212 electrically connects the first S/D electrode 1222 to the second S/D electrode 1222′ through the substrate. A gate via 1214 electrically connects the first gate structure 1232a to the third gate structure 1232a′ through the substrate. One of ordinary skill in the art would understand that the components of the layout of the amphi-FET 1200 are formed using materials and processes described above, which are not repeated here for the sake of brevity
The first cell 1320 includes a plurality of routing tracks 1306. The routing tracks 1306 are locations where conductive lines are able to be formed one level farther away from the substrate than the elements in the layout of the amphi-FET structure 1300. The first cell 1320 further includes a first active region 1315a and a second active region 1315b spaced from the first active region 1315a. In some embodiments, the first active region 1315a and the second active region 1315b include one or more NS. The first cell 1320 further includes a first S/D electrode 1322 associated with the first active region 1315a. The first cell 1320 further includes a first gate structure 1332a and a second gate structure 1332b, each of which are associated with both the first active region 1315a and the second active region 1315b.
The second cell 1330 includes the plurality of routing tracks 1306. The routing tracks 1306 are locations where conductive lines are able to be formed one level farther away from the substrate than the elements in the layout of the amphi-FET structure 1300. The second cell 1330 further includes a third active region 1315a′ and a fourth active region 1315b′ spaced from the third active region 1315a′. In some embodiments, the third active region 1315a′ and the fourth active region 1315b′ include one or more NS. The second cell 1330 further includes a second S/D electrode 1322′ associated with the third active region 1315a′. The second cell 1330 further includes a third gate structure 1332a′ and a fourth gate structure 1332b′, each of which are associated with both the third active region 1315a′ and the fourth active region 1315b′. The second cell 1330 further includes a connector 1340 electrically connecting an S/D electrode associated with the third active region 1315a′ to an S/D electrode associated with the fourth active region 1315b′.
An S/D connect via 1312 electrically connects the first S/D electrode 1322 to the second S/D electrode 1322′ through the substrate. A gate via 1314 electrically connects the first gate structure 1332a to the third gate structure 1332a′ through the substrate. One of ordinary skill in the art would understand that the components of the layout of the amphi-FET 1300 are formed using materials and processes described above, which are not repeated here for the sake of brevity.
In
Design house (or a design team) 1420 generates an IC design layout diagram 1422. IC design layout diagram 1422 includes various geometrical patterns designed for an IC device 1460. The geometrical patterns correspond to patterns of metal, oxide, or semiconductor layers that make up the various components of IC device 1460 to be fabricated. The various layers combine to form various IC features. For example, a portion of IC design layout diagram 1422 includes various IC features, such as an active region, gate electrode, source and drain region of the channel bar, source electrode, and drain electrode, metal lines or vias of an interlayer interconnection, and openings for bonding pads, to be formed in a semiconductor substrate (such as a silicon wafer) and various material layers disposed on the semiconductor substrate. Design house 1420 implements a proper design procedure to form IC design layout diagram 1422. The design procedure includes one or more of logic design, physical design or place and route. IC design layout diagram 1422 is presented in one or more data files having information of the geometrical patterns. For example, IC design layout diagram 1422 can be expressed in a GDSII file format or DFII file format.
Mask house 1430 includes mask data preparation 1432 and mask fabrication 1444. Mask house 1430 uses IC design layout diagram 1422 to manufacture one or more masks 1445 to be used for fabricating the various layers of IC device 1460 according to IC design layout diagram 1422. Mask house 1430 performs mask data preparation 1432, where IC design layout diagram 1422 is translated into a representative data file (RDF). Mask data preparation 1432 provides the RDF to mask fabrication 1444. Mask fabrication 1444 includes a mask writer. A mask writer converts the RDF to an image on a substrate, such as a mask 1445 or a semiconductor wafer 1453. The design layout diagram 1422 is manipulated by mask data preparation 1432 to comply with particular characteristics of the mask writer and/or requirements of IC fab 1450. In
In some embodiments, mask data preparation 1432 includes optical proximity correction (OPC) which uses lithography enhancement techniques to compensate for image errors, such as those that can arise from diffraction, interference, other process effects and the like. OPC adjusts IC design layout diagram 1422. In some embodiments, mask data preparation 1432 includes further resolution enhancement techniques (RET), such as off-axis illumination, sub-resolution assist features, phase-shifting masks, other suitable techniques, and the like or combinations thereof. In some embodiments, inverse lithography technology (ILT) is also used, which treats OPC as an inverse imaging problem.
In some embodiments, mask data preparation 1432 includes a mask rule checker (MRC) that checks the IC design layout diagram 1422 that has undergone processes in OPC with a set of mask creation rules which contain certain geometric and/or connectivity restrictions to ensure sufficient margins, to account for variability in semiconductor manufacturing processes, and the like. In some embodiments, the MRC modifies the IC design layout diagram 1422 to compensate for limitations during mask fabrication 1444, which may undo part of the modifications performed by OPC in order to meet mask creation rules.
In some embodiments, mask data preparation 1432 includes lithography process checking (LPC) that simulates processing that will be implemented by IC fab 1450 to fabricate IC device 1460. LPC simulates this processing based on IC design layout diagram 1422 to create a simulated manufactured device, such as IC device 1460. The processing parameters in LPC simulation can include parameters associated with various processes of the IC manufacturing cycle, parameters associated with tools used for manufacturing the IC, and/or other aspects of the manufacturing process. LPC takes into account various factors, such as aerial image contrast, depth of focus (DOF), mask error enhancement factor (MEEF), other suitable factors, and the like or combinations thereof. In some embodiments, after a simulated manufactured device has been created by LPC, if the simulated device is not close enough in shape to satisfy design rules, OPC and/or MRC are be repeated to further refine IC design layout diagram 1422.
It should be understood that the above description of mask data preparation 1432 has been simplified for the purposes of clarity. In some embodiments, mask data preparation 1432 includes additional features such as a logic operation (LOP) to modify the IC design layout diagram 1422 according to manufacturing rules. Additionally, the processes applied to IC design layout diagram 1422 during mask data preparation 1432 may be executed in a variety of different orders.
After mask data preparation 1432 and during mask fabrication 1444, a mask 1445 or a group of masks 1445 are fabricated based on the modified IC design layout diagram 1422. In some embodiments, mask fabrication 1444 includes performing one or more lithographic exposures based on IC design layout diagram 1422. In some embodiments, an electron-beam (e-beam) or a mechanism of multiple e-beams is used to form a pattern on a mask (photomask or reticle) 1445 based on the modified IC design layout diagram 1422. Mask 1445 can be formed in various technologies. In some embodiments, mask 1445 is formed using binary technology. In some embodiments, a mask pattern includes opaque regions and transparent regions. A radiation beam, such as an ultraviolet (UV) beam, used to expose the image sensitive material layer (e.g., photoresist) which has been coated on a wafer, is blocked by the opaque region and transmits through the transparent regions. In one example, a binary mask version of mask 1445 includes a transparent substrate (e.g., fused quartz) and an opaque material (e.g., chromium) coated in the opaque regions of the binary mask. In another example, mask 1445 is formed using a phase shift technology. In a phase shift mask (PSM) version of mask 1445, various features in the pattern formed on the phase shift mask are configured to have proper phase difference to enhance the resolution and imaging quality. In various examples, the phase shift mask can be attenuated PSM or alternating PSM. The mask(s) generated by mask fabrication 1444 is used in a variety of processes. For example, such a mask(s) is used in an ion implantation process to form various doped regions in semiconductor wafer 1453, in an etching process to form various etching regions in semiconductor wafer 1453, and/or in other suitable processes.
IC fab 1450 is an IC fabrication business that includes one or more manufacturing facilities for the fabrication of a variety of different IC products. In some embodiments, IC Fab 1450 is a semiconductor foundry. For example, there may be a manufacturing facility for the front end fabrication of a plurality of IC products (front-end-of-line (FEOL) fabrication), while a second manufacturing facility may provide the back end fabrication for the interconnection and packaging of the IC products (back-end-of-line (BEOL) fabrication), and a third manufacturing facility may provide other services for the foundry business.
IC fab 1450 includes fabrication tools 1452 configured to execute various manufacturing operations on semiconductor wafer 1453 such that IC device 1460 is fabricated in accordance with the mask(s), e.g., mask 1445. In various embodiments, fabrication tools 1452 include one or more of a wafer stepper, an ion implanter, a photoresist coater, a process chamber, e.g., a CVD chamber or LPCVD furnace, a CMP system, a plasma etch system, a wafer cleaning system, or other manufacturing equipment capable of performing one or more suitable manufacturing processes as discussed herein.
IC fab 1450 uses mask(s) 1445 fabricated by mask house 1430 to fabricate IC device 1460. Thus, IC fab 1450 at least indirectly uses IC design layout diagram 1422 to fabricate IC device 1460. In some embodiments, semiconductor wafer 1453 is fabricated by IC fab 1450 using mask(s) 1445 to form IC device 1460. In some embodiments, the IC fabrication includes performing one or more lithographic exposures based at least indirectly on IC design layout diagram 1422. Semiconductor wafer 1453 includes a silicon substrate or other proper substrate having material layers formed thereon. Semiconductor wafer 1453 further includes one or more of various doped regions, dielectric features, multilevel interconnects, and the like (formed at subsequent manufacturing steps).
In some embodiments, EDA system 1500 includes an APR system. Methods described herein of designing layout diagrams represent wire routing arrangements, in accordance with one or more embodiments, are implementable, for example, using EDA system 1500, in accordance with some embodiments.
In some embodiments, EDA system 1500 is a general purpose computing device including a processor 1502 and a non-transitory, computer-readable storage medium 1504. Computer-readable storage medium 1504 is, amongst other things, encoded with, i.e., stores, computer program code 1506, i.e., a set of executable instructions. Execution of computer program code 1506 by processor 1502 represents (at least in part) an EDA tool which implements a portion or all of the methods described herein in accordance with one or more embodiments (hereinafter, the noted processes and/or methods).
Processor 1502 is electrically coupled to computer-readable storage medium 1504 via a bus 1508. Processor 1502 is also electrically coupled to an I/O interface 1510 by bus 1508. A network interface 1512 is also electrically connected to processor 1502 via bus 1508. Network interface 1512 is connected to a network 1514, so that processor 1502 and computer-readable storage medium 1504 are capable of connecting to external elements via network 1514. Processor 1502 is configured to execute computer program code 1506 encoded in computer-readable storage medium 1504 in order to cause EDA system 1500 to be usable for performing a portion or all of the noted processes and/or methods. In one or more embodiments, processor 1502 is a central processing unit (CPU), a multi-processor, a distributed processing system, an application specific integrated circuit (ASIC), and/or a suitable processing unit.
In one or more embodiments, computer-readable storage medium 1504 is an electronic, magnetic, optical, electromagnetic, infrared, and/or a semiconductor system (or apparatus or device). For example, computer-readable storage medium 1504 includes a semiconductor or solid-state memory, a magnetic tape, a removable computer diskette, a random access memory (RAM), a read-only memory (ROM), a rigid magnetic disk, and/or an optical disk. In one or more embodiments using optical disks, computer-readable storage medium 1504 includes a compact disk-read only memory (CD-ROM), a compact disk-read/write (CD-R/W), and/or a digital video disc (DVD).
In one or more embodiments, storage medium 1504 stores computer program code 1506 configured to cause EDA system 1500 (where such execution represents (at least in part) the EDA tool) to be usable for performing a portion or all of the noted processes and/or methods. In one or more embodiments, storage medium 1504 also stores information which facilitates performing a portion or all of the noted processes and/or methods. In one or more embodiments, storage medium 1504 stores library 1507 of standard cells including such standard cells as disclosed herein.
EDA system 1500 includes I/O interface 1510. I/O interface 1510 is coupled to external circuitry. In one or more embodiments, I/O interface 1510 includes a keyboard, keypad, mouse, trackball, trackpad, touchscreen, and/or cursor direction keys for communicating information and commands to processor 1502.
EDA system 1500 also includes network interface 1512 coupled to processor 1502. Network interface 1512 allows EDA system 1500 to communicate with network 1514, to which one or more other computer systems are connected. Network interface 1512 includes wireless network interfaces such as BLUETOOTH, WIFI, WIMAX, GPRS, or WCDMA; or wired network interfaces such as ETHERNET, USB, or IEEE-1364. In one or more embodiments, a portion or all of noted processes and/or methods, is implemented in two or more EDA systems 1500.
EDA system 1500 is configured to receive information through I/O interface 1510. The information received through I/O interface 1510 includes one or more of instructions, data, design rules, libraries of standard cells, and/or other parameters for processing by processor 1502. The information is transferred to processor 1502 via bus 1508. EDA system 1500 is configured to receive information related to a UI through I/O interface 1510. The information is stored in storage medium 1504 as user interface (UI) 1542.
In some embodiments, a portion or all of the noted processes and/or methods is implemented as a standalone software application for execution by a processor. In some embodiments, a portion or all of the noted processes and/or methods is implemented as a software application that is a part of an additional software application. In some embodiments, a portion or all of the noted processes and/or methods is implemented as a plug-in to a software application. In some embodiments, at least one of the noted processes and/or methods is implemented as a software application that is a portion of an EDA tool. In some embodiments, a portion or all of the noted processes and/or methods is implemented as a software application that is used by EDA system 1500. In some embodiments, a layout diagram which includes standard cells is generated using a tool such as VIRTUOSO® available from CADENCE DESIGN SYSTEMS, Inc., or another suitable layout generating tool.
In some embodiments, the processes are realized as functions of a program stored in a non-transitory computer readable recording medium. Examples of a non-transitory computer readable recording medium include, but are not limited to, external/removable and/or internal/built-in storage or memory unit, e.g., one or more of an optical disk, such as a DVD, a magnetic disk, such as a hard disk, a semiconductor memory, such as a ROM, a RAM, a memory card, and the like.
Details regarding an integrated circuit (IC) manufacturing system (e.g., EDA system 1500 of
An aspect of this description relates to a method of making a semiconductor device. The method includes forming a first active region on a first side of a substrate. The method further includes forming a first source/drain (S/D) electrode surrounding a first portion of the first active region. The method further includes forming an S/D connect via extending through the substrate. The method further includes flipping the substrate. The method further includes forming a second active region on a second side of the substrate, wherein the second side of the substrate is opposite to the first side of the substrate. The method further includes forming a second S/D electrode surrounding a first portion of the second active region, wherein the S/D connect directly contacts both the first S/D electrode and the second S/D electrode. In some embodiments, the method further includes forming a first gate structure surrounding a second portion of the first active region; forming a second gate structure surrounding a second portion of the second active region; and forming a gate via extending through the substrate, wherein the gate via directly contacts both the first gate structure and the second gate structure. In some embodiments, forming the S/D connect via occurs prior to forming the first S/D electrode and prior to forming the second S/D electrode. In some embodiments, forming the S/D connect via occurs after forming the first S/D electrode. In some embodiments, flipping the substrate occurs prior to forming the S/D connect via. In some embodiments, forming the S/D connect via includes forming the S/D connect via having a same width parallel to the first side of the substrate as a width of the first S/D electrode.
An aspect of this description relates to a method of designing a semiconductor device. The method includes receiving a layout of a device, wherein the device is designed to be formed on a single side of a substrate, and the layout comprises a plurality of routing tracks. The method further includes cutting the layout along a first direction, wherein the first direction is parallel to the plurality of routing tracks or perpendicular to the plurality of routing tracks. The method further includes dividing the cut layout into a first cell and a second cell based on a location of the cutting, wherein the first cell includes a first gate structure, and the second cell includes a second gate structure. The method further includes inserting a gate via into the first cell or the second cell, wherein the gate via is positioned to directly connect to the first gate structure and to directly connect to the second gate structure. In some embodiments, the first direction is parallel to the plurality of routing tracks. In some embodiments, the first direction is perpendicular to the plurality of routing tracks. In some embodiments, the method further includes positioning the first cell on a first side of the substrate; and positioning the second cell on a second side of the substrate, wherein the second side of the substrate is opposite to the first side of the substrate. In some embodiments, the method further includes inserting a source/drain (S/D) via into the first cell or the second cell, wherein the S/D via directly connects to a first S/D region in the first cell and directly connects to a second S/D region in the second cell. In some embodiments, the method further includes instructing fabrication tools to manufacture the semiconductor device following the inserting the gate via.
An aspect of this description relates to a method of making a semiconductor device. The method includes forming a first electrode surrounding a first portion of a first active region on a first side of a substrate. The method further includes forming a second electrode surrounding a second portion of a second active region on a second side of the substrate. The method further includes forming a through substrate via extending through the substrate, wherein the through substrate via directly contacts both the first electrode and the second electrode. In some embodiments, forming the first electrode includes forming a source/drain (S/D) electrode. In some embodiments, forming the first electrode includes forming a gate electrode. In some embodiments, forming the through substrate via includes forming the through substrate via having a same width, measured parallel to the first side of the substrate, as at least one of the first electrode or the second electrode. In some embodiments, forming the through substrate via includes forming the through substrate via having a smaller width, measured parallel to the first side of the substrate, than both the first electrode and the second electrode. In some embodiments, the method further includes forming a third electrode surrounding a third portion of the first active region; and forming a fourth electrode surrounding a fourth portion of the second active region. In some embodiments, the method further includes forming a second through substrate via extending through the substrate, wherein the second through substrate via directly connects to the third electrode and the fourth electrode. In some embodiments, forming the second through substrate via includes forming the second through substrate via offset from the through substrate via in a first direction parallel to the first side of the substrate, and offset from the through substrate via in a second direction perpendicular to a longitudinal direction of the first active region.
The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.
This application is a divisional of U.S. application Ser. No. 17/214,194, filed Mar. 26, 2021, which is incorporated herein by reference in its entirety.
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| 7260442 | Hwang et al. | Aug 2007 | B2 |
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| 10504982 | Lee | Dec 2019 | B2 |
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| Number | Date | Country | |
|---|---|---|---|
| 20240021606 A1 | Jan 2024 | US |
| Number | Date | Country | |
|---|---|---|---|
| Parent | 17214194 | Mar 2021 | US |
| Child | 18360539 | US |
