Claims
- 1. A method for forming an array of contact structures for providing electrical connection to an integrated circuit, said method comprising:
providing a dielectric substrate; forming a plurality of depressions into said dielectric substrate, each of said plurality of depressions having an inside surface defined thereon; and forming a plurality of conductive layers, one of said plurality of conductive layers being formed over at least a portion of the inside surface of each of said plurality of depressions, said plurality of depressions being sized and spaced such that said plurality of conductive layers can be removably and electrically engaged with an array of electrical leads of said integrated circuit.
- 2. The method of claim 1, wherein forming said plurality of depressions into said dielectric substrate comprises conducting an etching operation on said dielectric substrate.
- 3. The method of claim 1, further comprising establishing electrical connection between said plurality of conductive layers and external circuitry.
- 4. The method of claim 1, wherein forming said plurality of conductive layers comprises forming a layer including a material selected from the group consisting of titanium, tungsten, beryllium, copper, gold, palladium, combinations thereof, and alloys thereof.
- 5. A method for making a contact structure that makes electrical contact with an electrical lead of an integrated circuit package, the method comprising:
providing a substrate including a dielectric material; forming a depression into said substrate, said depression having an inside surface defined thereon; forming a conductive layer disposed over at least a portion of said inside surface of said depression, said depression being sized and positioned such that said conductive layer may electrically engage said electrical lead; and forming an electrical trace disposed over a surface of said substrate, said electrical trace being:
positioned in electrical contact with said conductive layer; and composed of a conductive material so as to provide electrical communication between said conductive layer and external circuitry.
- 6. The method of claim 5, wherein said substrate comprises a silicon-containing material.
- 7. The method of claim 5, further comprising making an electrical connection to said electrical trace with conductive tape that extends from said electrical trace to a side of said substrate opposite said surface of said substrate.
- 8. The method of claim 5, wherein said conductive layer comprises a material selected from the group consisting of titanium, tungsten, beryllium, copper, gold, palladium, combinations thereof, and alloys thereof.
- 9. A method of making an interposer structure for providing electrical communication between an array of electrical leads of an integrated circuit and external circuitry, the method comprising:
providing a substrate including a dielectric material; and forming an array of contact structures over said substrate, said array of contact structures being sized and spaced so as to electrically engage said array of electrical leads, each of said contact structures including:
a raised member extending away from said substrate and having a top surface distal to said substrate; a conductive layer disposed over at least a portion of said top surface of said raised member; and an electrical trace disposed over a surface of said substrate, said electrical trace being in electrical contact with said conductive layer, said electrical trace comprising a conductive material so as to provide electrical communication between said conductive layer and said external circuitry.
- 10. The method of claim 9, further comprising forming an array of terminal contact points in electrical communication with said array of contact structures, said array of contact structures having a first pitch and said array of terminal contact points having a second pitch that is greater than said first pitch.
- 11. The method of claim 10, wherein:
said array of terminal contact points is in electrical communication with said array of contact structures by conductive members selected from the group consisting of conductive tape, wirebonded leads, and non-bonded leads; and said conductive members are positioned in electrical contact with said electrical traces.
- 12. The method of claim 11, wherein one or more of said raised members are included in a replaceable module that is removably attached to said substrate.
- 13. A method of making an interposer structure for providing electrical communication between an array of electrical leads of an integrated circuit and external circuitry, the method comprising:
providing a substrate including a dielectric material; and forming an array of contact structures on said substrate, said array of contact structures being sized and spaced so as to be capable of electrically engaging said array of electrical leads, wherein each of said contact structures is formed by:
forming a depression into said substrate, said depression having an inside surface defined thereon; forming a conductive layer disposed over at least a portion of said inside surface of said depression; forming an electrical trace disposed over a surface of said substrate; and electrically connecting said electrical trace with said conductive layer, wherein said electrical trace comprises a conductive material so as to provide electrical communication between said conductive layer and said external circuitry.
- 14. The method of claim 13, further comprising forming an array of terminal contact points in electrical communication with said array of contact structures, wherein:
said array of contact structures has a first pitch; and said array of terminal contact points has a second pitch that is greater than said first pitch.
- 15. The method of claim 14, wherein:
said array of terminal contact points is in electrical communication with said array of contact structures by conductive members selected from the group consisting of conductive tape, wirebonded leads, and non-bonded leads; and said conductive members are positioned in electrical contact with said electrical traces.
Parent Case Info
[0001] This application is a divisional of U.S. patent application Ser. No. 09/631,253 filed on Aug. 2, 2000, which is a divisional of U.S. patent application Ser. No. 09/058,586, filed on Apr. 10, 1998, which are incorporated herein by reference.
Divisions (2)
|
Number |
Date |
Country |
Parent |
09631253 |
Aug 2000 |
US |
Child |
10365874 |
Feb 2003 |
US |
Parent |
09058586 |
Apr 1998 |
US |
Child |
09631253 |
Aug 2000 |
US |