Patent Application
20240332250
This application claims the priority benefit of Italian Application for Patent No. 102023000006039 filed on Mar. 29, 2023, the content of which is hereby incorporated by reference in its entirety to the maximum extent allowable by law.
The description relates to manufacturing semiconductor devices.
Solutions as described herein can be applied to power integrated circuit (IC) semiconductor devices such as power quad flat no-leads (QFN) packages for automotive or industrial products, for instance.
In current manufacturing processes of (IC) semiconductor devices, multiple devices are concurrently processed and finally singulated into individual devices.
During processing, a plurality of substrates (leadframes) for individual devices are held together in a leadframe strip using metallic connecting structures including (sacrificial) connecting bars running along the periphery of each device.
Prior to the singulation step, a plating step can be performed in order to plate the leadframe bottom surface with a metallic (solderable) layer made of tin, for instance.
Processing of certain devices may be facilitated by providing relatively large connecting bars (e.g., wider than 200 microns) that are exposed during the plating step. This results in the connecting bars being plated during the plating step with a fairly large amount of metal accumulated on the connecting bars.
During the singulation step a blade is used to remove the connecting bars and the solderable metallic layer plated thereon. Due to the amount of metal accumulated on the connecting bars, the action of the blade during the singulation step may produce flakes or filaments that undesirably “bridge” neighboring leads causing a short circuit therebetween.
Such an undesired electrical coupling (short) causes rejection and/or failure of the device.
There is a need in the art for solutions which aim at addressing the issues discussed in the foregoing.
One or more embodiments relate to a method.
One or more embodiments relate to a corresponding (integrated circuit) semiconductor device.
In solutions as described herein, a processing step is provided in order to counter filaments/flakes formation which could cause failure of the device.
In solutions as described herein, metallic material accumulated on the back/bottom surface of the connecting bars during the plating step is removed before the singulation step in order to counter flakes/filaments formation.
In solutions as described herein, metallic material may be removed from the back/bottom surface of the connecting bars via laser ablation.
One or more embodiments will now be described, by way of example only, with reference to the annexed figures, wherein:
Corresponding numerals and symbols in the different figures generally refer to corresponding parts unless otherwise indicated.
The figures are drawn to clearly illustrate the relevant aspects of the embodiments and are not necessarily drawn to scale.
The edges of features drawn in the figures do not necessarily indicate the termination of the extent of the feature.
In the ensuing description one or more specific details are illustrated, aimed at providing an in-depth understanding of examples of embodiments of this description. The embodiments may be obtained without one or more of the specific details, or with other methods, components, materials, etc. In other cases, known structures, materials, or operations are not illustrated or described in detail so that certain aspects of embodiments will not be obscured.
Reference to “an embodiment” or “one embodiment” in the framework of the present description is intended to indicate that a particular configuration, structure, or characteristic described in relation to the embodiment is comprised in at least one embodiment. Hence, phrases such as “in an embodiment” or “in one embodiment” that may be present in one or more points of the present description do not necessarily refer to one and the same embodiment.
Moreover, particular conformations, structures, or characteristics may be combined in any adequate way in one or more embodiments.
The headings/references used herein are provided merely for convenience and hence do not define the extent of protection or the scope of the embodiments.
For simplicity and ease of explanation, throughout this description, and unless the context indicates otherwise, like parts or elements are indicated in the various figures with like reference signs, and a corresponding description will not be repeated for each and every figure.
These portions of leadframes or substrates are indicated with the reference 120 in the figures, e.g., in
In fact, in current manufacturing processes of (integrated circuit) semiconductor devices plural devices/leadframes are processed concurrently. Concurrent processing of a plurality of devices is achieved by providing a common substrate (e.g., a leadframe strip) comprising a plurality of individual substrate for each device.
The designation “leadframe” (or “lead frame”) is currently used (see, for instance the USPC Consolidated Glossary of the United States Patent and Trademark Office) to indicate a metal frame that provides support for an integrated circuit chip or die as well as electrical leads to interconnect the integrated circuit in the die or chip (the terms chip/s and die/dice are regarded as synonymous) to other electrical components or contacts.
Essentially, a leadframe comprises an array of electrically-conductive formations (or leads, e.g., 12B) that from an outline location extend inwardly in the direction of a semiconductor chip or die thus forming an array of electrically-conductive formations from a die pad (e.g., 12A in
In certain cases, a leadframe can be of the pre-molded type, that is a type of leadframe comprising a sculptured metal (e.g., copper) structure formed by etching a metal sheet and comprising empty spaces that are filled by an insulating compound (a resin, for instance) “pre-molded” on the sculptured metal structure.
In order to concurrently process several devices, several leadframes are arranged in a leadframe strip 12 and held together via sacrificial connecting bars CB running at the periphery of the individual leadframes 120.
Leadframes 120 are connected to the connecting bars via so-called tie bars TB, bridge-like formations that connect the pads (e.g., 12A) or the leads (e.g., 12B) of a leadframe to the connecting bars.
As known to those of skill in the art, current manufacturing processes of (integrated circuit, IC) semiconductor devices may involve: arranging one or more semiconductor (e.g., silicon) die on the top/front surface of a corresponding die mounting location (e.g., die pads 12A); providing electrical coupling between the die/dice and selected one of the leads 12B via wire bonding or, as it is the case in power devices, via clips or ribbons; molding an insulating molding compound (e.g., an epoxy resin) on the leadframe strip 12 having the dice arranged on the top/front surface thereof to provide a protective plastic package to the devices; plating a solderable electrically conductive layer (e.g., a tin layer) on the bottom/back surface of the leadframes 12; and a final singulation step wherein the processed leadframe strip 12 is cut (e.g., via sawing) into individual devices (with individual leadframes 120).
The sequence of steps just described is merely exemplary insofar as, for example, additional processing steps may be envisaged.
As noted, processing steps as described so far are otherwise conventional in the art, which makes it making unnecessary to provide a more detailed description herein.
In various embodiments, other techniques (e.g., printing) can be adopted in the place of plating to provide a solderable metallic layer on the back or bottom surface of the substrate 120.
Singulation is performed after dice/chips are arranged on the top/front surface of the corresponding die mounting locations (e.g., the die pads 12A) and a plastic encapsulation is molded onto the assembly. The dice/chips are assumed to be arranged on the front or top surface of the leadframe strip 12/individual leadframes 120. Thus, they are not visible in figures such as
As known to those skilled in the art, an electrically conductive layer of, for example, tin may enhance solderability of the device onto support substrate like a printed circuit board (PCB), for instance.
In certain embodiments, the leadframe portion indicated with the reference 12A in
This can be the case, for instance, of a power device, where the current(s) transferred from a (power) die to the power output leads of the device can be significant and leads with a larger contact area may be used for that purpose.
Consequently, it will be understood that the leadframe portion indicated with the reference 12A in
A processing flow as consider so far may involve a plating step wherein the connecting bars CB are exposed (that is, left uncovered by the molding compound) at the back/bottom surface of the leadframe strip 12.
In the case exemplified in
Depending on the device design, connecting bars CB as exemplified in
As discussed, after the plating step, the leadframe strip 12 is cut (e.g., via a sawing blade B: for simplicity this is visible only in
In the singulation step the blade B cuts the connecting bars CB along their length (over a region having a width indicated as SW) thus removing the connecting bars CB as well as a portion of the tie bars TB connected thereto.
The common substrate 12 has a second surface opposite the first surface and comprises adjacent substrate portions 120 having mutually facing sides with elongate sacrificial connecting bars CB extending therebetween.
A solderable metallic layer (e.g., tin) is grown (e.g., plated) on the second surface of the common electrically conductive substrate 12 with the solderable metallic layer extending (also) over the connecting bars CB.
As a consequence of the action of the blade B and due to the amount of solderable metallic material plated on the back/bottom surface of the leadframes in the leadframe strip 12, filaments F of solderable metallic material may form starting from a die pad 12A (or from a lead 12B).
As illustrated in
It is observed that formation of such filaments F is a major cause of rejection of when processing certain types of IC semiconductor devices.
As discussed, a possible conventional approach to counter filaments F formation involves reducing in as much as possible the thickness of the solderable metallic layer deposited on the back/bottom surface of the leadframe 12 during the plating step.
It is however noted that: the thickness of the solderable layer cannot be reduced beyond a certain limit as this would cause solderability issues when soldering the device to the final substrate (e.g., a PCB); and reducing the thickness of the solderable layer reduces formation of filaments F (thus leading to lower defect ratios), but does not provide a completely adequate solution to the problem of filament formation.
In solutions as described herein, formation of filaments F is countered by (selectively) removing the solderable metallic layer deposited on the back/bottom surface of the connecting bars CB, from at least part of the length the sacrificial connecting bars CB.
As illustrated in
As exemplified in
In various embodiments, other techniques (e.g., etching) can be adopted to selectively remove the solderable metallic layer from the locations 100.
In solutions as described herein, formation of filaments F is thus countered in so far as (e.g., prior to the singulation step) the solderable metallic layer is removed from selected locations 100 of the connecting bars CB; the full thickness of the solderable metallic layer is removed, thus leaving uncovered, that is exposed, the metallic material of the leadframe strip 12 underneath.
In examples as considered herein, the solderable metallic layer may be tin and the leadframe 12 copper. In these examples, copper will be exposed at the (ablated) regions 100, while the rest of the leadframe strip 12 will be covered with tin. Different materials or alloys may be used depending on application options.
In examples as considered herein, cutting the leadframe 12 providing (prior to singulation) a common electrically conductive substrate having the plurality of semiconductor dice arranged onto the first surface thereof to provide singulated individual semiconductor devices is (e.g., via the blade B over a width SW) along the length of the elongate sacrificial connecting bars CB having the solderable metallic layer removed from at least part of the length the sacrificial connecting bars CB.
In examples as considered herein, the solderable metallic layer is removed (e.g., via laser ablation LB) at selected locations 100 distributed along the length of the sacrificial connecting bars CB.
As illustrated, the solderable metallic layer can be removed from the sacrificial connecting bars CB at tie bars TB that couple the elongate sacrificial connecting bars (CB) to adjacent substrate portions 120 in the common electrically conductive substrate (leadframe 12).
As illustrated in
After removing the solderable metallic layer at regions 100, a singulation step may be performed, wherein the sacrificial connecting bars CB are removed (via sawing, for instance).
Having removed the full thickness of the solderable metallic layer at regions 100, the blade will not contact the solderable metallic layer at the tie bars TB thus reducing (notionally eliminating) the risk of filament formation.
As illustrated in
That is, the solderable metallic layer can be removed from the distal ends 100′ of the tie bars TB that (in the leadframe 12 prior to singulation) couple the elongate sacrificial connecting bars CB to adjacent substrate portions 120 in the common electrically conductive substrate 12.
It is noted that removing the solderable metallic material from the regions 100 of the connecting bars CB does not compromise the solderability of the final device; apart from the small portion 100′ at the distal ends of the remainders of the tie bars TB, the bottom surface of the leadframes 120 is plated with a solderable metallic layer of a desired thickness.
Such processing may result in a (final) singulated semiconductor device that comprises one or more semiconductor dice (or chips) arranged onto a first surface of a portion 120 of an electrically conductive substrate (such as a leadframe 12) having a second surface opposite the first surface with a solderable metallic layer grown on the second surface.
In such a final singulated semiconductor device, the respective portion (leadframe portion 120) of electrically conductive substrate comprises remainders of the tie bars (the distal ends 100′) distributed along the length of and protruding from at least one side of that leadframe portion. The solderable metallic layer is absent from these remainders of tie bars 100′ in so far as the solderable metallic layer was removed (e.g., laser ablated) from these distal ends 100′.
The claims are an integral part of the technical teaching provided in respect of the embodiments.
Without prejudice to the underlying principles, the details and embodiments may vary, even significantly, with respect to what has been described by way of example only without departing from the extent of protection. The extent of protection is determined by the annexed claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 102023000006039 | Mar 2023 | IT | national |
