The present invention relates to the field of integrated circuit manufacture; more specifically, it relates to methods of simultaneously forming multiple structures having different dimensions using sidewall transfer.
As the density and performance of integrated circuits increase, there is a corresponding decrease in the dimensions of integrated circuit structures. Sidewall image transfer techniques have been used to define integrated circuit structures of such small dimensions that are not easily or impossible to obtain using conventional photolithographic techniques. However, current sidewall image transfer techniques can only provide only one critical dimension at critical pitch in a given fabrication level. Accordingly, there exists a need in the art to eliminate the deficiencies and limitations described hereinabove.
A first aspect of the present invention is a method, comprising: forming a plurality of mandrels on a layer on a substrate; forming a first conformal layer on the mandrels and on a top surface of the layer; forming a second conformal layer on the first conformal layer; forming a block mask over a second less than whole portion of the plurality of mandrels; performing an isotropic etch to remove the second conformal layer from a first less than whole portion of the plurality of mandrels where the second conformal layer is not protected by the block mask; performing an anisotropic etch of the first and second conformal layers to (i) form first sidewall spacers on the first less than whole portion of the plurality mandrels and to (ii) form second sidewall spacers on the second less than whole portion of the plurality mandrels, the first and second sidewall spacers having different widths; removing the plurality of mandrels; and using the first and second sidewall spacers as a hardmask, simultaneously transferring the pattern formed by the first and second sidewall spacers into the layer.
A second aspect of the present invention is a method, comprising: forming a first and a second mandrel on a layer on a substrate; forming a first conformal layer on sidewalls and top surfaces of the first and second mandrels and on a top surface of the layer between the first and second mandrels; forming a second conformal layer on a top surface of the first conformal layer; forming a block mask over the second mandrel and regions of the first and second conformal layers proximate to the second mandrel; using an isotropic etch, removing the second conformal layer where the second conformal layer is not protected by the block mask; removing the block mask; performing an anisotropic etch to form first sidewall spacers on the first mandrel and second sidewall spacers on the second mandrel, the first and second sidewall spacers having different widths; removing the first and second mandrels; and using the first and second sidewall spacers as a hardmask, simultaneously transferring the pattern formed by the first and second sidewall spacers into the layer.
A third aspect of the present invention is a method, comprising: forming a first, a second and a third mandrel on a layer on a substrate; forming a first conformal layer on sidewalls and top surfaces of the first, second and third mandrels and on a top surface of the layer between the first, second and third mandrels; forming a second conformal layer on a top surface of the first conformal layer; forming a first block mask over the second mandrel and regions of the first and second conformal layers proximate to the second mandrel; using a first isotropic etch, removing the second conformal layer where the second conformal layer is not protected by the first block mask; removing the first block mask; forming a third conformal layer on exposed surfaces of the first and second conformal layers; forming a second block mask on the third conformal layer over the second and third mandrels; using a second isotropic etch, removing the third conformal layer where the third conformal layer is not protected by the second block mask; performing an anisotropic etch to simultaneously form first sidewall spacers on the first mandrel, second sidewall spacers on the second mandrel and third sidewall spacers on the third mandrel, the first, second and third sidewall spacers having different widths; removing the first, second and third mandrels; and using the first, second and third sidewall spacers as a hardmask, simultaneously transferring the pattern formed by the first, second and third sidewall spacers into the layer.
A fourth aspect of the present invention is a method comprising: forming N mandrels on a top surface of a layer of a substrate, wherein N is a positive integer equal to or greater than 2; depositing N conformal layers; removing regions of N−1 conformal layers using a different block mask of N−1 block masks between depositions of each of the last 2 to N conformal layers, such that for I=1 to N, the Ith mandrel has I conformal layers on sidewall of the Ith mandrel, each of the N mandrels having a different number and a different combination of the N conformal layers; using an anisotropic etch, forming a sidewall spacer on each sidewall of the N mandrels, for I=1 to N, the Ith mandrel having a sidewall comprising only I of the N conformal layers; removing the N mandrels; and using the N sidewall spacers as a hardmask, simultaneously transferring the pattern formed by the N sidewall spacers into the layer.
These and other aspects of the invention are described below.
The features of the invention are set forth in the appended claims. The invention itself, however, will be best understood by reference to the following detailed description of illustrative embodiments when read in conjunction with the accompanying drawings, wherein:
FIGS. 1M1A through 1M1E and 1M2A through 1M2B are cross-sectional views illustrating transferring the hard mask structures of
The ability to project a clear image of a small feature on a photomask onto a photoresist layer is limited by the wavelength of the light that is used, and the ability of the reduction lens system of a projection photolithographic exposure tool to capture enough diffraction orders from the illuminated mask. Current state-of-the-art photolithography exposure tools using deep ultraviolet (DUV) light from excimer lasers with wavelengths of 248 and 193 nm allow minimum feature sizes down to about 50 nm to be directly printed. Mask features define the integrated circuit structures. The minimum feature size that a projection system can print is given approximately by:
where:
The embodiments of the present invention include methods of forming multiple different width critical dimension features simultaneously. The methods include forming multiple sidewall spacers of different widths formed from different combinations of conformal layers on different mandrels, removing the mandrels, and simultaneously transferring the pattern of the different sidewall spacers into an underlying layer.
In
In
In
In
FIGS. 1M1A through 1M1E and 1M2A through 1M2B are cross-sectional views illustrating transferring the sidewall spacer structures of
FIGS. 1M1A through 1M1C illustrate forming trench isolation when layer 100 is silicon. In FIG. 1MA1, layer 100 is etched using spacers 135, 140 and 145 as hardmasks to form trenches 150. In FIG. 1M1B, sidewall spacers 135, 140 and 145 are removed. In FIG. 1M1C, trenches 150 (see FIG. 1M1A) are filled with a dielectric material to form trench isolation 155. Some regions of trench isolation 155 are separated by regions 100A of layer 100 that are W1 wide, some of regions of trench isolation 155 are separated by regions 100B of layer 100 that are W2 wide, and some of regions of trench isolation 155 are separated by regions 100C of layer 100 that are W3 wide. Since at least W1 and W2 are less than the critical dimension of the photolithographic exposure tool used to define mandrels 110 (see
FIGS. 1M1D and 1M1E illustrate forming gate electrodes of transistors when layer 100 is a layer of polysilicon over a layer of gate dielectric. In FIG. 1M1D, the pattern and horizontal dimensions of sidewall spacers 135, 140 and 145 of FIG. 1M1A have been transferred into layer 100 and the sidewall spacers removed to form gate electrodes 160A, 160B and 160C having respective widths W1, W2 and W3. Since at least W1 and W2 are less than the critical dimension of the photolithographic exposure tool used to define mandrels 110 (see
In FIG. 1M1E additional processing has been performed to supply source/drains 165A, 165B and 165C, forming respective field effect transistors 170A, 170B and 170C.
FIGS. 1M2A and 1M2B, illustrate forming doped wells 175 when layer 100 is a layer of silicon. In FIG. 1M2A, an ion implantation of dopant species X (e.g., Ge, As, P or B) using sidewall spacers 135, 140 and 145 as ion implantation block masks to form doped wells 175 having the inverse pattern of sidewall spacers 135, 140 and 145. In FIG. 1M2B sidewall spacers 135, 140 and 145 are removed. Some regions of doped wells 175 are separated by regions 100B of layer 100 that are W1 wide, some of regions of doped wells 175 are separated by regions 100B of layer 100 that are W2 wide, and some of regions of doped wells 175 are separated by regions 100C of layer 100 that are W3. Since at least W1 and W2 are less than the critical dimension of the photolithographic exposure tool used to define mandrels 110 (see
If the steps illustrated in
In the embodiments described supra, the three critical dimensions W1, W2 and W3 are determined by the thickness of the three sidewall spacers. For example, if all three sidewalls spacers were 10 nm thick, then W1=10 nm, W2=20 nm and W3=30 nm. For example, if the first sidewall spacer is 10 nm thick, the second sidewall spacer is 20 nm thick and the third sidewall spacer is 30 nm thick, then W1=10 nm, W2=30 nm and W3=60 nm.
Thus, the embodiments of the present invention provide a sidewall image transfer method that can provide multiple critical dimensions at critical pitch in a given fabrication level.
The descriptions of the various embodiments of the present invention have been presented for purposes of illustration, but are not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.
| Number | Name | Date | Kind |
|---|---|---|---|
| 4776922 | Bhattacharyya et al. | Oct 1988 | A |
| 5795830 | Cronin et al. | Aug 1998 | A |
| 6063688 | Doyle et al. | May 2000 | A |
| 6300221 | Roberds et al. | Oct 2001 | B1 |
| 6335257 | Tseng | Jan 2002 | B1 |
| 7087532 | Dobuzinsky et al. | Aug 2006 | B2 |
| 7301210 | Abadeer et al. | Nov 2007 | B2 |
| 7390746 | Bai et al. | Jun 2008 | B2 |
| 7699996 | Furukawa et al. | Apr 2010 | B2 |
| 7763531 | Abadeer et al. | Jul 2010 | B2 |
| 7807575 | Zhou | Oct 2010 | B2 |
| 7919413 | Chen | Apr 2011 | B2 |
| 8030217 | Niroomand et al. | Oct 2011 | B2 |
| 8099686 | Schultz | Jan 2012 | B2 |
| 8123968 | Bai et al. | Feb 2012 | B2 |
| 8168377 | Mitsuoka et al. | May 2012 | B2 |
| 8173357 | Nishimura | May 2012 | B2 |
| 8314034 | Tan et al. | Nov 2012 | B2 |
| 8324036 | Cheng et al. | Dec 2012 | B2 |
| 8383448 | Kao | Feb 2013 | B2 |
| 8394710 | Cheng et al. | Mar 2013 | B2 |
| 20020045308 | Juengling | Apr 2002 | A1 |
| 20050164454 | Leslie | Jul 2005 | A1 |
| 20070292996 | Abadeer et al. | Dec 2007 | A1 |
| 20080258188 | Kao | Oct 2008 | A1 |
| 20090246954 | Miyoshi et al. | Oct 2009 | A1 |
| 20100144151 | Sills et al. | Jun 2010 | A1 |
| 20100248481 | Schultz | Sep 2010 | A1 |
| 20110014786 | Sezginer et al. | Jan 2011 | A1 |
| 20110049630 | Majumdar et al. | Mar 2011 | A1 |
| 20110076850 | Sumioka | Mar 2011 | A1 |
| 20110113393 | Sezginer | May 2011 | A1 |
| 20110117743 | Bai et al. | May 2011 | A1 |
| 20110130006 | Abatchev et al. | Jun 2011 | A1 |
| 20120118854 | Smayling et al. | May 2012 | A1 |
| 20120132616 | Barnola et al. | May 2012 | A1 |
| 20120164390 | Washburn et al. | Jun 2012 | A1 |
| 20120164837 | Tan et al. | Jun 2012 | A1 |
| 20120241975 | Farys et al. | Sep 2012 | A1 |
| 20120252175 | Majumdar et al. | Oct 2012 | A1 |
| 20130001749 | Arnold et al. | Jan 2013 | A1 |
| 20130001750 | Arnold et al. | Jan 2013 | A1 |
| 20130032945 | Lin et al. | Feb 2013 | A1 |
| 20130032949 | Lin et al. | Feb 2013 | A1 |
| 20130089984 | Raghunathan et al. | Apr 2013 | A1 |
| Number | Date | Country |
|---|---|---|
| 2011054664 | May 2011 | WO |
| Number | Date | Country | |
|---|---|---|---|
| 20140024209 A1 | Jan 2014 | US |