Patent Application
20250006613
Integrated circuit (IC) chips and/or semiconductor dies are routinely connected to larger circuit boards such as motherboards and other types of printed circuit boards (PCBs) via a package substrate. As IC chips and/or dies reduce in size and interconnect densities increase, alternatives to traditional substrate layers are being developed to provide stable transmission of high-frequency data signals between different circuitry and/or increased power delivery. One option being pursued is the implementation of package substrates with glass cores. Generally, glass core implementations offer several advantages compared to implementations with conventional epoxy cores, including a higher plated through-hole (PTH) density, lower signal losses, and lower total thickness variation.
In general, the same reference numbers will be used throughout the drawing(s) and accompanying written description to refer to the same or like parts. The figures are not necessarily to scale. Instead, the thickness of the layers or regions may be enlarged in the drawings. Although the figures show layers and regions with clean lines and boundaries, some or all of these lines and/or boundaries may be idealized. In reality, the boundaries and/or lines may be unobservable, blended, and/or irregular.
As shown in the illustrated example, each of the dies 106, 108 is electrically and mechanically coupled to the package substrate 110 via corresponding arrays of interconnects 114. In
As shown in
As used herein, the bridge bumps 118 are bumps on the dies 106, 108 through which electrical signals pass between different ones of the dies 106, 108 within the IC package 100. Thus, as shown in the illustrated example, the bridge bumps 118 of the first die 106 are electrically coupled to the bridge bumps 118 of the second die 108 via an interconnect bridge 126 (e.g., a silicon-based interconnect bridge, an interconnect die, an embedded interconnect bridge (EMIB)) embedded in the package substrate 110. As represented in
In some examples, an underfill material 119 is disposed between the dies 106, 108 and the package substrate 110 around and/or between the first level interconnects 114 (e.g., around and/or between the core bumps 116 and/or the bridge bumps 118). In the illustrated example, only the first die 106 is associated with the underfill material 119. However, in other examples, both dies 106, 108 are associated with the underfill material 119. In other examples, the underfill material 119 is omitted. In some examples, the mold compound used for the package lid 112 is used as an underfill material that surrounds the first level interconnects 114.
In some examples, the IC package 100 includes additional passive components, such as surface-mount resistors, capacitors, and/or inductors disposed on the package mounting surface 105 of the package substrate 110 and/or the die mounting surface 122 of the package substrate 110.
In
In some examples, the cores 132, 134, 136 include at least one of: aluminosilicate, borosilicate, alumino-borosilicate, silica, and/or fused silica. In some examples, the cores 132, 134, 136 include one or more additives including: aluminum oxide (Al2O3), boron trioxide (B2O3), magnesia oxide (MgO), calcium oxide (CaO), stoichiometric silicon oxide (SrO), barium oxide (BaO), stannic oxide (SnO2), nickel alloy (Na2O), potassium oxide (K2O), phosphorus trioxide (P2O3), zirconium dioxide (ZrO2), lithium oxide (Li2O), titanium (Ti), and/or zinc (Zn). In some examples, the cores 132, 134, 136 include silicon and oxygen. In some examples, the cores 132, 134, 136 include silicon, oxygen and/or one or more of aluminum, boron, magnesium, calcium, barium, tin, sodium, potassium, strontium, phosphorus, zirconium, lithium, titanium, and/or zinc. In some examples, the cores 132, 134, 136 include at least 23 percent silicon by weight and at least 26 percent oxygen by weight. In some examples, the glass cores 132, 134, 136 are individual layers of glass including silicon, oxygen, and aluminum. In some examples, the cores 132, 134, 136 include at least 23 percent silicon by weight, at least 26 percent oxygen by weight, and at least 5 percent aluminum by weight. In some examples, as discussed further below, different ones of the glass cores 132, 134, 136 include different materials or different compositions of materials so that the different glass cores 132, 134, 136 are associated with different coefficients of thermal expansion (CTE). In some examples, the CTE is modified between the different glass cores 132, 134, 136 by changing the amount of alkali dopants (e.g., Na2O, K2O, etc.) included in the glass. In general, the lower the alkali content, the lower the CTE. Thus, for a CTE of 3 ppm/° C., the alkali content may be less than 0.1%. By contrast, for a CTE of 9 ppm/° C., the alkali content can be up to 20%.
In some examples, the cores 132, 134, 136 are amorphous solid glass layers. In some examples, the cores 132, 134, 136 are layers of glass that do not include an organic adhesive or an organic material. In some examples, the cores 132, 134, 136 are solid layers of glass having a rectangular shape in plan view. In some examples, the cores 132, 134, 136, as glass substrates, include at least one glass layer and do not include epoxy and do not include glass fibers (e.g., do not include an epoxy-based prepreg layer with glass cloth). In some examples, the cores 132, 134, 136 correspond to single pieces of glass that extend the full height/thickness of each corresponding core.
In some examples, the cores 132, 134, 136 have a rectangular shape that is substantially coextensive, in plan view, with the layers above and/or below the core. In some examples, the cores 132, 134, 136 have a thickness in a range of about 25 micrometers (μm) to about 400 μm (with the overall thickness of the substrate core 128 ranging from about 50 μm to about 1.4 millimeters (mm)). In some examples, the cores 132, 134, 136 can have dimensions of about 10 mm on a side to about 250 mm on a side (e.g., 10 mm by 10 mm to 250 mm by 250 mm). In some examples, the cores 132, 134, 136 correspond to rectangular prism volumes with sections (e.g., vias) removed and filled with other materials (e.g., metal).
The build-up regions 130, 131 are represented in
In some examples, one or both of the build-up regions 130, 131 may be omitted. That is, in some examples, the stack of glass cores 132, 134, 136 defines most (e.g., all or substantially all) of the thickness of the package substrate 110 (e.g., all except for outer solder resist layers, all except for a reduced set of metallization layers in the build-up regions 130, 131, etc.). In some such examples, the stack of glass cores 132, 134, 136 includes more than three glass layers and the redistribution of electrical paths defined by the interconnects 124 is achieved by traces or routing running parallel to and between adjacent ones of the glass layers. Further, in some examples, as shown in
Among other things, glass cores are advantageous over epoxy-based cores because glass is stiffer and, therefore, provides for greater mechanical support or strength for the package substrate. Thus, the substrate core 128 and, more particularly, the individual glass cores 132, 134, 136 are example means for strengthening the package substrate. In addition to mechanical benefits, glass cores also provide other advantages including a higher plated through-hole (PTH) density, lower signal losses, and a lower total thickness variation.
Although the above advantages may be realized in disclosed examples, glass cores also present challenges due to the fragile (e.g., brittle) nature of glass and the possibility of defects that can develop into cracks that propagate through the glass. A common type of failure of known glass cores is referred to as a seware failure. Seware failures result in the separation of a glass core along a crack that propagates from an edge of the glass core along its length and width between the main outer surfaces (e.g., upper and lower surfaces, front and back surfaces) of the glass core. That is, seware failures are characterized by a glass core being split into two separate sheets of glass along a line extending generally parallel to the main plane of the glass core.
Factors that contribute to seware failures include defects on the edges of glass cores resulting from singulation and the internal stress induced by a mismatch in coefficient of thermal expansion (CTE) between the glass core (e.g., a CTE of around 3 ppm/° C. to 10 ppm/° C.) and the material in the build-up regions (e.g., a CTE of around 39 ppm/° C. for the organic dielectric layers, a CTE of around 17 ppm/° C. for the copper, and a CTE around 2.6 ppm/° C. for silicon) during thermal cycles of the package substrate 110 (either during the fabrication process or during use thereafter). More particularly, package substrates, such as the package substrate 110 of
Examples disclosed herein reduce (e.g., minimize) concerns for seware failures by implementing the substrate core 128 of the substrate with multiple distinct (e.g., disaggregated) glass cores (e.g., the glass cores 132, 134, 136) stacked on top of one another as shown in
For instance, in some examples, the middle glass core 134 has a lower CTE than the top glass core 132 and a lower CTE than the bottom glass core 136. In some examples, the CTE of the top glass core 132 and the bottom glass core 136 are the same. Thus, in some examples, the different CTEs of the glass cores 132, 134, 136 are symmetrical across the overall thickness of the substrate core 128. That is, the arrangement or ordering of the stack of glass cores 132, 134, 136 and their associated CTEs define a symmetric sequence of CTEs (e.g., a symmetrical CTE gradient) from a lowermost glass core (e.g., the third glass core 136) to an uppermost glass core (e.g., the first glass core 132). In some such examples, the lowest CTE value in the symmetrical CTE gradient is closer to the middle of the stack of multiple glass cores than a highest CTE value in the symmetrical CTE gradient (which are closer the upper and lower sides of the stack). In other examples, the different CTEs may not be symmetrical. For instance, in some examples, the top glass core 132 (e.g., the glass core closest to the dies 106, 108) has the highest CTE in the stack and the bottom glass core 136 (e.g., the glass core farthest from the dies 106, 108) has the lowest CTE with the central glass core 134 having a CTE between the other two. In other examples, the top glass core 132 (e.g., the glass core closest to the dies 106, 108) has the lowest CTE in the stack with the bottom glass core 136 having the highest CTE in the stack. Any other suitable arrangement of differing CTE values across any suitable number of stacked glass cores may additional or alternatively be implemented to achieve any suitable CTE gradient across the overall substrate core 128. In some examples, the highest CTE for a glass core is around 7 ppm/° C. to 9 ppm/° C. and the lowest CTE is around 3 ppm/° C. to 5 ppm/° C., with one or more intervening glass core having CTEs at different incremental points between these outer limits.
In addition to implementing multiple glass cores (e.g., the glass cores 132, 134, 136) with different CTEs to reduce stress, in some examples, as already noted above, one or both of the build-up regions 130, 131 is omitted or significantly reduced in thickness (e.g., reduced in the number of metallization layers included therein). As a result, there is less stress produced on the glass cores 132, 134, 136 from the CTE mismatch between the glass and the build-up regions 130, 131.
Further, in some examples, a buffer material 140 (e.g., buffer layer, adhesive resin/material/layer) is disposed between adjacent ones of the glass cores 132, 134, 136 to hold the glass cores together. In some such examples, the buffer material 140 has a relatively low modulus of elasticity to absorb stress resulting from thermal fluctuations and the different CTEs of the different glass cores 132, 134, 136, thereby further reducing stress internal to the substrate core 128. In some examples, the buffer material 140 is an organic dielectric material (e.g., polyimide, parylene, etc.). In some examples, the buffer material 140 is an inorganic dielectric material (e.g., silicon oxide (SiOx), silicon nitride (SiNx)). In some examples, the buffer material 140 includes a carbon doped oxide (CDO). In some examples, the buffer material 140 includes the same or similar dielectric material used in the build-up regions 130, 131. In some examples, the layers of the buffer material 140 include conductive material that facilitates the redistribution of electrical paths between the glass cores 132, 134, 136. Thus, the materials between the glass cores are also referred to herein as redistribution material. Redistribution material may include one or more redistribution layers in the package substrate 110. Likewise, in such examples, the stack of glass cores 132, 134, 136 is sometimes referred to herein as a redistribution region or redistribution layer.
Although three different glass cores (e.g., the glass cores 132, 134, 136) are shown in the example substrate core 128 of
In the illustrated example of
In the illustrated example, the different glass cores 206, 208, 210, 212, 214 correspond to different ones of the glass cores 132, 134, 136 of
In the illustrated example, the different glass cores 206, 208, 210, 212, 214 are separated by intervening layers of dielectric material 220 (e.g., adhesive material, adhesive resin) corresponding to the buffer material 140 discussed above in connection with
In the illustrated example of
In this example, the first glass core 206 includes a cavity 228 containing an interconnect bridge 230 embedded therein. In this example, the interconnect bridge 230 corresponds to the interconnect bridge 126 of
As shown in the illustrated example, a first solder resist layer 232 is added onto the build-up region 204. In this example, the first solder resist layer 232 defines a first outer surface 234 (e.g., the uppermost surface) of the package substrate 200. That is, the solder resist layer 232 defines the die mounting surface 122 of the package substrate 110 of
In some examples, first and second contacts 240, 242 are provided along the first and second solder resist layers 232, 236 and are electrically coupled to the TGVs 222. In this example, the first contacts 240 along the first solder resist layer 232 correspond to the contacts 120 of
As shown in
In some examples, once the different glass core assemblies 602, 604, 606 are brought together (as represented in
In this example, the first glass core 206 of the uppermost glass core assembly 802 in
In some examples, once the different glass core assemblies 700, 802, 804 are brought together (as represented in
The stage of fabrication represented in
In some examples, the dielectric layer 902 is added through a lamination process. Thereafter, the contact pads 904 and additional contacts 906 are added by drilling holes through the dielectric layer 902 and then filling the holes with metal and adding additional metal overtop of the outer surface of the dielectric layer 902. In some examples, the lamination of the dielectric layer 902 results in gaps surrounding the interconnect bridge 230 within the cavity 228 being filled. That is, in some examples, the same material used in the dielectric layer 902 laterally encloses (e.g., at least partially surrounds) the interconnect bridge 230. In some examples, a separate dielectric material is added to fill the cavity 228 around the interconnect bridge 230 prior to the addition of the dielectric layer 902 across the top of the interconnect bridge 230. In some such examples, the dielectric material in the cavity 228 is the same as the material used for the dielectric layer 902 above the interconnect bridge 230. In other examples, different dielectric materials can be used in the cavity 228 and above the interconnect bridge 230. Further, in some examples, one or both of the dielectric materials surrounding the interconnect bridge 230 within the cavity and overtop of the interconnect bridge he material in the dielectric layer 902 may be the same as the dielectric material 220 between the glass cores 206, 208, 210, 212, 214. In other examples, the dielectric material 220 between the glass cores 206, 208, 210, 212, 214 is different than the dielectric materials in contact with the lateral sides and top of the interconnect bridge 230.
The example method of
At block 1204, the example method involves determining whether to embed an interconnect bridge in the glass core. If so, the method advances to block 1206 where a cavity within the glass core is provided (e.g., as discussed above in connection with
At block 1208, the example method involves adding TGVs (e.g., the TGVs 222) through the glass core (e.g., as discussed in connection with
At block 1210, the example method involves depositing an adhesive resin (e.g., the dielectric material 220) onto one or both of the outer surfaces of the glass core (e.g., as described in connection with
At block 1214, the example method involves determining whether to fabricate another glass core. If so, the method returns to block 1202 to repeat the process for a different glass core. In some examples, the different glass core can be constructed with a different CTE. In some examples, the next glass core is fabricated independent of the previously fabricated glass core. Accordingly, in some examples, separate iterations through the example process can be performed in parallel rather than sequentially.
Once there are no further glass cores to fabricate, the example method advances to block 1216 that involves combining the glass cores. In some examples, the adhesive resin (added at block 1210) is used to attach the different glass cores together (e.g., as discussed in connection with
At block 1218, the example method involves placing an interconnect within the cavity (e.g., the cavity made in at least one glass core at block 1206). At block 1220, the example method involves determining whether to add build-up regions (e.g., the build-up regions 130, 131, 204 of
At block 1224, the example method involves completing the package substrate. In some examples, this includes adding solder resist layers (e.g., the solder resist layers 232, 236 discussed in connection with
The example IC package 100 disclosed herein (including any one of the example package substrates 110, 200, 1100) may be included in any suitable electronic component.
The IC device 1400 may include one or more device layers 1404 disposed on and/or above the die substrate 1402. The device layer 1404 may include features of one or more transistors 1440 (e.g., metal oxide semiconductor field-effect transistors (MOSFETs)) formed on the die substrate 1402. The device layer 1404 may include, for example, one or more source and/or drain (S/D) regions 1420, a gate 1422 to control current flow between the S/D regions 1420, and one or more S/D contacts 1424 to route electrical signals to/from the S/D regions 1420. The transistors 1440 may include additional features not depicted for the sake of clarity, such as device isolation regions, gate contacts, and the like. The transistors 1440 are not limited to the type and configuration depicted in
Each transistor 1440 may include a gate 1422 including a gate dielectric and a gate electrode. The gate dielectric may include one layer or a stack of layers. The one or more layers may include silicon oxide, silicon dioxide, silicon carbide, and/or a high-k dielectric material. The high-k dielectric material may include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and/or zinc. Examples of high-k materials that may be used in the gate dielectric include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and/or lead zinc niobate. In some examples, an annealing process may be carried out on the gate dielectric to improve its quality when a high-k material is used.
The gate electrode may be formed on the gate dielectric and may include at least one p-type work function metal or n-type work function metal, depending on whether the transistor 1440 is to be a p-type metal oxide semiconductor (PMOS) or an n-type metal oxide semiconductor (NMOS) transistor. In some implementations, the gate electrode may include a stack of two or more metal layers, where one or more metal layers are work function metal layers and at least one metal layer is a fill metal layer. Further metal layers may be included, such as a barrier layer. For a PMOS transistor, metals that may be used for the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, conductive metal oxides (e.g., ruthenium oxide), and/or any of the metals discussed below with reference to an NMOS transistor (e.g., for work function tuning). For an NMOS transistor, metals that may be used for the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, carbides of these metals (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and/or aluminum carbide), and/or any of the metals discussed above with reference to a PMOS transistor (e.g., for work function tuning).
In some examples, when viewed as a cross-section of the transistor 1440 along the source-channel-drain direction, the gate electrode may include a U-shaped structure that includes a bottom portion substantially parallel to the surface of the die substrate 1402 and two sidewall portions that are substantially perpendicular to the top surface of the die substrate 1402. In other examples, at least one of the metal layers that form the gate electrode may be a planar layer that is substantially parallel to the top surface of the die substrate 1402 and does not include sidewall portions substantially perpendicular to the top surface of the die substrate 1402. In other examples, the gate electrode may include a combination of U-shaped structures and/or planar, non-U-shaped structures. For example, the gate electrode may include one or more U-shaped metal layers formed atop one or more planar, non-U-shaped layers.
In some examples, a pair of sidewall spacers may be formed on opposing sides of the gate stack to bracket the gate stack. The sidewall spacers may be formed from materials such as silicon nitride, silicon oxide, silicon carbide, silicon nitride doped with carbon, and/or silicon oxynitride. Processes for forming sidewall spacers are well known in the art and generally include deposition and etching process operations. In some examples, a plurality of spacer pairs may be used; for instance, two pairs, three pairs, or four pairs of sidewall spacers may be formed on opposing sides of the gate stack.
The S/D regions 1420 may be formed within the die substrate 1402 adjacent to the gate 1422 of corresponding transistor(s) 1440. The S/D regions 1420 may be formed using an implantation/diffusion process or an etching/deposition process, for example. In the former process, dopants such as boron, aluminum, antimony, phosphorous, or arsenic may be ion-implanted into the die substrate 1402 to form the S/D regions 1420. An annealing process that activates the dopants and causes them to diffuse farther into the die substrate 1402 may follow the ion-implantation process. In the latter process, the die substrate 1402 may first be etched to form recesses at the locations of the S/D regions 1420. An epitaxial deposition process may then be carried out to fill the recesses with material that is used to fabricate the S/D regions 1420. In some implementations, the S/D regions 1420 may be fabricated using a silicon alloy such as silicon germanium or silicon carbide. In some examples, the epitaxially deposited silicon alloy may be doped in situ with dopants such as boron, arsenic, or phosphorous. In some examples, the S/D regions 1420 may be formed using one or more alternate semiconductor materials such as germanium or a group III-V material or alloy. In further examples, one or more layers of metal and/or metal alloys may be used to form the S/D regions 1420.
Electrical signals, such as power and/or input/output (I/O) signals, may be routed to and/or from the devices (e.g., transistors 1440) of the device layer 1404 through one or more interconnect layers disposed on the device layer 1404 (illustrated in
The interconnect structures 1428 may be arranged within the interconnect layers 1406-2010 to route electrical signals according to a wide variety of designs (in particular, the arrangement is not limited to the particular configuration of interconnect structures 1428 depicted in
In some examples, the interconnect structures 1428 may include lines 1428a and/or vias 1428b filled with an electrically conductive material such as a metal. The lines 1428a may be arranged to route electrical signals in a direction of a plane that is substantially parallel with a surface of the die substrate 1402 upon which the device layer 1404 is formed. For example, the lines 1428a may route electrical signals in a direction in and/or out of the page from the perspective of
The interconnect layers 1406-2010 may include a dielectric material 1426 disposed between the interconnect structures 1428, as shown in
A first interconnect layer 1406 (referred to as Metal 1 or “M1”) may be formed directly on the device layer 1404. In some examples, the first interconnect layer 1406 may include lines 1428a and/or vias 1428b, as shown. The lines 1428a of the first interconnect layer 1406 may be coupled with contacts (e.g., the S/D contacts 1424) of the device layer 1404.
A second interconnect layer 1408 (referred to as Metal 2 or “M2”) may be formed directly on the first interconnect layer 1406. In some examples, the second interconnect layer 1408 may include vias 1428b to couple the lines 1428a of the second interconnect layer 1408 with the lines 1428a of the first interconnect layer 1406. Although the lines 1428a and the vias 1428b are structurally delineated with a line within each interconnect layer (e.g., within the second interconnect layer 1408) for the sake of clarity, the lines 1428a and the vias 1428b may be structurally and/or materially contiguous (e.g., simultaneously filled during a dual-damascene process) in some examples.
A third interconnect layer 1410 (referred to as Metal 3 or “M3”) (and additional interconnect layers, as desired) may be formed in succession on the second interconnect layer 1408 according to similar techniques and/or configurations described in connection with the second interconnect layer 1408 or the first interconnect layer 1406. In some examples, the interconnect layers that are “higher up” in the metallization stack 1419 in the IC device 1400 (i.e., further away from the device layer 1404) may be thicker.
The IC device 1400 may include a solder resist material 1434 (e.g., polyimide or similar material) and one or more conductive contacts 1436 formed on the interconnect layers 1406-2010. In
In some examples, the circuit board 1502 may be a printed circuit board (PCB) including multiple metal layers separated from one another by layers of dielectric material and interconnected by electrically conductive vias. Any one or more of the metal layers may be formed in a desired circuit pattern to route electrical signals (optionally in conjunction with other metal layers) between the components coupled to the circuit board 1502. In other examples, the circuit board 1502 may be a non-PCB substrate.
The IC device assembly 1500 illustrated in
The package-on-interposer structure 1536 may include an IC package 1520 coupled to an interposer 1504 by coupling components 1518. The coupling components 1518 may take any suitable form for the application, such as the forms discussed above with reference to the coupling components 1516. Although a single IC package 1520 is shown in
In some examples, the interposer 1504 may be formed as a PCB, including multiple metal layers separated from one another by layers of dielectric material and interconnected by electrically conductive vias. In some examples, the interposer 1504 may be formed of an epoxy resin, a fiberglass-reinforced epoxy resin, an epoxy resin with inorganic fillers, a ceramic material, or a polymer material such as polyimide. In some examples, the interposer 1504 may be formed of alternate rigid or flexible materials that may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other group III-V and group IV materials. The interposer 1504 may include metal interconnects 1508 and vias 1510, including but not limited to through-silicon vias (TSVs) 1506. The interposer 1504 may further include embedded devices 1514, including both passive and active devices. Such devices may include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices. More complex devices such as radio frequency devices, power amplifiers, power management devices, antennas, arrays, sensors, and microelectromechanical systems (MEMS) devices may also be formed on the interposer 1504. The package-on-interposer structure 1536 may take the form of any of the package-on-interposer structures known in the art.
The IC device assembly 1500 may include an IC package 1524 coupled to the first face 1540 of the circuit board 1502 by coupling components 1522. The coupling components 1522 may take the form of any of the examples discussed above with reference to the coupling components 1516, and the IC package 1524 may take the form of any of the examples discussed above with reference to the IC package 1520.
The IC device assembly 1500 illustrated in
Additionally, in various examples, the electrical device 1600 may not include one or more of the components illustrated in
The electrical device 1600 may include programmable circuitry 1602 (e.g., one or more processing devices). The programmable circuitry 1602 may include one or more digital signal processors (DSPs), application-specific integrated circuits (ASICs), central processing units (CPUs), graphics processing units (GPUs), cryptoprocessors (specialized processors that execute cryptographic algorithms within hardware), server processors, or any other suitable processing devices. The electrical device 1600 may include a memory 1604, which may itself include one or more memory devices such as volatile memory (e.g., dynamic random access memory (DRAM)), nonvolatile memory (e.g., read-only memory (ROM)), flash memory, solid state memory, and/or a hard drive. In some examples, the memory 1604 may include memory that shares a die with the programmable circuitry 1602. This memory may be used as cache memory and may include embedded dynamic random access memory (eDRAM) or spin transfer torque magnetic random access memory (STT-MRAM).
In some examples, the electrical device 1600 may include a communication chip 1612 (e.g., one or more communication chips). For example, the communication chip 1612 may be configured for managing wireless communications for the transfer of data to and from the electrical device 1600. The term “wireless” and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a nonsolid medium. The term does not imply that the associated devices do not contain any wires, although in some examples they might not.
The communication chip 1612 may implement any of a number of wireless standards or protocols, including but not limited to Institute for Electrical and Electronic Engineers (IEEE) standards including Wi-Fi (IEEE 802.11 family), IEEE 802.16 standards (e.g., IEEE 802.16-2005 Amendment), Long-Term Evolution (LTE) project along with any amendments, updates, and/or revisions (e.g., advanced LTE project, ultra mobile broadband (UMB) project (also referred to as “3GPP2”), etc.). IEEE 802.16 compatible Broadband Wireless Access (BWA) networks are generally referred to as WiMAX networks, an acronym that stands for Worldwide Interoperability for Microwave Access, which is a certification mark for products that pass conformity and interoperability tests for the IEEE 802.16 standards. The communication chip 1612 may operate in accordance with a Global System for Mobile Communication (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE network. The communication chip 1612 may operate in accordance with Enhanced Data for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). The communication chip 1612 may operate in accordance with Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution-Data Optimized (EV-DO), and derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The communication chip 1612 may operate in accordance with other wireless protocols in other examples. The electrical device 1600 may include an antenna 1622 to facilitate wireless communications and/or to receive other wireless communications (such as AM or FM radio transmissions).
In some examples, the communication chip 1612 may manage wired communications, such as electrical, optical, or any other suitable communication protocols (e.g., the Ethernet). As noted above, the communication chip 1612 may include multiple communication chips. For instance, a first communication chip 1612 may be dedicated to shorter-range wireless communications such as Wi-Fi or Bluetooth, and a second communication chip 1612 may be dedicated to longer-range wireless communications such as global positioning system (GPS), EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, or others. In some examples, a first communication chip 1612 may be dedicated to wireless communications, and a second communication chip 1612 may be dedicated to wired communications.
The electrical device 1600 may include battery/power circuitry 1614. The battery/power circuitry 1614 may include one or more energy storage devices (e.g., batteries or capacitors) and/or circuitry for coupling components of the electrical device 1600 to an energy source separate from the electrical device 1600 (e.g., AC line power).
The electrical device 1600 may include a display 1606 (or corresponding interface circuitry, as discussed above). The display 1606 may include any visual indicators, such as a heads-up display, a computer monitor, a projector, a touchscreen display, a liquid crystal display (LCD), a light-emitting diode display, or a flat panel display.
The electrical device 1600 may include an audio output device 1608 (or corresponding interface circuitry, as discussed above). The audio output device 1608 may include any device that generates an audible indicator, such as speakers, headsets, or earbuds.
The electrical device 1600 may include an audio input device 1618 (or corresponding interface circuitry, as discussed above). The audio input device 1618 may include any device that generates a signal representative of a sound, such as microphones, microphone arrays, or digital instruments (e.g., instruments having a musical instrument digital interface (MIDI) output).
The electrical device 1600 may include GPS circuitry 1616. The GPS circuitry 1616 may be in communication with a satellite-based system and may receive a location of the electrical device 1600, as known in the art.
The electrical device 1600 may include any other output device 1610 (or corresponding interface circuitry, as discussed above). Examples of the other output device 1610 may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or an additional storage device.
The electrical device 1600 may include any other input device 1620 (or corresponding interface circuitry, as discussed above). Examples of the other input device 1620 may include an accelerometer, a gyroscope, a compass, an image capture device, a keyboard, a cursor control device such as a mouse, a stylus, a touchpad, a bar code reader, a Quick Response (QR) code reader, any sensor, or a radio frequency identification (RFID) reader.
The electrical device 1600 may have any desired form factor, such as a hand-held or mobile electrical device (e.g., a cell phone, a smart phone, a mobile internet device, a music player, a tablet computer, a laptop computer, a netbook computer, an ultrabook computer, a personal digital assistant (PDA), an ultra mobile personal computer, etc.), a desktop electrical device, a server or other networked computing component, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a vehicle control unit, a digital camera, a digital video recorder, or a wearable electrical device. In some examples, the electrical device 1600 may be any other electronic device that processes data.
“Including” and “comprising” (and all forms and tenses thereof) are used herein to be open ended terms. Thus, whenever a claim employs any form of “include” or “comprise” (e.g., comprises, includes, comprising, including, having, etc.) as a preamble or within a claim recitation of any kind, it is to be understood that additional elements, terms, etc., may be present without falling outside the scope of the corresponding claim or recitation. As used herein, when the phrase “at least” is used as the transition term in, for example, a preamble of a claim, it is open-ended in the same manner as the term “comprising” and “including” are open ended. The term “and/or” when used, for example, in a form such as A, B, and/or C refers to any combination or subset of A, B, C such as (1) A alone, (2) B alone, (3) C alone, (4) A with B, (5) A with C, (6) B with C, or (7) A with B and with C. As used herein in the context of describing structures, components, items, objects and/or things, the phrase “at least one of A and B” is intended to refer to implementations including any of (1) at least one A, (2) at least one B, or (3) at least one A and at least one B. Similarly, as used herein in the context of describing structures, components, items, objects and/or things, the phrase “at least one of A or B” is intended to refer to implementations including any of (1) at least one A, (2) at least one B, or (3) at least one A and at least one B. As used herein in the context of describing the performance or execution of processes, instructions, actions, activities, etc., the phrase “at least one of A and B” is intended to refer to implementations including any of (1) at least one A, (2) at least one B, or (3) at least one A and at least one B. Similarly, as used herein in the context of describing the performance or execution of processes, instructions, actions, activities, etc., the phrase “at least one of A or B” is intended to refer to implementations including any of (1) at least one A, (2) at least one B, or (3) at least one A and at least one B.
As used herein, singular references (e.g., “a”, “an”, “first”, “second”, etc.) do not exclude a plurality. The term “a” or “an” object, as used herein, refers to one or more of that object. The terms “a” (or “an”), “one or more”, and “at least one” are used interchangeably herein. Furthermore, although individually listed, a plurality of means, elements, or actions may be implemented by, e.g., the same entity or object. Additionally, although individual features may be included in different examples or claims, these may possibly be combined, and the inclusion in different examples or claims does not imply that a combination of features is not feasible and/or advantageous.
As used herein, unless otherwise stated, the term “above” describes the relationship of two parts relative to Earth. A first part is above a second part, if the second part has at least one part between Earth and the first part. Likewise, as used herein, a first part is “below” a second part when the first part is closer to the Earth than the second part. As noted above, a first part can be above or below a second part with one or more of: other parts therebetween, without other parts therebetween, with the first and second parts touching, or without the first and second parts being in direct contact with one another.
Notwithstanding the foregoing, in the case of referencing a semiconductor device (e.g., a transistor), a semiconductor die containing a semiconductor device, and/or an integrated circuit (IC) package containing a semiconductor die during fabrication or manufacturing, “above” is not with reference to Earth, but instead is with reference to an underlying substrate on which relevant components are fabricated, assembled, mounted, supported, or otherwise provided. Thus, as used herein and unless otherwise stated or implied from the context, a first component within a semiconductor die (e.g., a transistor or other semiconductor device) is “above” a second component within the semiconductor die when the first component is farther away from a substrate (e.g., a semiconductor wafer) during fabrication/manufacturing than the second component on which the two components are fabricated or otherwise provided. Similarly, unless otherwise stated or implied from the context, a first component within an IC package (e.g., a semiconductor die) is “above” a second component within the IC package during fabrication when the first component is farther away from a printed circuit board (PCB) to which the IC package is to be mounted or attached. It is to be understood that semiconductor devices are often used in orientation different than their orientation during fabrication. Thus, when referring to a semiconductor device (e.g., a transistor), a semiconductor die containing a semiconductor device, and/or an integrated circuit (IC) package containing a semiconductor die during use, the definition of “above” in the preceding paragraph (i.e., the term “above” describes the relationship of two parts relative to Earth) will likely govern based on the usage context.
As used in this patent, stating that any part (e.g., a layer, film, area, region, or plate) is in any way on (e.g., positioned on, located on, disposed on, or formed on, etc.) another part, indicates that the referenced part is either in contact with the other part, or that the referenced part is above the other part with one or more intermediate part(s) located therebetween.
As used herein, connection references (e.g., attached, coupled, connected, and joined) may include intermediate members between the elements referenced by the connection reference and/or relative movement between those elements unless otherwise indicated. As such, connection references do not necessarily infer that two elements are directly connected and/or in fixed relation to each other. As used herein, stating that any part is in “contact” with another part is defined to mean that there is no intermediate part between the two parts.
Unless specifically stated otherwise, descriptors such as “first,” “second,” “third,” etc., are used herein without imputing or otherwise indicating any meaning of priority, physical order, arrangement in a list, and/or ordering in any way, but are merely used as labels and/or arbitrary names to distinguish elements for ease of understanding the disclosed examples. In some examples, the descriptor “first” may be used to refer to an element in the detailed description, while the same element may be referred to in a claim with a different descriptor such as “second” or “third.” In such instances, it should be understood that such descriptors are used merely for identifying those elements distinctly within the context of the discussion (e.g., within a claim) in which the elements might, for example, otherwise share a same name.
As used herein, “approximately” and “about” modify their subjects/values to recognize the potential presence of variations that occur in real world applications. For example, “approximately” and “about” may modify dimensions that may not be exact due to manufacturing tolerances and/or other real world imperfections as will be understood by persons of ordinary skill in the art. For example, “approximately” and “about” may indicate such dimensions may be within a tolerance range of +/−10% unless otherwise specified herein.
As used herein “substantially real time” refers to occurrence in a near instantaneous manner recognizing there may be real world delays for computing time, transmission, etc. Thus, unless otherwise specified, “substantially real time” refers to real time+1 second.
As used herein, the phrase “in communication,” including variations thereof, encompasses direct communication and/or indirect communication through one or more intermediary components, and does not require direct physical (e.g., wired) communication and/or constant communication, but rather additionally includes selective communication at periodic intervals, scheduled intervals, aperiodic intervals, and/or one-time events.
As used herein, “programmable circuitry” is defined to include (i) one or more special purpose electrical circuits (e.g., an application specific circuit (ASIC)) structured to perform specific operation(s) and including one or more semiconductor-based logic devices (e.g., electrical hardware implemented by one or more transistors), and/or (ii) one or more general purpose semiconductor-based electrical circuits programmable with instructions to perform specific functions(s) and/or operation(s) and including one or more semiconductor-based logic devices (e.g., electrical hardware implemented by one or more transistors). Examples of programmable circuitry include programmable microprocessors such as Central Processor Units (CPUs) that may execute first instructions to perform one or more operations and/or functions, Field Programmable Gate Arrays (FPGAs) that may be programmed with second instructions to cause configuration and/or structuring of the FPGAs to instantiate one or more operations and/or functions corresponding to the first instructions, Graphics Processor Units (GPUs) that may execute first instructions to perform one or more operations and/or functions, Digital Signal Processors (DSPs) that may execute first instructions to perform one or more operations and/or functions, XPUs, Network Processing Units (NPUs) one or more microcontrollers that may execute first instructions to perform one or more operations and/or functions and/or integrated circuits such as Application Specific Integrated Circuits (ASICs). For example, an XPU may be implemented by a heterogeneous computing system including multiple types of programmable circuitry (e.g., one or more FPGAs, one or more CPUs, one or more GPUs, one or more NPUs, one or more DSPs, etc., and/or any combination(s) thereof), and orchestration technology (e.g., application programming interface(s) (API(s)) that may assign computing task(s) to whichever one(s) of the multiple types of programmable circuitry is/are suited and available to perform the computing task(s).
As used herein integrated circuit/circuitry is defined as one or more semiconductor packages containing one or more circuit elements such as transistors, capacitors, inductors, resistors, current paths, diodes, etc. For example an integrated circuit may be implemented as one or more of an ASIC, an FPGA, a chip, a microchip, programmable circuitry, a semiconductor substrate coupling multiple circuit elements, a system on chip (SoC), etc.
From the foregoing, it will be appreciated that example systems, apparatus, articles of manufacture, and methods have been disclosed that involve package substrates that include substrate cores containing a stack of discrete glass layers or glass cores having different CTEs. The different CTEs define a CTE gradient that reduces stress within package substrates and, specifically, mitigates against seware failures that are known to arise in substrate with a single, solid glass core with a single CTE. As a result, examples disclosed herein improve yield loss in the fabrication of package substrates and also improve the reliability and/or useful life of IC packages relative to known techniques. Furthermore, examples disclosed herein include an interconnect bridge embedded within such substrate cores (e.g., within one or more glass layer in the stack of glass cores). Embedding an interconnect bridge with a glass core can provide die-to-die interconnects without the need for a thick build-up region on top of the package substrate. Reducing and/or eliminating the need for a build-up region outside of the substrate core is achieved by metallization between the different layers in the stack of glass cores that functions as redistribution layers for the package substrate.
Further examples and combinations thereof include the following:
Example 1 includes a substrate for in integrated circuit package, the substrate comprising a first glass layer having a cavity defined therein, a second glass layer different from the first glass layer, and an interconnect bridge at least partially in the cavity, the interconnect bridge to electrically couple a first semiconductor die to a second semiconductor die.
Example 2 includes the substrate of example 1, wherein the first glass layer has a first coefficient of thermal expansion (CTE), and the second glass layer has a second CTE, the second CTE different from the first CTE.
Example 3 includes the substrate of example 2, further including a third glass layer having a third CTE.
Example 4 includes the substrate of any one of examples 1-3, wherein the interconnect bridge includes silicon.
Example 5 includes the substrate of any one of examples 1-4, wherein first glass layer is closer to the first semiconductor die than the second glass layer is to the first semiconductor die, and the interconnect bridge includes a through-silicon via to electrically connect the first semiconductor die to a through-glass via in the second glass layer.
Example 6 includes the substrate of any one of examples 1-5, wherein first glass layer has a first surface that faces toward the first semiconductor die, and the interconnect bridge has a second surface that faces toward the first semiconductor die, the second surface substantially flush with the first surface.
Example 7 includes the substrate of any one of examples 1-6, wherein first glass layer has a first thickness, and the interconnect bridge has a second thickness, the second thickness approximately equal to the first thickness.
Example 8 includes the substrate of any one of examples 1-6, wherein first glass layer has a first thickness, and the interconnect bridge has a second thickness, the second thickness less than the first thickness.
Example 9 includes the substrate of any one of examples 1-6, wherein first glass layer has a first thickness, and the interconnect bridge has a second thickness, the second thickness greater than the first thickness.
Example 10 includes the substrate of any one of examples 1-9, wherein first glass layer is spaced apart from the second glass layer.
Example 11 includes the substrate of any one of examples 1-10, further including a dielectric material between the first glass layer and the second glass layer.
Example 12 includes the substrate of example 11, wherein the dielectric material has a lower modulus of elasticity than the first glass layer.
Example 13 includes the substrate of any one of examples 11 or 12, further including a redistribution layer including metal within the dielectric material.
Example 14 includes the substrate of any one of examples 1-13, further including a dielectric material within the cavity, the dielectric material to at least partially surround the interconnect bridge.
Example 15 includes an integrated circuit (IC) package comprising a first semiconductor die, a second semiconductor die adjacent the first semiconductor die, a package substrate including a stack of multiple glass layers, and an interconnect die in at least one layer of multiple glass layers, the first semiconductor die electrically coupled to the second semiconductor die through the interconnect die.
Example 16 includes the IC package of example 15, wherein different ones of the glass layers have different coefficients of thermal expansion (CTEs).
Example 17 includes the IC package of example 16, wherein differences in the different CTEs corresponds to incremental changes in CTE across a larger span of CTE values.
Example 18 includes an apparatus comprising a first semiconductor chip, a second semiconductor chip, and a package substrate, the first and second semiconductor chips mounted to the package substrate, the package substrate including distinct glass sheets, and a silicon-based bridge within an opening in at least a first one of the glass sheets, the silicon-based bridge electrically coupling the first and second semiconductor chips.
Example 19 includes the apparatus of example 18, wherein the first one of the glass sheets has a coefficient of thermal expansion (CTE) different from a CTE of a second one of the glass sheets.
Example 20 includes the apparatus of any one of examples 18 or 19, wherein the first one of the glass sheets is separated from a second one of the glass sheets by an intervening layer of dielectric material.
The following claims are hereby incorporated into this Detailed Description by this reference. Although certain example systems, apparatus, articles of manufacture, and methods have been disclosed herein, the scope of coverage of this patent is not limited thereto. On the contrary, this patent covers all systems, apparatus, articles of manufacture, and methods fairly falling within the scope of the claims of this patent.
