Patent Application
20240241446
This disclosure relates generally to semiconductor device fabrication and, more particularly, to methods and apparatus to reduce extreme ultraviolet light for photolithography.
Semiconductor device fabrication includes various processes to manufacture integrated circuits or chips. Many processes involved in semiconductor device fabrication involve the use of photolithography. Photolithography involves the application of light onto a layer of light-sensitive material (e.g., a photoresist, also sometimes referred to simply as a resist) in a controlled manner to produce a pattern in the layer of material in which portions of the layer of material are retained while other portions are removed. Often, the exposure of light onto a photoresist is controlled through the use of a photolithography mask (e.g., a photomask or simply mask) between the light source and the photoresist.
In general, the same reference numbers will be used throughout the drawing(s) and accompanying written description to refer to the same or like parts. The figures are not necessarily to scale. Instead, the thickness of the layers or regions may be enlarged in the drawings. Although the figures show layers and regions with clean lines and boundaries, some or all of these lines and/or boundaries may be idealized. In reality, the boundaries and/or lines may be unobservable, blended, and/or irregular.
Semiconductor manufacturing often employs photolithography to form a pattern of an integrated circuit (IC) chip or printed circuit board. Often, extreme ultraviolet (EUV) light (e.g., ultraviolet light at a wavelength of approximately 13.5 nanometers (nm)) is used during photolithography manufacturing processes. EUV lithography can achieve ultra-fine feature sizes with a single exposure and/or can be used for scaling to even smaller feature sizes as IC chips continue to shrink in size, which surpasses limitations of traditional photolithography. Additionally, EUV lithography increases or improves manufacturing throughput by enabling faster wafer processing, leading to higher productivity. Although EUV lithography provides benefits over photolithography, EUV lithography is an expensive manufacturing process (e.g., the most expensive process) of semiconductor manufacturing. For example, to form a critical dimension (CD) of approximately 30.5 nanometers (nm) on a substrate employing EUV lithography requires approximately 92 millijoules (mJ) of energy.
Examples disclosed herein employ methods and apparatus to reduce a dose of EUV needed during EUV lithography manufacturing process(es). Reducing the dose needed for EUV lithography significantly reduces energy costs, equipment costs and, thus, manufacturing costs. To reduce costs, example methods and apparatus disclosed herein employ a combination of EUV light and ultraviolet light exposure (i.e., a dual-dose exposure) to achieve a critical dimension target during subsequent etching process(es). For example, example methods and apparatus disclosed herein expose a wafer or photoresist layer to an ultraviolet light to sensitize (e.g., alter solubility properties of) the photoresist layer followed by extreme ultraviolet light exposure for patterning the photoresist. Subsequent to the UV and EUV light exposure, a solution (e.g., a developer solution) can be applied to remove portions of the photoresist layer corresponding to a litho-pattern on the photoresist having to a desired critical dimension. Thus, example and apparatus disclosed herein employ a reduced EUV light dose. By applying UV light (e.g., a pre-dose or a post-dose) to a photoresist layer, an EUV dose can be significantly reduced, which can reduce manufacturing costs, increase manufacturing throughput, and/or reduce process/equipment cost.
Specifically, example methods and apparatus disclosed herein expose a wafer having an EUV resist layer or patterning mask (e.g., a chemically amplified resists (CAR)) to both UV light and EUV light. For example, the wafer (e.g., the resist on the wafer) is exposed to the UV light at a first instance in time and the wafer (e.g., the resist on the wafer) is exposed to EUV light at a second instance in time different than the first instance. In this manner, application of the UV light sensitizes (e.g., alters a solubility characteristic of) the resist layer to reduce energy needed by EUV light for patterning the resist layer. Specifically, applying UV light reduces an amount of EUV light exposure needed to pattern the photoresist. For example, to form a critical dimension (CD) of approximately 30.5 nanometers (nm) on a substrate employing a combination of UV light and EUV light requires approximately 55 millijoules (mJ) of energy, which is approximately 35 millijoules (mJ) less than applying solely EUV light (e.g., absent the application of the UV light) for providing the same critical dimension. Thus, application of the UV light reduces the dose of EUV light needed to pattern the photoresist, thereby reducing manufacturing costs. In some examples, the UV light is applied to the wafer (e.g., the resist or mask layer of the wafer) prior to application of the EUV light. In some examples, the EUV light is applied to the wafer (e.g., the resist or mask layer of the wafer) prior to application of the UV light. The order in which the UV light and the EUV light is applied to the wafer does not have a significant or material impact on the final patterning or critical dimension target of a wafer.
Moreover, example methods and apparatus disclosed herein can be employed with EUV resists based on traditional chemically amplified resists (CAR) that are sensitive to UV light. In this manner, no special operations and/or materials are needed. Conventional or known EUV resists can be employed and a pattern (e.g., on a photoresist) can be provided based solely on a dual exposure to UV light and EUV light. In other words, example lithography apparatus disclosed herein can pattern a photoresist based on combination of UV/EUV without all the complexity of special operations and materials (i.e., a specially designed resist that includes a photoacid generator, a photo sensitizer, and a photo-base generator). Thus, example methods and apparatus disclosed herein significantly simply lithography manufacturing and significantly reduce manufacturing costs.
In some instances, the underlying substrate 106 corresponds to a portion of an IC package. More particularly, in some instances, the underlying substrate 106 corresponds to a particular layer within a semiconductor die (e.g., an IC chip or chiplet) within the IC package, a particular layer within a package substrate for the IC package, and/or any other suitable substrate. Example semiconductor dies or chiplets (e.g., tiles) provided by the examples disclosed herein can implement controllers, microprocessors, Digital Signal Processors (DSPs), Central Processor Units (CPUs), Graphics Processor Units (GPUs), programmed microprocessors, Field Programmable Gate Arrays (FPGAs), Application Specific Integrated Circuits (ASICs), Reduced Instruction Set Computers (RISCs), any other circuitry and/or combinations thereof. Additionally, example semiconductor dies can be chiplets of a disaggregated die. Each chiplet (also referred to as a tile) may implement a dedicated function. Together, the chiplets may implement a complex circuitry. The complex circuitry can be any type of device that can be implemented as a plurality of chiplets that are physically separated from, but communicatively coupled to, one another. For example, processor circuitry may be implemented by two or more separate chiplets that together implement a microprocessor, etc. Alternatively, in other examples, example semiconductor dies may be different chips (e.g., a processor circuitry, a memory, and/or or some other type of component) that together implement a system on a chip (SoC) in a semiconductor package.
To provide a pattern corresponding to circuitry of the substrate 106, the photoresist 104 is patterned to define openings (e.g., formed in a later process) in the photoresist 104 that can then be used as a mask to create corresponding openings in the underlying substrate 106 (e.g., through an etching process that removes portions of the underlying substrate exposed through the openings in the photoresist 104). In some instances, instead of removing portions of the underlying substrate 106 exposed through the openings in the photoresist 104, the openings in the photoresist 104 can be filled with a material to be added onto the underlying substrate 106 at the locations defined by the openings. In some instances, the photoresist 104 is removed after subsequent processing associated with the use of the patterned openings have been completed. In other instances, the photoresist 104 is retained on the underlying substrate 106 and remains as part of the final product (e.g., some portion of an IC package).
To provide the lithography patterning on the substrate 106, the lithography apparatus 100 disclosed herein exposes the wafer 102 (e.g., the substrate 106 and/or the photoresist 104) to an ultraviolet (UV) light 108 and an extreme ultraviolet (EUV) light 110. For example, the UV light 108 can have a wavelength in the range of 100s of nanometers (nm) depending on the technique used to produce the UV light 108 (e.g., approximately, 248 nm (KrF), approximately 365 nm (i-line light), approximately 405 nm (g-line light), approximately 435 nm (h-line light), etc.) and the EUV light 110 can have a wavelength that is significantly shorter (e.g., approximately 13.5 nm). To provide the UV light 108, the example lithography apparatus 100 includes an example ultraviolet (UV) source 112 (e.g., a UV applicator, a UV light source, a UV station). To provide the EUV light 110, the example lithography apparatus 100 includes an example extreme ultraviolet (EUV) source 114 (e.g., an EUV applicator, a EUV station, an EUV light source, etc.).
In the illustrated example, the UV source 112 provides a pre-dosing of ultraviolet (UV) light on the photoresist 104 and the EUV source 114 provides a patterned exposure on portions of the photoresist 104 exposed to the EUV light to create (e.g., finalize) a pattern of openings (e.g., a lithography pattern) on the photoresist 104 (e.g., using a reduced EUV dose relative to what would otherwise be needed in the absence of the pre-dosing of the UV light). However, in some examples, the EUV source 114 and the UV source 112 can be reversed (see, for example,
As used herein, to sensitize the photoresist 104 means to change a solubility characteristic of the photoresist 104. For example, the photoresist 104 can be a positive photoresist or a negative photoresist. In a positive photoresist, the UV light 108 and the EUV light 110 weaken exposed areas of the photoresist 104, thereby increasing solubility characteristics of the exposed areas of the photoresist 104 in a developer solution (e.g., the developer solution dissolves the exposed areas leaving a pattern of non-exposed areas where the mask was placed). In a negative photoresist, the UV light 108 and the EUV light 110 strengthen (e.g., polymerizing or cross-linking) exposed areas of the photoresist 104, thereby making the exposed areas insoluble in a developer solution (e.g., the developer solution dissolves away only the areas that were not exposed to the UV light 108 and the EUV light 110, leaving a pattern where the mask was not placed). Thus, depending on type of photoresist material, exposing the photoresist 104 to the UV light 108 can weaken (e.g., soften) or harden the photoresist 104.
Resist materials defining the photoresist 104 can be different types of EUV resist materials based on traditional chemically amplified resists (CAR) that are sensitive to UV light in addition to EUV light. Thus, conventional or known resist materials can be employed. Some example photoresist materials that can be used include, but not limited to, diazo-naphthoquinone (DNQ), metal containing resists such as, for example, hafnium oxide nanoparticles, zirconium oxide nanoparticles, hafnium-based photoresists, and/or any other suitable material(s).
To expose the wafer 102 to the UV light 108, the UV source 112 of the illustrated example includes a UV light source 116 that provides the UV light 108 (e.g., wavelengths of 100s nanometers (nm) (e.g., 365 nm, 405 nm, 435 nm, etc.)). The UV light source 116 can be a flood light, an UV LED, vapor light, fluorescent light, a halogen light, and/or any other light or bulb that emits ultraviolet light. The UV light source 116 of the UV source 112 emits, disperses, or otherwise scatters (e.g., a first dose of) the UV light 108 directed at the photoresist 104 after the photoresist 104 is layered on the substrate 106. Specifically, the UV light 108 provided by the UV source 112 of the illustrated example is applied across a surface 104a (e.g., an entire surface area or upper surface) of the photoresist 104. In some instances, the UV light 108 is spread uniformly (e.g., evenly distributed) across the surface 104a. That is, in some examples, the photoresist 104 is exposed to the UV light 108 without a mask positioned between the light source 116 and the photoresist 104. In some examples, the UV light 108 is spread in a non-unform pattern across the surface 104a of the photoresist 104. In some examples, the UV light 108 (e.g., a first dose of UV light) is a flood exposure (e.g., provided by a flood light). Additionally, the UV source 112 of the illustrated example exposes the photoresist 104 to the UV light 108 prior to the EUV source 114 exposing the photoresist 104 with the EUV light 110. Thus, the UV source 112 of the illustrated example provides a pre-dose of the UV light 108 on the photoresist 104. Providing a pre-dose of the UV light 108 sensitizes (e.g., softens, weakens, or hardens) the photoresist 104. As a result, a lower dose of the EUV light 110 is needed to provide a pattern of openings (e.g., a lithography pattern) on the wafer 102 (e.g., with a desired critical dimension target). Thus, because the photoresist 104 of the illustrated example is sensitive to light, the UV light 108 provided by the UV source 112 provides structural changes to (e.g., alters solubility characteristics of) the photoresist 104 (e.g., exposure to light either softens or hardens the photoresist 104). Although the UV light 108 provided by the UV source 112 changes or alters a physical characteristic of the photoresist 104, the UV light 108 does not pattern the openings on the photoresist 104. That is, in some examples, the changes or alterations to the photoresist 104 caused by the pre-dose of the UV light 108 are insufficient by themselves to result in the removal of any portion(s) of the photoresist 104 when a developer solution is applied. However, the UV light 108 enables a reduced dose of the EUV light 110 needed to be applied to the photoresist 104 to affect sufficient changes or alterations to the photoresist 104 to be patterned with portion(s) removed during a development process. Thus, the UV light 108 contributes to achieving (e.g., in combination with the EUV light 110) a desired critical dimension (CD) of the pattern openings on the photoresist 104. In other words, the combination of the EUV light 110 and UV light 108 exposure to the photoresist 104 provides or establishes (e.g., a critical dimension target or control of) the pattern (e.g., the pattern openings) of the photoresist 104.
Different wavelengths of the UV light 108 can be evaluated and/or determined for a specific type of resist material defining the photoresist 104. Therefore, different resist materials and/or UV light wavelengths can be used for different applications. After pre-dosing the wafer 102 with the UV light provided by the UV source 112, the wafer 102 is processed by the EUV source 114. Pre-dosing the wafer 102 with the UV light 108 enables the EUV source 114 to provide a pattern of openings on the wafer 102 (e.g., with a target critical dimension) using a lower dose (e.g., lower energy) than processing the wafer 102 without the pre-dose UV light (e.g., to achieve the same critical dimension target).
After the wafer 102 is processed by the UV source 112, a pattern of openings is provided on the photoresist 104 via the EUV source 114. To provide a pattern of openings on the photoresist 104, the EUV source 114 includes an example photomask 120 (or simply mask) to photolithographically pattern the photoresist 104 on the substrate 106. The EUV source 114 of
As shown in
As the EUV light 110 reaches the photomask 120, the absorber 122 absorbs the EUV light 110. The reflective films within the multilayer 124 reflect at least a portion of the EUV light 110 (referred to herein as reflected patterned EUV light 128) that is directed toward the photoresist 104. The reflected patterned EUV light 128 is defined by the pattern of the absorber 122. That is, as shown in
In the illustrated example, the photoresist 104 is a photo-sensitive material such that the portions of the photoresist 104 exposed to the reflected patterned EUV light 128 will react to the light and change characteristics. Specifically, in some instances, the photoresist 104 exposed to light will harden such that when a developer solution is applied to the photoresist 104, the portions that remain relatively soft (e.g., the portions not exposed to the EUV light 110) will be removed while the hardened portions will remain. In this manner the pattern defined by the opaque regions 132 of the absorber 122 on the photomask 120 are transferred to the photoresist 104. In other instances, the portions of the photoresist 104 exposed to the reflected EUV light 128 change so that they remain when a developer solution is applied while the rest of the photoresist 104 is removed. In this manner the pattern defined by the openings 130 in the absorber 122 (e.g., the inverse of the pattern defined by the opaque regions 132) is transferred to the photoresist 104.
In operation, the lithography apparatus 100 of the illustrated example reduces energy use of the EUV source 114. As an example, the lithography apparatus 100 can provide an example critical dimension target of approximately 30.5 nanometers using less energy than would be required without the use of the UV source 112. For example, the EUV source 114 can provide the critical dimension target of approximately 30.5 nanometers using approximately 55 millijoules when pre-dosing the wafer 102 with the UV light 108 provided by the UV source 112. In contrast, the EUV source 114 would require approximately 95 millijoules to provide a critical dimension target of approximately 30.5 nanometers absent the pre-dose of the UV light 108. In other words, employing the UV light 108 in combination with the EUV light 110 enables a dose of EUV light 110 that is between approximately 35 percent and 45 percent (e.g., 40 percent) less to establish a desired critical dimension as a result of the UV light exposure. Additionally, compared to the EUV source 114 (which uses approximately 55 millijoules (mJ)), the UV source 112 uses less energy (e.g., approximately 10 millijoules (mJ)). Moreover, the UV light source 116 employs a light bulb (e.g., a flood light) that is significantly less expensive than a light source of the EUV light source 118 generating the EUV light 110. Thus, the lithography apparatus 100 disclosed herein significantly reduces manufacturing costs, equipment costs, and can provide a higher throughput of wafer production.
Furthermore, the lithography apparatus 100 of the illustrated example can configure the UV source 112 and the EUV source 114 in a single unit or equipment (e.g., a single enclosed housing defining a machine or equipment) and/or in a semiconductor manufacturing track to provide consistent wafer-to-wafer processing times and conditions. Thus, in some examples, the UV source 112 and the EUV source 114 are provided in a single housing or the same housing structure. By providing the UV source 112 and the EUV source 114 in a semiconductor manufacturing track or a link (e.g., as a single manufacturing operating process), the lithography apparatus 100 reduces delay between the UV light application and the EUV light application, thereby providing consistent and/or uniform UV exposure to EUV exposure time and resulting in more consistent wafer output. For example, providing the UV source 112 and the EUV source 114 inside a track enables more consistent exposure time, and/or time between exposures, resulting in more consistent critical dimension and/or critical dimension control. If the UV source 112 is separate from the EUV source 114 requiring transfer of the wafer 102 to the different sources (e.g., separate operating processes), such delay between the pre-dose of UV light and the EUV exposure could be significant and can provide inconsistencies between wafers. For example, separating the pre-dose UV light and the EUV light applications can result in less critical dimension control, resulting in inferior results and/or critical dimension control. Thus, the UV source 112 and the EUV source 114 are to be provided in the semiconductor manufacturing track, where the UV source and the EUV source are linked in the semiconductor manufacturing track to provide steady wafer-to-wafer processing times and conditions. After the EUV source 114 exposes the photoresist 104 to the EUV pattern, the photoresist 104 can be processed by a developer solution to form the pattern provided by the photomask 120. After formation of the pattern, the wafer 102 can be processed using any suitable manufacturing process(es) on the exposed portions of the substrate 106 (e.g., etching the substrate 106, depositing material(s) onto the substrate, etc.) based on the litho-pattern developed by the lithography apparatus 100.
In some examples, the lithography apparatus 100 of
In some examples, the semiconductor manufacturing track 140 can be a unitary system (e.g., a single piece of equipment) with different stations or units within the unitary system to provide the different front-end manufacturing processes including deposition, photoresist, lithography, etching, ion implantation and packaging. In such examples, each of the front-end manufacturing processes (e.g., deposition, photoresist, lithography, etching, ion implantation and packaging) are operatively coupled or interconnected via a track, in which the track moves a wafer (e.g., the wafer 102) between the different stations within the single unit or equipment. In some examples, each of the front-end manufacturing processes (e.g., deposition, photoresist, lithography, etching, ion implantation and packaging) are provided by different or standalone pieces of equipment that are operatively coupled via the track.
In some examples, the lithography apparatus 100 (e.g., the UV source 112 and the EUV source 114) can be used to implement a lithography process in the example semiconductor manufacturing track 140 noted above (e.g., the front-end manufacturing process). For example, the lithography apparatus 100 can be located between the photoresist process and the etching process of the example front-end manufacturing track noted above. Thus, the lithography apparatus 100 of the illustrated example can be located downstream from a photoresist unit or equipment and upstream from an etching unit or equipment.
In some examples, the lithography apparatus 100 of the illustrated example is implemented with example processor circuitry 142 (e.g., a controller, a processor, a microprocessor, etc.). In some examples, the processor circuitry 142 is omitted. The example processor circuitry 142 of the illustrated example can be configured to: identify (e.g. access) data indicating a type of photoresist material of the photoresist, determine a UV dosage and/or EUV dosage needed to pattern the photoresist 104 based on the identified photoresist material, control the UV light source 116 and/or the EUV light source 118 (e.g., an intensity of the UV light and/or the EUV light, and/or duration of exposure to the UV light and/or the EUV light), and/or cause the wafer 102 to move between the UV source 112 and the EUV source 114 and/or to/from the UV source 112, and/or the EUV source 114.
In some examples, the processor circuitry 142 can control or command a transmission system (e.g., a motor) of the semiconductor manufacturing track 140 to move the wafer 102 relative to the lithography apparatus 100. For example, the processor circuitry 142 of the illustrated example can command the semiconductor manufacturing track 140 to convey the wafer 102 from a station (e.g., a photoresist process station) upstream from the lithography apparatus 100 to advance the wafer 102 to the lithography apparatus 100. Likewise, after exposure by the lithography apparatus 100, the controller 142 of the illustrated example can command the semiconductor manufacturing track 140 to convey or advance the wafer 102 from the lithography apparatus 100 (e.g., a photoresist process station) to a station (e.g., an etching station, a baking station, etc.) downstream from the lithography apparatus 100.
In some examples, the processor circuitry 142 of the illustrated example can control a duration and/or intensity of the UV light 108 and/or the EUV light 110 as the wafer 102 is processed by the lithography apparatus 100. For example, the processor circuitry 142 of the illustrated example can be communicatively coupled to the UV light source 116 and the EUV light source 118 and can send a signal (e.g., a current or voltage signal) to adjust (e.g., increase or decrease) an intensity of UV light source 108 and/or an intensity of the EUV light source 110. In some examples, the processor circuitry 142 can command or operate a motor of the semiconductor manufacturing track 140 to control a duration of photoresist exposure to the UV light 108 and/or the EUV light 110.
In some examples, the processor circuitry 142 can be configured to identify or access data (e.g., from a look-up table, memory, photo analysis, etc.) to determine or detect a type of photoresist material and command or control (e.g., adjust a current or voltage to) the UV light source 116 and/or the EUV light source 118 to adjust (e.g., increase or decrease) an intensity (e.g., a brightness) of the UV light 108 and/or the EUV light 110 needed to provide the pattern (e.g., a critical dimension target) on the photoresist layer 104 based on the identified photoresist layer 104. In some examples, the processor circuitry 142 can commend or control operation of a track of the semiconductor manufacturing track 140 to control a duration of exposure to the UV light 108 and/or the EUV light 110 that would be needed to provide the pattern (e.g., a critical dimension target) on the photoresist layer 104 based on the identified photoresist material of the photoresist layer 104.
In some examples, controlling intensity and/or exposure time can provide consistent and/or superior manufacturing results. For example, linking the UV source 112 and the EUV source 114 in a semiconductor manufacturing track provides consistent first dose-to-second dose exposure time to improve wafer-to-wafer processing. In some examples, the processor circuitry 142 can be employed to provide consistent first dose-to-second dose exposure time to improve wafer-to-wafer processing.
The processor circuitry 142 of
Furthermore, the processor circuitry 142 may be implemented by hardware alone or by hardware in combination with software and/or firmware. Thus, for example, the processor circuitry 142, could be implemented by programmable circuitry in combination with machine readable instructions (e.g., firmware or software), processor circuitry, analog circuit(s), digital circuit(s), logic circuit(s), programmable processor(s), programmable microcontroller(s), graphics processing unit(s) (GPU(s)), digital signal processor(s) (DSP(s)), ASIC(s), programmable logic device(s) (PLD(s)), and/or field programmable logic device(s) (FPLD(s)) such as FPGAs.
The lithography apparatus 200 of the illustrated example is substantially similar or identical to the lithography apparatus 100 of
Next, a photoresist layer is applied to the substrate (block 304). For example, referring to
After the photoresist is applied to the substrate at block 304, the photoresist is exposed to an ultraviolet light at a first instance (block 306). For example, referring to
After the photoresist 104 is sensitized by the UV light, the photoresist is exposed to extreme ultraviolet light at a second instance different than the first instance (block 308). For example, referring to
After the photoresist is patterned with a lithography pattern, a pattern is formed on the photoresist (block 310) (e.g., one or more openings are formed in the photoresist). For example, referring to
After pattern formation, the wafer 102 can undergo further processing for producing semiconductor devices. For example, the wafer 102 can continue to undergo further conventional manufacturing processes including, but not limited to, plasma etching, laser drilling, laser etching, polishing, integrated circuit microfabrication processes, wet etching, dry etching, anisotropic etching, spin coating, electroforming or electroplating, laser ablation, sputtering, chemical deposition, plasma deposition, surface modification, injection molding, hot embossing, thermoplastic fusion bonding, low temperature bonding using adhesives, stamping, machining, 3-D printing, laminating, and/or any other processes commonly used for manufacture of semiconductor devices.
In the example method 300 of
The method 300 of
In some such example,
The program may be embodied in instructions (e.g., software and/or firmware) stored on one or more non-transitory computer readable and/or machine readable storage medium such as cache memory, a magnetic-storage device or disk (e.g., a floppy disk, a Hard Disk Drive (HDD), etc.), an optical-storage device or disk (e.g., a Blu-ray disk, a Compact Disk (CD), a Digital Versatile Disk (DVD), etc.), a Redundant Array of Independent Disks (RAID), a register, ROM, a solid-state drive (SSD), SSD memory, non-volatile memory (e.g., electrically erasable programmable read-only memory (EEPROM), flash memory, etc.), volatile memory (e.g., Random Access Memory (RAM) of any type, etc.), and/or any other storage device or storage disk. The instructions of the non-transitory computer readable and/or machine readable medium may program and/or be executed by programmable circuitry located in one or more hardware devices, but the entire program and/or parts thereof could alternatively be executed and/or instantiated by one or more hardware devices other than the programmable circuitry and/or embodied in dedicated hardware. The machine readable instructions may be distributed across multiple hardware devices and/or executed by two or more hardware devices (e.g., a server and a client hardware device). For example, the client hardware device may be implemented by an endpoint client hardware device (e.g., a hardware device associated with a human and/or machine user) or an intermediate client hardware device gateway (e.g., a radio access network (RAN)) that may facilitate communication between a server and an endpoint client hardware device. Similarly, the non-transitory computer readable storage medium may include one or more mediums. Further, although the example program is described with reference to the flowchart(s) illustrated in
The machine readable instructions described herein may be stored in one or more of a compressed format, an encrypted format, a fragmented format, a compiled format, an executable format, a packaged format, etc. Machine readable instructions as described herein may be stored as data (e.g., computer-readable data, machine-readable data, one or more bits (e.g., one or more computer-readable bits, one or more machine-readable bits, etc.), a bitstream (e.g., a computer-readable bitstream, a machine-readable bitstream, etc.), etc.) or a data structure (e.g., as portion(s) of instructions, code, representations of code, etc.) that may be utilized to create, manufacture, and/or produce machine executable instructions. For example, the machine readable instructions may be fragmented and stored on one or more storage devices, disks and/or computing devices (e.g., servers) located at the same or different locations of a network or collection of networks (e.g., in the cloud, in edge devices, etc.). The machine readable instructions may require one or more of installation, modification, adaptation, updating, combining, supplementing, configuring, decryption, decompression, unpacking, distribution, reassignment, compilation, etc., in order to make them directly readable, interpretable, and/or executable by a computing device and/or other machine. For example, the machine readable instructions may be stored in multiple parts, which are individually compressed, encrypted, and/or stored on separate computing devices, wherein the parts when decrypted, decompressed, and/or combined form a set of computer-executable and/or machine executable instructions that implement one or more functions and/or operations that may together form a program such as that described herein.
In another example, the machine readable instructions may be stored in a state in which they may be read by programmable circuitry, but require addition of a library (e.g., a dynamic link library (DLL)), a software development kit (SDK), an application programming interface (API), etc., in order to execute the machine-readable instructions on a particular computing device or other device. In another example, the machine readable instructions may need to be configured (e.g., settings stored, data input, network addresses recorded, etc.) before the machine readable instructions and/or the corresponding program(s) can be executed in whole or in part. Thus, machine readable, computer readable and/or machine readable media, as used herein, may include instructions and/or program(s) regardless of the particular format or state of the machine readable instructions and/or program(s).
The machine readable instructions described herein can be represented by any past, present, or future instruction language, scripting language, programming language, etc. For example, the machine readable instructions may be represented using any of the following languages: C, C++, Java, C#, Perl, Python, JavaScript, HyperText Markup Language (HTML), Structured Query Language (SQL), Swift, etc.
As mentioned above, the example operations of
The programmable circuitry platform 500 of the illustrated example includes programmable circuitry 512. The programmable circuitry 512 of the illustrated example is hardware. For example, the programmable circuitry 512 can be implemented by one or more integrated circuits, logic circuits, FPGAs, microprocessors, CPUs, GPUs, DSPs, and/or microcontrollers from any desired family or manufacturer. The programmable circuitry 512 may be implemented by one or more semiconductor based (e.g., silicon based) devices. In this example, the programmable circuitry 512 implements the UV source 112, EUV source, and/or the lithography apparatus 100, 200.
The programmable circuitry 512 of the illustrated example includes a local memory 513 (e.g., a cache, registers, etc.). The programmable circuitry 512 of the illustrated example is in communication with main memory 514, 516, which includes a volatile memory 514 and a non-volatile memory 516, by a bus 518. The volatile memory 514 may be implemented by Synchronous Dynamic Random Access Memory (SDRAM), Dynamic Random Access Memory (DRAM), RAMBUS® Dynamic Random Access Memory (RDRAM®), and/or any other type of RAM device. The non-volatile memory 516 may be implemented by flash memory and/or any other desired type of memory device. Access to the main memory 514, 516 of the illustrated example is controlled by a memory controller 517. In some examples, the memory controller 517 may be implemented by one or more integrated circuits, logic circuits, microcontrollers from any desired family or manufacturer, or any other type of circuitry to manage the flow of data going to and from the main memory 514, 516.
The programmable circuitry platform 500 of the illustrated example also includes interface circuitry 520. The interface circuitry 520 may be implemented by hardware in accordance with any type of interface standard, such as an Ethernet interface, a universal serial bus (USB) interface, a Bluetooth® interface, a near field communication (NFC) interface, a Peripheral Component Interconnect (PCI) interface, and/or a Peripheral Component Interconnect Express (PCIe) interface.
In the illustrated example, one or more input devices 522 are connected to the interface circuitry 520. The input device(s) 522 permit(s) a user (e.g., a human user, a machine user, etc.) to enter data and/or commands into the programmable circuitry 512. The input device(s) 522 can be implemented by, for example, an audio sensor, a microphone, a camera (still or video), a keyboard, a button, a mouse, a touchscreen, a trackpad, a trackball, an isopoint device, and/or a voice recognition system.
One or more output devices 524 are also connected to the interface circuitry 520 of the illustrated example. The output device(s) 524 can be implemented, for example, by display devices (e.g., a light emitting diode (LED), an organic light emitting diode (OLED), a liquid crystal display (LCD), a cathode ray tube (CRT) display, an in-place switching (IPS) display, a touchscreen, etc.), a tactile output device, a printer, and/or speaker. The interface circuitry 520 of the illustrated example, thus, typically includes a graphics driver card, a graphics driver chip, and/or graphics processor circuitry such as a GPU.
The interface circuitry 520 of the illustrated example also includes a communication device such as a transmitter, a receiver, a transceiver, a modem, a residential gateway, a wireless access point, and/or a network interface to facilitate exchange of data with external machines (e.g., computing devices of any kind) by a network 526. The communication can be by, for example, an Ethernet connection, a digital subscriber line (DSL) connection, a telephone line connection, a coaxial cable system, a satellite system, a beyond-line-of-sight wireless system, a line-of-sight wireless system, a cellular telephone system, an optical connection, etc.
The programmable circuitry platform 500 of the illustrated example also includes one or more mass storage discs or devices 528 to store firmware, software, and/or data. Examples of such mass storage discs or devices 528 include magnetic storage devices (e.g., floppy disk, drives, HDDs, etc.), optical storage devices (e.g., Blu-ray disks, CDs, DVDs, etc.), RAID systems, and/or solid-state storage discs or devices such as flash memory devices and/or SSDs.
The machine readable instructions 532, which may be implemented by the machine readable instructions of
The cores 602 may communicate by a first example bus 604. In some examples, the first bus 604 may be implemented by a communication bus to effectuate communication associated with one(s) of the cores 602. For example, the first bus 604 may be implemented by at least one of an Inter-Integrated Circuit (I2C) bus, a Serial Peripheral Interface (SPI) bus, a PCI bus, or a PCIe bus. Additionally or alternatively, the first bus 604 may be implemented by any other type of computing or electrical bus. The cores 602 may obtain data, instructions, and/or signals from one or more external devices by example interface circuitry 606. The cores 602 may output data, instructions, and/or signals to the one or more external devices by the interface circuitry 606. Although the cores 602 of this example include example local memory 620 (e.g., Level 1 (L1) cache that may be split into an L1 data cache and an L1 instruction cache), the microprocessor 600 also includes example shared memory 610 that may be shared by the cores (e.g., Level 2 (L2 cache)) for high-speed access to data and/or instructions. Data and/or instructions may be transferred (e.g., shared) by writing to and/or reading from the shared memory 610. The local memory 620 of each of the cores 602 and the shared memory 610 may be part of a hierarchy of storage devices including multiple levels of cache memory and the main memory (e.g., the main memory 514, 516 of
Each core 602 may be referred to as a CPU, DSP, GPU, etc., or any other type of hardware circuitry. Each core 602 includes control unit circuitry 614, arithmetic and logic (AL) circuitry (sometimes referred to as an ALU) 616, a plurality of registers 618, the local memory 620, and a second example bus 622. Other structures may be present. For example, each core 602 may include vector unit circuitry, single instruction multiple data (SIMD) unit circuitry, load/store unit (LSU) circuitry, branch/jump unit circuitry, floating-point unit (FPU) circuitry, etc. The control unit circuitry 614 includes semiconductor-based circuits structured to control (e.g., coordinate) data movement within the corresponding core 602. The AL circuitry 616 includes semiconductor-based circuits structured to perform one or more mathematic and/or logic operations on the data within the corresponding core 602. The AL circuitry 616 of some examples performs integer based operations. In other examples, the AL circuitry 616 also performs floating-point operations. In yet other examples, the AL circuitry 616 may include first AL circuitry that performs integer-based operations and second AL circuitry that performs floating-point operations. In some examples, the AL circuitry 616 may be referred to as an Arithmetic Logic Unit (ALU).
The registers 618 are semiconductor-based structures to store data and/or instructions such as results of one or more of the operations performed by the AL circuitry 616 of the corresponding core 602. For example, the registers 618 may include vector register(s), SIMD register(s), general-purpose register(s), flag register(s), segment register(s), machine-specific register(s), instruction pointer register(s), control register(s), debug register(s), memory management register(s), machine check register(s), etc. The registers 618 may be arranged in a bank as shown in
Each core 602 and/or, more generally, the microprocessor 600 may include additional and/or alternate structures to those shown and described above. For example, one or more clock circuits, one or more power supplies, one or more power gates, one or more cache home agents (CHAs), one or more converged/common mesh stops (CMSs), one or more shifters (e.g., barrel shifter(s)) and/or other circuitry may be present. The microprocessor 600 is a semiconductor device fabricated to include many transistors interconnected to implement the structures described above in one or more integrated circuits (ICs) contained in one or more packages.
The microprocessor 600 may include and/or cooperate with one or more accelerators (e.g., acceleration circuitry, hardware accelerators, etc.). In some examples, accelerators are implemented by logic circuitry to perform certain tasks more quickly and/or efficiently than can be done by a general-purpose processor. Examples of accelerators include ASICs and FPGAs such as those discussed herein. A GPU, DSP and/or other programmable device can also be an accelerator. Accelerators may be on-board the microprocessor 600, in the same chip package as the microprocessor 600 and/or in one or more separate packages from the microprocessor 600.
More specifically, in contrast to the microprocessor 600 of
In the example of
In some examples, the binary file is compiled, generated, transformed, and/or otherwise output from a uniform software platform utilized to program FPGAs. For example, the uniform software platform may translate first instructions (e.g., code or a program) that correspond to one or more operations/functions in a high-level language (e.g., C, C++, Python, etc.) into second instructions that correspond to the one or more operations/functions in an HDL. In some such examples, the binary file is compiled, generated, and/or otherwise output from the uniform software platform based on the second instructions. In some examples, the FPGA circuitry 700 of
The FPGA circuitry 700 of
The FPGA circuitry 700 also includes an array of example logic gate circuitry 708, a plurality of example configurable interconnections 710, and example storage circuitry 712. The logic gate circuitry 708 and the configurable interconnections 710 are configurable to instantiate one or more operations/functions that may correspond to at least some of the machine readable instructions of
The configurable interconnections 710 of the illustrated example are conductive pathways, traces, vias, or the like that may include electrically controllable switches (e.g., transistors) whose state can be changed by programming (e.g., using an HDL instruction language) to activate or deactivate one or more connections between one or more of the logic gate circuitry 708 to program desired logic circuits.
The storage circuitry 712 of the illustrated example is structured to store result(s) of the one or more of the operations performed by corresponding logic gates. The storage circuitry 712 may be implemented by registers or the like. In the illustrated example, the storage circuitry 712 is distributed amongst the logic gate circuitry 708 to facilitate access and increase execution speed.
The example FPGA circuitry 700 of
Although
It should be understood that some or all of the circuitry of FIG. [ER-Diagram] may thus, be instantiated at the same or different times. For example, same and/or different portion(s) of the microprocessor 600 of
In some examples, some or all of the circuitry of FIG. [ER-Diagram] may be instantiated, for example, in one or more threads executing concurrently and/or in series. For example, the microprocessor 600 of
In some examples, the programmable circuitry 512 of
“Including” and “comprising” (and all forms and tenses thereof) are used herein to be open ended terms. Thus, whenever a claim employs any form of “include” or “comprise” (e.g., comprises, includes, comprising, including, having, etc.) as a preamble or within a claim recitation of any kind, it is to be understood that additional elements, terms, etc., may be present without falling outside the scope of the corresponding claim or recitation. As used herein, when the phrase “at least” is used as the transition term in, for example, a preamble of a claim, it is open-ended in the same manner as the term “comprising” and “including” are open ended. The term “and/or” when used, for example, in a form such as A, B, and/or C refers to any combination or subset of A, B, C such as (1) A alone, (2) B alone, (3) C alone, (4) A with B, (5) A with C, (6) B with C, or (7) A with B and with C. As used herein in the context of describing structures, components, items, objects and/or things, the phrase “at least one of A and B” is intended to refer to implementations including any of (1) at least one A, (2) at least one B, or (3) at least one A and at least one B. Similarly, as used herein in the context of describing structures, components, items, objects and/or things, the phrase “at least one of A or B” is intended to refer to implementations including any of (1) at least one A, (2) at least one B, or (3) at least one A and at least one B. As used herein in the context of describing the performance or execution of processes, instructions, actions, activities, etc., the phrase “at least one of A and B” is intended to refer to implementations including any of (1) at least one A, (2) at least one B, or (3) at least one A and at least one B. Similarly, as used herein in the context of describing the performance or execution of processes, instructions, actions, activities, etc., the phrase “at least one of A or B” is intended to refer to implementations including any of (1) at least one A, (2) at least one B, or (3) at least one A and at least one B.
As used herein, singular references (e.g., “a”, “an”, “first”, “second”, etc.) do not exclude a plurality. The term “a” or “an” object, as used herein, refers to one or more of that object. The terms “a” (or “an”), “one or more”, and “at least one” are used interchangeably herein. Furthermore, although individually listed, a plurality of means, elements, or actions may be implemented by, e.g., the same entity or object. Additionally, although individual features may be included in different examples or claims, these may possibly be combined, and the inclusion in different examples or claims does not imply that a combination of features is not feasible and/or advantageous.
As used herein, unless otherwise stated, the term “above” describes the relationship of two parts relative to Earth. A first part is above a second part, if the second part has at least one part between Earth and the first part. Likewise, as used herein, a first part is “below” a second part when the first part is closer to the Earth than the second part. As noted above, a first part can be above or below a second part with one or more of: other parts therebetween, without other parts therebetween, with the first and second parts touching, or without the first and second parts being in direct contact with one another.
Notwithstanding the foregoing, in the case of referencing a semiconductor device (e.g., a transistor), a semiconductor die containing a semiconductor device, and/or an integrated circuit (IC) package containing a semiconductor die during fabrication or manufacturing, “above” is not with reference to Earth, but instead is with reference to an underlying substrate on which relevant components are fabricated, assembled, mounted, supported, or otherwise provided. Thus, as used herein and unless otherwise stated or implied from the context, a first component within a semiconductor die (e.g., a transistor or other semiconductor device) is “above” a second component within the semiconductor die when the first component is farther away from a substrate (e.g., a semiconductor wafer) during fabrication/manufacturing than the second component on which the two components are fabricated or otherwise provided. Similarly, unless otherwise stated or implied from the context, a first component within an IC package (e.g., a semiconductor die) is “above” a second component within the IC package during fabrication when the first component is farther away from a printed circuit board (PCB) to which the IC package is to be mounted or attached. It is to be understood that semiconductor devices are often used in orientation different than their orientation during fabrication. Thus, when referring to a semiconductor device (e.g., a transistor), a semiconductor die containing a semiconductor device, and/or an integrated circuit (IC) package containing a semiconductor die during use, the definition of “above” in the preceding paragraph (i.e., the term “above” describes the relationship of two parts relative to Earth) will likely govern based on the usage context.
As used in this patent, stating that any part (e.g., a layer, film, area, region, or plate) is in any way on (e.g., positioned on, located on, disposed on, or formed on, etc.) another part, indicates that the referenced part is either in contact with the other part, or that the referenced part is above the other part with one or more intermediate part(s) located therebetween.
As used herein, connection references (e.g., attached, coupled, connected, and joined) may include intermediate members between the elements referenced by the connection reference and/or relative movement between those elements unless otherwise indicated. As such, connection references do not necessarily infer that two elements are directly connected and/or in fixed relation to each other. As used herein, stating that any part is in “contact” with another part is defined to mean that there is no intermediate part between the two parts.
Unless specifically stated otherwise, descriptors such as “first,” “second,” “third,” etc., are used herein without imputing or otherwise indicating any meaning of priority, physical order, arrangement in a list, and/or ordering in any way, but are merely used as labels and/or arbitrary names to distinguish elements for ease of understanding the disclosed examples. In some examples, the descriptor “first” may be used to refer to an element in the detailed description, while the same element may be referred to in a claim with a different descriptor such as “second” or “third.” In such instances, it should be understood that such descriptors are used merely for identifying those elements distinctly within the context of the discussion (e.g., within a claim) in which the elements might, for example, otherwise share a same name.
As used herein, “approximately” and “about” modify their subjects/values to recognize the potential presence of variations that occur in real world applications. For example, “approximately” and “about” may modify dimensions that may not be exact due to manufacturing tolerances and/or other real world imperfections as will be understood by persons of ordinary skill in the art. For example, “approximately” and “about” may indicate such dimensions may be within a tolerance range of +/−10% unless otherwise specified herein.
As used herein “substantially real time” refers to occurrence in a near instantaneous manner recognizing there may be real world delays for computing time, transmission, etc. Thus, unless otherwise specified, “substantially real time” refers to real time+1 second.
As used herein, the phrase “in communication,” including variations thereof, encompasses direct communication and/or indirect communication through one or more intermediary components, and does not require direct physical (e.g., wired) communication and/or constant communication, but rather additionally includes selective communication at periodic intervals, scheduled intervals, aperiodic intervals, and/or one-time events.
As used herein, “programmable circuitry” is defined to include (i) one or more special purpose electrical circuits (e.g., an application specific circuit (ASIC)) structured to perform specific operation(s) and including one or more semiconductor-based logic devices (e.g., electrical hardware implemented by one or more transistors), and/or (ii) one or more general purpose semiconductor-based electrical circuits programmable with instructions to perform specific functions(s) and/or operation(s) and including one or more semiconductor-based logic devices (e.g., electrical hardware implemented by one or more transistors). Examples of programmable circuitry include programmable microprocessors such as Central Processor Units (CPUs) that may execute first instructions to perform one or more operations and/or functions, Field Programmable Gate Arrays (FPGAs) that may be programmed with second instructions to cause configuration and/or structuring of the FPGAs to instantiate one or more operations and/or functions corresponding to the first instructions, Graphics Processor Units (GPUs) that may execute first instructions to perform one or more operations and/or functions, Digital Signal Processors (DSPs) that may execute first instructions to perform one or more operations and/or functions, XPUs, Network Processing Units (NPUs) one or more microcontrollers that may execute first instructions to perform one or more operations and/or functions and/or integrated circuits such as Application Specific Integrated Circuits (ASICs). For example, an XPU may be implemented by a heterogeneous computing system including multiple types of programmable circuitry (e.g., one or more FPGAs, one or more CPUs, one or more GPUs, one or more NPUs, one or more DSPs, etc., and/or any combination(s) thereof), and orchestration technology (e.g., application programming interface(s) (API(s)) that may assign computing task(s) to whichever one(s) of the multiple types of programmable circuitry is/are suited and available to perform the computing task(s).
As used herein integrated circuit/circuitry is defined as one or more semiconductor packages containing one or more circuit elements such as transistors, capacitors, inductors, resistors, current paths, diodes, etc. For example, an integrated circuit may be implemented as one or more of an ASIC, an FPGA, a chip, a microchip, programmable circuitry, a semiconductor substrate coupling multiple circuit elements, a system on chip (SoC), etc.
From the foregoing, it will be appreciated that example systems, apparatus, articles of manufacture, and methods have been disclosed that enable lower doses or energy of extreme ultraviolet light to pattern photoresist layers of wafers and/or other semiconductor devices. Reducing the dose of EUV light for lithography patterning significantly decreases manufacturing cost and improves manufacturing throughput.
Further examples and combinations thereof include the following:
Example 1 includes a lithography apparatus having includes an ultraviolet (UV) source to expose a photoresist layer to UV light; and an extreme ultraviolet (EUV) source coupled to the UV source, the EUV source to expose the photoresist layer to EUV light to via a photomask, a combination of the UV light and the EUV light provide a pattern on the photoresist layer when a developer solution is applied to the photoresist layer.
Example 2 includes the apparatus of example 1, wherein the combination of the UV light and the EUV is sufficient to remove portion(s) of the photoresist layer based on the pattern provided on the photoresist layer when a developer solution is applied.
Example 3 includes the apparatus of example 2, wherein exposure of the UV light or the EUV light to the photoresist layer by themselves is insufficient to result in the removal of any portion(s) of the photoresist layer when the developer solution is applied.
Example 4 includes the apparatus of example 1, wherein a dose of EUV light is approximately 40 percent less to establish a critical dimension on the pattern of the photoresist layer as a result of the UV light exposure compared to a dose of energy needed absent exposure of the UV light.
Example 5 includes the apparatus of example 1, wherein the UV source disperses the UV light across an entire surface of the photoresist.
Example 6 includes the apparatus of example 1, wherein UV source includes a UV light source to provide the UV light.
Example 7 includes the apparatus of example 6, wherein the UV light source is a flood light.
Example 8 includes the apparatus of example 1, wherein EUV source patterns the photoresist based on a pattern provided by a photomask.
Example 9 includes the apparatus of example 1, wherein UV source and the EUV source are provided in a single housing.
Example 10 includes the apparatus of example 1, wherein the UV light source exposes the photoresist to the UV light prior to the EUV source exposing the photoresist to the EUV light.
Example 11 includes the apparatus of example 10, wherein the EUV light source exposes the photoresist to the EUV light prior to the UV source exposing the photoresist to the UV light.
Example 12 includes a method including exposing a photoresist layer of a wafer to a first dose of an ultraviolet (UV) light to alter property characteristics of the photoresist layer; and exposing the photoresist layer of the wafer to a second dose of an extreme ultraviolet (EUV) light, the first dose of the UV light and the second dose of the EUV light to contribute to a pattern of the photoresist layer.
Example 13 includes the method of example 12, further including providing the first dose of the UV light to the photoresist layer prior to the second dose of the EUV light.
Example 14 includes the method of example 12, further including providing the second dose of the EUV light to the photoresist layer prior to the first dose of the UV light.
Example 15 includes the method of example 12, further including providing the first dose of the UV light and the second dose of the EUV light in a semiconductor manufacturing track.
Example 16 includes a lithography apparatus including an ultraviolet (UV) source; an extreme ultraviolet (EUV) source; interface circuitry; machine readable instructions; and programmable circuitry to at least one of instantiate or execute the machine readable instructions to: cause the UV source to expose a photoresist layer of a wafer to a first dose of ultraviolet (UV) light across a surface of the photoresist layer; and cause the EUV source to expose the photoresist layer to a second dose of extreme ultraviolet (EUV) light via a patterned mask defining a pattern of openings.
Example 17 includes the apparatus of example 16, wherein the first dose of UV light and the second dose of EUV light are linked in a semiconductor manufacturing track to provide consistent first dose-to-second dose exposure time to improve wafer-to-wafer processing.
Example 18 includes the apparatus of example 16, wherein the programmable circuitry causes the photoresist to be exposed to the first dose of UV light for a first duration and causes the photoresist to be exposed to the second dose of EUV light for a second duration.
Example 19 includes the apparatus of example 16, wherein the programmable circuitry causes the wafer to move between the UV source and the EUV source.
Example 20 includes the apparatus of example 16, wherein a combination of the UV light and the EUV light provide a pattern on the photoresist layer when a developer solution is applied to the photoresist layer.
The following claims are hereby incorporated into this Detailed Description by this reference. Although certain example systems, apparatus, articles of manufacture, and methods have been disclosed herein, the scope of coverage of this patent is not limited thereto. On the contrary, this patent covers all systems, apparatus, articles of manufacture, and methods fairly falling within the scope of the claims of this patent.
