NOT APPLICABLE
Personal electronic products, such as cell phones, personal data assistants, digital cameras, laptops, etc, are generally comprised of several packaged semiconductor IC chips and surface mount components assembled onto interconnect substrates, such as printed circuit boards and flex substrates. There is an ever increasing demand to incorporate more functionality and features into personal electronic products and the like. This, in turn, has placed ever increasing demands on the design, size, and assembly of the interconnect substrates. As the number of assembled components increases, substrate areas and costs increase, while demand for a smaller form factor increases.
As part of making their invention, the inventors have recognized that there is a need to address these issues and that it would be advantageous to find ways to enable increases in functionality and features of electronic products without causing increases in substrate areas and costs, and decreases in product yields. As also part of making their inventions, the inventors have recognized that many electronic products have several components that can be grouped together in several small groups that provide specific functions. For example, an electronic product often has one or more power conversion circuits, each of which typically comprises a control IC chip, an inductor, one or two capacitors, and sometimes a resistor or two. As another example, an electronic product may have an analog-to-digital circuit and/or a digital-to-analog circuit, each of which typically comprises an IC chip, and several resistors and capacitors. As also part of making their invention, the inventors have discovered that the substrate area required for a circuit group can be significantly decreased by incorporating the components of the circuit group into a single package.
Accordingly, a first general embodiment of the invention is directed to a semiconductor die package broadly comprising at least one semiconductor die disposed on one surface of a leadframe and electrically coupled to at least one conductive region of the leadframe, at least one location on a conductive region of the leadframe at the first surface thereof, the location being adapted to receive an electrically conductive bump, and at least one passive electrical component disposed on the other surface of a leadframe and electrically coupled to at least one conductive region of the leadframe.
Another general embodiment of the invention is directed to a method of manufacturing a semiconductor die package broadly comprising assembling at least one semiconductor die and a leadframe together at a first surface of a leadframe and with a conductive region of the die electrically coupled to at least one conductive region of the leadframe, assembling at least one passive electrical component and the leadframe together at a second surface of the leadframe and with a conductive region of the die electrically coupled to at least one conductive region of the leadframe, and assembling at least one electrically conductive bump and the leadframe together at the first surface of the leadframe and with the at least one electrically conductive bump electrically coupled to at least one conductive region of the leadframe.
Another general embodiment of the invention is directed to a method of manufacturing a semiconductor die package broadly comprising assembling at least one semiconductor die and the leadframe together at the first surface of the leadframe and with a conductive region of the die electrically coupled to at least one conductive region of the leadframe, at least one location on the conductive region at the first surface of the leadframe being left unobstructed for receiving an electrically conductive bump, assembling at least one passive electrical component and the leadframe together at a second surface of the leadframe and with a conductive region of the die electrically coupled to at least one conductive region of the leadframe, and disposing a body of electrically insulating material over the second surface of the leadframe and at least around a portion of the at least one passive electrical component.
The present invention also encompasses systems that include packages according to the present invention, each such system having an interconnect substrate and a semiconductor die package according to the present invention attached to the interconnect substrate, with electrical connections made therewith.
The invention enables the manufacture of ultra-miniature power converters and other circuits fitting within a volume on the order of 2.5 mm by 2.5 mm by 0.9 mm, and which can be used in portable consumer products, such as cell phones, MP3 players, PDAs, and the like.
The above general embodiments and other embodiments of the invention are described in the Detailed Description with reference to the Figures. In the Figures, like numerals may reference like elements and descriptions of some elements may not be repeated.
Regulator circuit 30 has eight (8) terminals, labeled as PVIN, SW, GND, EN, FB, and VSEL<2:0>, which are coupled to the other components of circuit group 10 as shown in
A minimum footprint of package 100 is 2.5 mm by 2.5 mm, which is 31% smaller than the typical footprint of 3 mm by 3 mm needed by an optimal discrete component implementation. A typical thickness of package 100 is about 0.9 mm, including the thickness of semiconductor die 130 (typically around 0.1 mm) but not including the height of bumps 190, and about 1 mm when the typical height of 0.2 mm for bumps 190 is included. While these thicknesses are larger than the thickness of about 0.6 mm for the discrete components, most product applications have ample vertical space and can accommodate the larger thicknesses without difficulty. With the construction of package 100 shown in
Bodies 105 of electrically conductive adhesive material are disposed on conductive regions 114-117 at the leadframe's bottom surface 112, and the surface-mount components 120, 140, and 150 are placed onto appropriate ones of the conductive regions. Bodies 105 may comprise solder paste or a conductive polymeric adhesive, and may be disposed by screen printing. Components 120, 140, and 150 may be assembled by conventional surface mounting equipment and methods. Each of components 120, 140, and 150 may have a generally box or cylindrical shape, with two conduction terminals at its distal ends. Input capacitor 120 will have its conduction terminals electrically coupled to conductive regions 115 and 116, respectively, output capacitor 150 will have its conduction terminals electrically coupled to conductive regions 116 and 117, respectively, and inductor 140 will have its conduction terminals electrically coupled to conductive regions 114 and 117, respectively. Bodies 105 of conductive adhesive material may thereafter be reflowed (in the case of solder) or otherwise cured (in the case of polymeric adhesive) to complete the assembly of components 120, 140, and 150 onto leadframe 110. The resulting assembly is shown in
Referring to
Referring to
Still Referring to
At this point, package 100 may be separated from the frame (if present), trimmed of any flashing material, and sold to customers for use in various electrical systems. In further embodiments, an underfill material 180, shown in
While the above manufacturing method has been illustrated with die 130 being assembled with leadframe 110 after components 120, 140, and 150 have been assembled, it may be appreciated that the method may be practiced with die 130 being assembled with leadframe 110 before components 120, 140, and 150 are assembled with leadframe 110. Also, a non-volatile solder paste (e.g., a solder paste that substantially does not emit gas upon reflow and does not require cleaning after reflow) may be used for bodies 105 and 107 of electrically conductive adhesive material. In this case, it is possible to dispose electrically insulating material 160 on leadframe 110 substantially simultaneously with the assembly of semiconductor die 130 to the leadframe, or to dispose electrically insulating material 160 on leadframe 110 substantially simultaneously with the assembly of components 120, 140, and 150 with the leadframe. As one example, semiconductor die 130 may be placed on the leadframe's top surface 111, with bodies 107 comprising non-volatile solder paste, and a mold may be placed to cover the leadframe's bottom surface 112 and the passive components 120, 140, and 150, which have been previously assembled onto the leadframe. Material 160 may then be disposed in the mold, and heat may be applied to simultaneously reflow bodies 107 and solidify/cure material 160. A plate of non-stick material, having an aperture to accept die 130, may be used to prevent material 160 from flowing over the leadframe's top surface 111. As another example, passive components 120, 140, and 150 may be placed onto leadframe 110, with bodies 105 comprising non-volatile solder paste, a mold may be placed over the components and the leadframe, material 160 may be disposed in the mold, and heat may be applied to simultaneously reflow bodies 105 and solidify/cure material 160. As another example, components 120, 140, and 150 may initially be embedded into a block of material 160 with their surfaces exposed for contact to leadframe 110, and with material 160 comprising a thermoplastic or partially cured polymeric material. The embedded components may then be placed over and aligned to leadframe 110 with heat applied from the other side of the leadframe to reflow bodies 105 of non-volatile solder paste and to cause material 160 to flow onto and adhere to leadframe 110. In this approach, it is further possible to attach die 130 at the same time (the aforementioned non-stick plate may be used), thereby enabling all of components 120-150 to be assembled with leadframe 110 simultaneously.
Accordingly, it should be understood that, where the performance of an action of any of the methods disclosed herein is not predicated on the completion of another action, the actions may be performed in any time sequence (e.g., time order) with respect to one another, including simultaneous performance and interleaved performance of various actions. (Interleaved performance may, for example, occur when parts of two or more actions are performed in a mixed fashion.) Accordingly, it may be appreciated that, while the method claims of the present application recite sets of actions, the method claims are not limited to the order of the actions listed in the claim language, but instead cover all of the above possible orderings, including simultaneous and interleaving performance of actions and other possible orderings not explicitly described above, unless otherwise specified by the claim language (such as by explicitly stating that one action proceeds or follows another action).
As noted above, package 100 provides substantial space savings over discrete component implementations. As additional advantages of the packages disclosed herein, the leadframe provides reduced series resistance among the components of the power supply, and the combination of the leadframe with insulating material 160 provides more reliable electrical connections. In addition, since the packages disclosed herein provide complete functioning circuits, the packages may be tested before being assembled onto product substrates, thereby increasing yields of the product substrates. In addition, as to power supply implementations of the packages of the present invention, the configuration of the power supply components in the packages can provide conversion efficiencies of 85% or more.
While exemplary packages 100 have been illustrated with the use of one semiconductor die, it may be appreciated that further embodiments may include two or more semiconductor die, which may be assembled onto either of the leadframe surfaces 111 or 112. In addition, while the above packages have been illustrated with the passive components (120, 140, and 150) being assembled onto the leadframe's bottom surface 112, further embodiments may include passive components mounted on the leadframe's top surface 111, such as ultra-thin surface mount resistors.
The semiconductor die packages described above can be used in electrical assemblies including circuit boards with the packages mounted thereon. They may also be used in systems such as phones, computers, etc.
Some of the examples described above are directed to “leadless” type packages such as MLP-type packages (microleadframe packages) where the terminal ends of the leads do not extend past the lateral edges of the molding material. Embodiments of the invention may also include leaded packages where the leads extend past the lateral surfaces of the molding material.
Any recitation of “a”, “an”, and “the” is intended to mean one or more unless specifically indicated to the contrary.
The terms and expressions which have been employed herein are used as terms of description and not of limitation, and there is no intention in the use of such terms and expressions of excluding equivalents of the features shown and described, it being recognized that various modifications are possible within the scope of the invention claimed.
Moreover, one or more features of one or more embodiments of the invention may be combined with one or more features of other embodiments of the invention without departing from the scope of the invention.
While the present invention has been particularly described with respect to the illustrated embodiments, it will be appreciated that various alterations, modifications, adaptations, and equivalent arrangements may be made based on the present disclosure, and are intended to be within the scope of the invention and the appended claims.