The invention is described by way of examples with reference to the accompanying drawings, wherein:
The carrier substrate 12 is typically a package substrate that is made of alternating dielectric layers and metal layers (not shown). The metal layers are patterned to form conductive lines. The carrier substrate 12 further has plugs and vias that connect metal lines of different levels to one another. The carrier substrate 12 also has a plurality of terminals 20 on an upper surface, and a plurality of contacts (not shown) for connecting the carrier substrate 12 to another substrate such as a motherboard or a computer card. The terminals 20 and the contacts of the carrier substrate 12 are also connected to the metal lines formed within the carrier substrate 12.
The microelectronic die 14 includes a semiconductor substrate 22, an integrated circuit 24, contacts 26, and conductive bumps 28. The integrated circuit 24 is formed in and on a lower surface of the semiconductor substrate 22. The integrated circuit 24 includes a large number (typically millions) of electronic components such as transistors, and further includes a plurality of alternating metal and dielectric layers. The metal layers of the integrated circuit 24 are patterned into metal lines, and the metal lines of different levels are connected to one another with metal plugs and vias. The contacts 26 are formed on a lower surface of the integrated circuit 24, and are also connected to the metal lines of the integrated circuit 24. The conductive bumps 28 are formed on the contacts 26, utilizing an electroplating operation.
The conductive bumps 28 are placed on the terminals 20. The entire assembly, including the microelectronic die 14 and the carrier substrate 12, is inserted into an oven at a temperature sufficiently high that the bumps 28 reflow and attach to the terminals 20 according to a process commonly known as “Controlled Collapse Chip Connect” (C4). The assembly 10 is then allowed to cool, which causes solidification of the bumps 28.
The underfill material 16 is made of a polymer. The underfill material 16 is introduced at an edge of the microelectronic die 14 and flows into a cavity between the microelectronic die 14 and the carrier substrate 12 under capillary action. The underfill material 16 envelopes the bumps 28, but at this stage is not cured and cannot provide rigidity to protect the bumps 28 from delaminating off the terminals 20 or the contacts 26.
The periphery seal 18 is subsequently placed on an upper surface of the microelectronic die 14. The periphery seal 18 is typically made of the same polymer material as the underfill material 16. Referring specifically to
Referring now to
Referring now to
All the components of the microelectronic assembly 10 of
A more brittle interface is formed between the periphery seal 18 and the thermally conductive member 34 than between the solder thermal interface material 30 and the thermally conductive member 34. The solder thermal interface material 30 is susceptible to creep and plastic deformation. Because of a stronger, more brittle interface between the periphery seal 18 and the thermally conductive member 34, and because of material properties of the periphery seal 18, the periphery seal 18 can tolerate a greater thermally induced stress than the solder thermal interface 30 without delaminating from either the thermally conductive member 34 or the microelectronic die 14. The periphery seal 18 can also tolerate a larger number of stress cycles than the solder thermal interface material 30, without creep or fatigue-related plastic deformation.
It can thus be seen that the combination of the solder thermal interface material 30 and the periphery seal 18 provides an interface that has a high thermal conductivity due to the high thermal conductivity of the solder thermal interface material 30, yet strong because of (i) the material of the periphery seal 18, (ii) the more brittle interface between the periphery seal 18 and the thermally conductive member 34, and (iii) because of the location of the periphery seal 18 on the periphery of the upper surface of the microelectronic die 14 where stress concentrations tend to be the highest.
With specific reference to
The exemplary computer system 700 includes a processor 702 (e.g., a central processing unit (CPU), a graphics processing unit (GPU) or both), a main memory 704 (e.g., read only memory (ROM), flash memory, dynamic random access memory (DRAM) such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM), etc.), and a static memory 706 (e.g., flash memory, static random access memory (SRAM), etc.), which communicate with each other via a bus 708.
The computer system 700 may further include a video display 710 (e.g., a liquid crystal display (LCD) or a cathode ray tube (CRT)). The computer system 700 also includes an alpha-numeric input device 712 (e.g., a keyboard), a cursor control device 714 (e.g., a mouse), a disk drive unit 716, a signal generation device 718 (e.g., a speaker), and a network interface device 720.
The disk drive unit 716 includes a machine-readable medium 722 on which is stored one or more sets of instructions 724 (e.g., software) embodying any one or more of the methodologies or functions described herein. The software may also reside, completely or at least partially, within the main memory 704 and/or within the processor 702 during execution thereof by the computer system 700, the main memory 704 and the processor 702 also constituting machine-readable media.
The software may further be transmitted or received over a network 728 via the network interface device 720.
While the machine-readable medium 724 is shown in an exemplary embodiment to be a single medium, the term “machine-readable medium” should be taken to include a single medium or multiple media (e.g., a centralized or distributed database, and/or associated caches and servers) that store the one or more sets of instructions. The term “machine-readable medium” shall also be taken to include any medium that is capable of storing, encoding or carrying a set of instructions for execution by the machine and that cause the machine to perform any one or more of the methodologies of the present invention. The term “machine-readable medium” shall accordingly be taken to include, but not be limited to, solid-state memories, optical and magnetic media, and carrier wave signals.
While certain exemplary embodiments have been described and shown in the accompanying drawings, it is to be understood that such embodiments are merely illustrative and not restrictive of the current invention, and that this invention is not restricted to the specific constructions and arrangements shown and described since modifications may occur to those ordinarily skilled in the art.