The subject matter of the present application relates to microelectronic packages and assemblies incorporating microelectronic packages.
Semiconductor chips are commonly provided as individual, prepackaged units. A standard chip has a flat, rectangular body with a large front face having contacts connected to the internal circuitry of the chip. Each individual chip typically is contained in a package having external terminals connected to the contacts of the chip. In turn, the terminals, i.e., the external connection points of the package, are configured to electrically connect to a circuit panel, such as a printed circuit board. In many conventional designs, the chip package occupies an area of the circuit panel considerably larger than the area of the chip itself. As used in this disclosure with reference to a flat chip having a front face, the “area of the chip” should be understood as referring to the area of the front face.
Size is a significant consideration in any physical arrangement of chips. The demand for more compact physical arrangements of chips has become even more intense with the rapid progress of portable electronic devices. Merely by way of example, devices commonly referred to as “smart phones” integrate the functions of a cellular telephone with powerful data processors, memory and ancillary devices such as global positioning system receivers, electronic cameras, and local area network connections along with high-resolution displays and associated image processing chips. Such devices can provide capabilities such as full internet connectivity, entertainment including full-resolution video, navigation, electronic banking and more, all in a pocket-size device. Complex portable devices require packing numerous chips into a small space. Moreover, some of the chips have many input and output connections, commonly referred to as “I/Os.” These I/Os must be interconnected with the I/Os of other chips. The components which form the interconnections should not greatly increase the size of the assembly. Similar needs arise in other applications as, for example, in data servers such as those used in internet search engines where increased performance and size reduction are needed.
Semiconductor chips containing memory storage arrays, particularly dynamic random access memory chips (DRAMs) and flash memory chips are commonly packaged in single- or multiple-chip packages and assemblies. Each package has many electrical connections for carrying signals, power and ground between terminals and the chips therein. The electrical connections can include different kinds of conductors such as horizontal conductors, e.g., traces, beam leads, etc., which extend in a horizontal direction relative to a contact-bearing surface of a chip, vertical conductors such as vias, which extend in a vertical direction relative to the surface of the chip, and wire bonds which extend in both horizontal and vertical directions relative to the surface of the chip.
Conventional microelectronic packages can incorporate a microelectronic element which is configured to predominantly provide memory storage array function, i.e., a microelectronic element that embodies a greater number of active devices to provide memory storage array function than any other function. The microelectronic element may be or include a DRAM chip, or a stacked electrically interconnected assembly of such semiconductor chips. Typically, all of the terminals of such package are placed in sets of columns adjacent to one or more peripheral edges of a package substrate to which the microelectronic element is mounted. For example, in one conventional microelectronic package 12 seen in
In light of the foregoing, certain improvements in the positioning of terminals on microelectronic packages can be made in order to improve electrical performance, particularly in assemblies which include such packages and a circuit panel to which such packages can be mounted and electrically interconnected with one another.
In accordance with an embodiment of the invention, a microelectronic package can include a substrate having a first surface with a plurality of substrate contacts thereon, and a second surface is opposite the first surface. A microelectronic element has a rear face facing the first surface, a front face facing away from the first surface, and first and second opposed edges extending between the front and rear surfaces. Each of the first and second edges may extend in a first direction parallel to the front face. At least one column of element contacts extends in the first direction along the front face. The first and second edges define an axial plane extending in the first direction and also in a third direction normal to the face of the microelectronic element, the axial plane being centered relative to the first and second edges.
In such package, in one example, conductive structure such as wire bonds extends above the front face and beyond at least one of the first or second edges, the conductive structure electrically connecting the element contacts with the substrate contacts.
In one embodiment, terminals of the package include first terminals which are disposed at a central region of the second surface of the substrate. The central region may be such that it is not wider than three and one-half times a minimum pitch between adjacent ones of parallel columns of the terminals. The central region of the surface of the substrate is located such that the axial plane intersects the central region.
In certain embodiments of the invention, these first terminals in the central region are configured to carry address information usable by circuitry within the package to determine an addressable memory location from among all the available addressable memory locations of a memory storage array within the microelectronic element. In a particular embodiment, the first terminals can be configured to carry all of the address information usable to determine such addressable memory location from available addressable memory locations of such memory storage array. In other embodiments, the first terminals can be configured to carry a majority of the address information or in a particular case, at least three quarters of the address information.
In one example, the first terminals can be configured to receive the address information transmitted thereto as a plurality of states or changes in state on respective terminals of the microelectronic package. In another example, the first terminals can be configured to receive the address information encoded as a plurality of states or changes in state on one or on a combination of the first terminals. In a particular embodiment, the first terminals can be configured to carry information that controls an operating mode of the microelectronic element. As in the case of the address information, such information can be encoded as a plurality of states or changes in state on one or on a plurality of terminals.
In a particular embodiment, the first terminals can be configured to carry all of a group of command signals, address signals, bank address signals and clock signals transferred to the microelectronic package on a “command-address bus” of a circuit panel. The command signals in such case may be among or may be restricted to the following: command signals such as write enable, row address strobe, and column address strobe, and the clock signals are sampling clocks used for sampling the address signals. While the clock signals can be of various types, in one embodiment, the clock signals carried by these terminals can be one or more pairs of differential clock signals transmitted as differential clock signals or as true and complement clock signals.
The signals of the command-address bus can be bussed on a circuit panel such as a printed circuit board or module card to multiple microelectronic packages in parallel, particularly to first and second microelectronic packages mounted to opposite surfaces of the circuit panel. For certain embodiments herein, by placing terminals which carry the address information, or in a particular example, command-address bus signals, in the central region of the package surface, rather than in peripheral regions near the edges of the microelectronic package, it is possible to reduce the lengths of stubs used to carry signals from the command-address bus 36 (
In some embodiments, the microelectronic package may have no more than four columns of terminals in the central region configured to carry all of the command signals, address signals, bank address signals and clock signals as described above. In certain embodiments, there may be only two columns of such terminals. In other embodiments there may only be one column of such terminals.
The microelectronic package may have second terminals other than the above-described command-address bus signal terminals, such second terminals being disposed in one or more of the peripheral regions and being configured to carry data signals. For example, the second terminals can include terminals used for carrying uni-directional or bi-directional data signals to and or from the microelectronic element, and data strobe signals, as well as data masks and ODT or “on die termination” signals used to turn on or off parallel terminations to termination resistors. It is possible in some embodiments for some or all terminals which are configured to carry signals other than the command-address bus signals to also be disposed in the central region of the package surface. Signals or reference potentials such as chip select, reset, power supply voltages, e.g., Vdd, Vddq, or ground, e.g., Vss and Vssq, can be carried by the second terminals, or may in some cases be carried by the first terminals.
In some embodiments, a microelectronic element may include a first semiconductor chip mounted adjacent the substrate and electrically connected thereto, and one or more second semiconductor chips overlying the first semiconductor chip and electrically connected therewith, in which the second semiconductor chips embody a greater number of active devices configured to provide memory storage array function than any other function.
A microelectronic assembly according to an aspect of the invention can include a circuit panel having first and second opposed surfaces and first and second panel contacts at the first and second surfaces, respectively, and first and second microelectronic packages each having terminals mounted to the respective panel contacts. In such assembly, each microelectronic package can include a substrate having first and second opposed surfaces, the first surface having substrate contacts thereon; and a microelectronic element embodying a greater number of active devices to provide memory storage array function than any other function. The microelectronic element can have a rear face facing the first surface, a front face opposite the rear face, and contacts on the front face electrically connected with the substrate contacts through conductive structure extending above the front face. A plurality of terminals on the second surface can be configured for connecting the microelectronic package with at least one component external to the package. The terminals can be electrically connected with the substrate contacts and include first terminals disposed at locations within first and second parallel grids. Each of the first and second grids can be configured to carry address information usable by circuitry within the package to determine an addressable memory location from among all the available addressable memory locations of a memory storage array within the microelectronic element. Signal assignments of the first terminals in the first grid can be a mirror image of the signal assignments of the first terminals in the second grid.
In one example, the first terminals of each of the first and second grids of each microelectronic package can be configured to carry all of the address information usable by the circuitry within the respective microelectronic package to determine the addressable memory location.
In one example, the first terminals of each of the first and second grids of each microelectronic package can be configured to carry information that controls an operating mode the microelectronic element of the respective microelectronic package.
In one example, the first terminals of each of the first and second grids of each microelectronic package can be configured to carry all of the command signals transferred to the respective microelectronic package, the command signals being write enable, row address strobe, and column address strobe signals.
In one example, the first terminals of each of the first and second grids of each microelectronic package can be configured to carry clock signals transferred to the respective microelectronic package, the clock signals including clocks used for sampling signals carrying the address information.
In one example, the first terminals of each of the first and second grids of each microelectronic package can be configured to carry all of the bank address signals transferred to the respective microelectronic package.
In one example, the first terminals in the second grid of the first package can be connected through the circuit panel to the first terminals in the first grid of the second package. The first terminals of the second grid of the first package can be aligned within one ball pitch of the corresponding first terminals to which they are connected of the first grid on the second package in x and y orthogonal directions parallel to the first and second circuit panel surfaces.
In one example, the grids can be aligned with one another in the x and y orthogonal directions such that the terminals of the grids can be coincident with one another.
In one example, each position of each grid can be occupied by one of the terminals.
In one example, at least one position of each grid may not be occupied by a terminal.
In one example, the grids of the first and second microelectronic packages can be functionally and mechanically matched.
In one example, a length of a stub of at least one of electrical connections between one of the first terminals of the first microelectronic package and a corresponding one of the first terminals of the second microelectronic package can be less than seven times a minimum pitch of the first terminals of each of the microelectronic packages.
In one example, at least some of the electrical connections through the circuit panel between the first terminals of the first and second microelectronic packages can have an electrical length of approximately a thickness of the circuit panel.
In one example, the total combined length of the conductive elements connecting a pair of electrically coupled first and second panel contacts exposed at the first and second surfaces of the circuit panel can be less than seven times a smallest pitch of the panel contacts.
In one example, the circuit panel can include a bus having a plurality of conductors configured to carry all of the address information transferred to each of the microelectronic packages. The conductors may extend in a first direction parallel to the first and second surfaces.
In one example, the first terminals can be disposed within an individual column in each of the first and second grids. The circuit panel may include no more than one routing layer for global routing of all of the address information between a connection site on the circuit panel at which the first terminals of the first and second packages can be electrically connected and a different connection site on the circuit panel at which the first terminals of at least a third microelectronic package can be electrically connected.
In one example, each of the first and second grids of first terminals of each microelectronic package can have two parallel columns, and wherein the circuit panel includes no more than two routing layers for global routing of all of the address information between respective connection sites on the circuit panel at which the terminals of one or more of the microelectronic packages can be electrically connected.
In one example, there may be no more than one routing layer for global routing of all of the address information between a connection site on the circuit panel at which the first terminals of the first and second packages can be electrically connected and a different connection site on the circuit panel at which the first terminals of at least a third microelectronic package can be electrically connected.
In one example, each microelectronic package can include a buffer element electrically connected to at least some of the respective terminals and the microelectronic element in the respective microelectronic package. Each buffer element can be configured to at least one of: regenerate, or at least partially decode at least one signal received at one or more of the terminals of the respective microelectronic package for transfer to the microelectronic element.
In one example, the microelectronic element of each microelectronic package can be a first microelectronic element, and each of the microelectronic packages may further include a second microelectronic element having a rear face facing the substrate and a front facing opposite the rear face, a plurality of element contacts on the front face being electrically connected with the substrate contacts through conductive structure extending above the front face. The second microelectronic element can embody a greater number of active devices to provide memory storage array function than any other function. In such example, the first terminals of each of the first and second grids of each microelectronic package can be configured to carry address information usable by circuitry within the respective microelectronic package to determine an addressable memory location from among all the available addressable memory locations of a memory storage array within the first and second microelectronic elements of the respective microelectronic package.
According to an aspect of the invention, a microelectronic assembly can include a microelectronic package and a circuit panel electrically connected with the microelectronic package. In such example, microelectronic package can include: a substrate having first and second opposed surfaces, the first surface having substrate contacts thereon; and a microelectronic element embodying a greater number of active devices to provide memory storage array function than any other function. The microelectronic element can have a rear face facing the first surface, a front face opposite the rear face, and contacts on the front face electrically connected with the substrate contacts through conductive structure extending above the front face. A plurality of terminals on the second surface can be configured for connecting the microelectronic package with the circuit panel. The terminals can be electrically connected with the substrate contacts and include first terminals disposed at locations within first and second parallel grids. Each of the first and second grids may be configured to carry address information usable by circuitry within the package to determine an addressable memory location from among all the available addressable memory locations of a memory storage array within the microelectronic element. Signal assignments of the first terminals in the first grid can be a mirror image of the signal assignments of the first terminals in the second grid.
In one example, the system may further include a housing, the microelectronic assembly and the one or more other electronic components being assembled with the housing.
In one example, the microelectronic assembly can be a first microelectronic assembly, and the system may further include a second such microelectronic assembly.
In one example, each microelectronic assembly can be mounted to, and electrically connected with a second circuit panel for transport of signals to and from each microelectronic assembly.
A microelectronic assembly according to an aspect of the invention can include a circuit panel having first and second opposed surfaces and first and second panel contacts at the first and second surfaces, respectively, and first and second microelectronic packages each having terminals mounted to the respective panel contacts. In such assembly, each microelectronic package can include a substrate having first and second opposed surfaces, the first surface having substrate contacts thereon; and a microelectronic element embodying a greater number of active devices to provide memory storage array function than any other function. The microelectronic element can have a rear face facing the first surface, a front face opposite the rear face, and contacts on the front face electrically connected with the substrate contacts through conductive structure extending above the front face. A plurality of terminals on the second surface can be configured for connecting the microelectronic package with at least one component external to the package. The terminals can be electrically connected with the substrate contacts and include first terminals disposed at locations within first and second parallel grids. The first terminals in each of the first and second grids can be configured to carry a majority of address information usable by circuitry within the package to determine an addressable memory location from among all the available addressable memory locations of a memory storage array within the microelectronic element. Signal assignments of the first terminals in the first grid can be a mirror image of the signal assignments of the first terminals in the second grid.
In one example, the first terminals of each of the first and second grids of each microelectronic package can be configured to carry at least three-quarters of the address information usable by the circuitry within the respective microelectronic package to determine the addressable memory location.
A microelectronic assembly according to another aspect of the invention can include a circuit panel having first and second opposed surfaces and first and second panel contacts at the first and second surfaces, respectively, and first and second microelectronic packages each having terminals mounted to the respective panel contacts. In such assembly, each microelectronic package can include a substrate having first and second opposed surfaces, the first surface having substrate contacts thereon; and a microelectronic element embodying a greater number of active devices to provide memory storage array function than any other function. The microelectronic element can have a rear face facing the first surface, a front face opposite the rear face, and contacts on the front face electrically connected with the substrate contacts through conductive structure extending above the front face. A plurality of terminals on the second surface can be configured for connecting the microelectronic package with at least one component external to the package. The terminals can be electrically connected with the substrate contacts and include a first set of first terminals arranged in a first individual column and second set of the first terminals arranged in a second individual column. The first terminals of each of the first and second individual columns can be configured to carry address information usable by circuitry within the microelectronic package to determine an addressable memory location from among all the available addressable memory locations of a memory storage array within the microelectronic element. Signal assignments of the first terminals in the first column can be symmetric about an axis extending between the first and second columns with respect to the signal assignments of the first terminals in the second column.
In view of the illustrative conventional microelectronic package 12 described relative to
Improvements can be made particularly for use of a microelectronic package when provided in an assembly such as shown in
The circuit panel 34 electrically interconnects the terminals of the respective packages 12A, 12B using local interconnect wiring that appears similar to a crisscross or “shoelace” pattern in which a terminal labeled “1” near one edge 16 of package 12A connects through the circuit panel 34 to a terminal labeled “1” of package 12B near the same edge 16 of package 12B. However, the edge 16 of package 12B as assembled to circuit panel 34 is far from the edge 16 of package 12A.
Connections through the circuit panel between terminals on each package, e.g., package 12A, to the corresponding terminals on the package mounted opposite thereto, i.e., package 12B, are fairly long. As further seen in
In some cases, the lengths of the circuit panel wiring required to connect the terminals of such oppositely mounted microelectronic packages may not severely impact the electrical performance of the assembly. However, when the signal carried by the connected pair of terminals on the packages 12A, 12B is a signal from a bus 36 used to carry address information or other information such as clock information usable to sample address information which is common to operation of the memory storage array function of a plurality of packages connected to the circuit panel, the inventors recognize that the wiring length of the stubs extending from the bus 36 to the terminals on each package may significantly affect performance. When the interconnecting wiring is relatively long, a more severe impact occurs, which can increase settling time, ringing, jitter, or intersymbol interference for a transmitted signal to an unacceptable degree.
In a particular embodiment, the bus 36 used to carry address information can be a command-address bus 36 configured to carry command information, address information, bank address information and clock information. In a specific implementation, the command information can be transmitted as command signals on respective signal conductors on the circuit panel. It is also possible for the address information to be transmitted as address signals on respective signal conductors, as it is also possible for the bank address information to be transmitted as bank address signals on respective signal conductors, and it is also possible for the clock information to be transmitted as clock signals on respective signal conductors. In a specific implementation of a microelectronic element which has a memory storage array such as a DRAM chip, the command signals which can be carried by the bus 36 can be write enable, row address strobe and column address strobe, and the clock signals which can be carried by the bus 36 can be clock signals used at least for sampling address signals carried by the bus 36.
Accordingly, certain embodiments of the invention described herein provide a microelectronic package configured so as to permit the lengths of stubs on a circuit panel to be reduced when first and second such packages are mounted opposite one another on opposite surfaces of a circuit panel, e.g., a circuit board, module board or card, or flexible circuit panel. Assemblies which incorporate first and second microelectronic packages mounted opposite one another on a circuit panel can have significantly reduced stub lengths between the respective packages. Reducing the stub lengths within such assemblies can improve electrical performance, such as by reducing one or more of settling time, ringing, jitter, or intersymbol interference, among others. Moreover, it may be possible to obtain other benefits as well, such as simplifying the structure of the circuit panel or reducing the complexity and cost of designing or manufacturing the circuit panel, or for both designing and manufacturing the circuit panel.
Thus, a microelectronic package 100 according to an embodiment of the invention is illustrated in
The microelectronic element has element contacts 111, 113 at a front face 105 thereof which are electrically connected to respective substrate contacts 121, 123 at a first surface 108 of the substrate 102. For example, wirebonds 112 may electrically connect the element contacts 111, 113 with the substrate contacts 121, 123. Alternatively, other types of conductors, e.g., portions of a lead frame, flexible ribbon bonds, etc., may be used to electrically connect the element contacts 111, 113 with the respective substrate contacts 121, 123, which in some cases may connect the element contacts 111, 113 with other conductive elements disposed at a greater height from the substrate surface 108 than the front face 105 of the microelectronic element 101. In one type of such microelectronic element 101, each one of some contacts of the element contacts 111, 113 may be configured to receive particular address information of the address information supplied to the microelectronic element. In a particular embodiment, each of such contacts 111, 113 may be configured to receive a respective address signal of a plurality of address signals supplied to the microelectronic element 101 from the outside the microelectronic element, i.e., through wiring of the package such as wire bonds 112, and through terminals 104, 106.
In one particular example of this type of microelectronic element 101, the address information present at the element contacts 111, 113 can be sampled relative to an edge of a clock used by the respective microelectronic element, i.e., upon on a transition of the clock between first and second different voltage states. That is, each address signal can be sampled upon a rising transition between a lower voltage state and a higher voltage state of the clock, or upon a falling transition between a higher voltage state and a lower voltage state of the clock. Thus, the plurality of address signals may all be sampled upon the rising transition of the clock, or such address signals may all be sampled upon the falling transition of the clock, or in another example, the address signal at one of the element contacts 111, 113 can be sampled upon the rising transition of the clock and the address signal at one other external contact can be sampled upon the falling transition of the clock.
In another type of microelectronic element 101 configured to predominantly provide memory storage array function, one or more of the address contacts thereon can be used in a multiplexed manner. In this example, a particular element contact 111, 113 of the respective microelectronic element 101 can receive two or more different signals supplied to the microelectronic element from the outside. Thus, a first address signal can be sampled at the particular contact 111, 113 upon a first transition of the clock between the first and second different voltage states (e.g., a rising transition), and a signal other than the first address signal can be sampled at the particular contact upon a second transition of the clock (e.g., a falling transition) between the first and second voltage states that is opposite the first transition.
In such a multiplexed manner, two different signals can be received within the same cycle of the clock on the same element contact 111, 113 of the respective microelectronic element 101. In a particular case, multiplexing in this manner can allow a first address signal and a different signal to be received in the same clock cycle on the same element contact 111, 113 of the respective microelectronic element 101. In yet another example, multiplexing in this manner can allow a first address signal and a second different address signal to be received in the same clock cycle on the same element contact 111, 113 of the respective microelectronic element 101.
In some embodiments, the substrate 102 can include a sheet-like or board-like dielectric element, which may consist essentially of polymeric material, e.g., a resin or polyimide, among others. Alternatively, the substrate can include a dielectric element having a composite construction such as glass-reinforced epoxy, e.g., of BT resin or FR-4 construction. In some examples, the dielectric element has a coefficient of thermal expansion in the plane of the dielectric element, i.e., in a direction parallel to a first surface 108 thereof, of up to 30 parts per million per degree Celsius (hereinafter, “ppm/° C.”). In another example, the substrate can include a supporting element of material having a coefficient of thermal expansion (“CTE”) of less than 12 parts per million per degree Celsius, on which the terminals and other conductive structure are disposed. For example, such low CTE element can consist essentially of glass, ceramic or semiconductor material or liquid crystal polymer material, or a combination of such materials.
As seen in
As further seen in
As particularly shown in
The microelectronic element may also include additional contacts that may not be disposed within a column of the element contacts. These additional contacts may be used for connection to power, ground, or as contacts available for contact with a probing device, such as may be used for testing.
As seen in
A first set of the first terminals 104 can be arranged at positions within a first grid 114 at a second surface 110 of the substrate 102 opposite from the first surface 108. A second set of the first terminals 104 can be arranged at positions within a second grid 124 at the second surface 110 of the substrate. Although, in some of the figures, the first and second grids are shown extending beyond the outer boundaries of the front surface of the microelectronic elements, that need not be the case. In certain embodiments of the invention, each of the first and second grids 114, 124 of first terminals can be configured to carry the above-noted address information or, in a particular embodiment, certain signals of the command-address bus.
For example, when the microelectronic element 101 includes or is a DRAM semiconductor chip, each of the first and second grids 114, 124 is configured to carry address information transferred to the microelectronic package 100 which is usable by circuitry within the package, e.g., row address and column address decoders, and bank selection circuitry, if present, to determine an addressable memory location from among all the available addressable memory locations of a memory storage array within a microelectronic element in the package. In a particular embodiment, each of the first and second grids 114, 124 can be configured to carry all the address information used by such circuitry within the microelectronic package 100 to determine an addressable memory location within such memory storage array.
In a variation of such embodiment, the first terminals of each of the first and second grids 114, 124 can be configured to carry a majority of the address information that is used by such circuitry within the microelectronic package 100 to determine an addressable memory location within such memory storage array, and then other terminals such as at least some of the above-referenced second terminals 106 on the microelectronic package would then be configured to carry the remaining part of the address information. In such variation, in a particular embodiment, the first terminals in each of the first and second grids 114, 124 are configured to carry three-quarters or more of the address information that is used by such circuitry within the microelectronic package 100 to determine an addressable memory location within such memory storage array.
In a particular embodiment, each of the first and second grids 114, 124 may not be configured to carry chip select information, e.g., information usable to select a particular chip within the microelectronic package 100 for access to a memory storage location within the chip. In another embodiment, at least one of the first and second grids 114, 124 may indeed carry chip select information.
Typically, when the microelectronic element 101 in the microelectronic package 100 is or includes a DRAM chip, the address information in one embodiment can include all address information transferred to the package from a component external to the package, e.g., a circuit panel such as the circuit panel 154 (
At least some of the second terminals 106 can be configured to carry signals other than the address signals that are carried by the first terminals 104 of the first and second grids 114, 124. In particular examples, the second terminals 106 may carry one or more of data, data strobe signals, or other signals or reference potentials such as chip select, reset, power supply voltages, e.g., Vdd, Vddq, and ground, e.g., Vss and Vssq. Some or all second terminals can be disposed at locations within the first and second grids 114, 124. In such case, some terminals disposed at locations within the first and second grids 114, 124 can be configured to carry one or more of data, data strobe signals, or other signals or reference potentials such as chip select, reset, power supply voltages, e.g., Vdd, Vddq, and ground, e.g., Vss and Vssq. Some terminals disposed at locations within the third and fourth grids 116, 126 can be configured to carry one or more of data, data strobe signals, or other signals or reference potentials such as chip select, reset, power supply voltages, e.g., Vdd, Vddq, and ground, e.g., Vss and Vssq.
In a particular embodiment, the first terminals of each of the first and second grids 114, 124 of each microelectronic package can be configured to carry information that controls an operating mode of the microelectronic element 101. More specifically, each of the first and second grids 114, 124 can be configured to carry all of a particular set of command signals and/or clock signals transferred to the microelectronic package 100. In one embodiment, the first terminals 104 can be configured to carry all of the command signals, address signals, bank address signals, and clock signals transferred to the microelectronic package 100 from an external component, e.g., circuit panel or other device, wherein the command signals include row address strobe, column address strobe and write enable.
In an embodiment in which one or more of the microelectronic elements are configured to provide dynamic memory storage array function, such as provided by a dynamic random access memory (“DRAM”) semiconductor chip, or an assembly of DRAM chips, the command signals can be write enable, row address strobe, and column address strobe signals. Other signals such as ODT (on die termination), chip select, clock enable, may or may not be carried by terminals disposed within the first and second grids 114, 124. The clock signals can be clocks used by one or more of the microelectronic elements for sampling the address signals. For example, in the microelectronic package of
In the embodiment illustrated in
In one embodiment, at least some of the second terminals 106 that are configured to carry signals other than the address signals can be arranged at positions within the first and second grids 114, 124. In one example, at least some of the second terminals 106 that are configured to carry signals other than the command signals, address signals, and clock signals can be arranged at positions within the first and second grids 114, 124. Although particular configurations of second terminals 106 are shown in the figures, the particular configurations shown are for illustrative purposes and are not meant to be limiting. For example, the second terminals 106 can also include terminals that are configured to be connected to power or ground signals.
An arrangement of the first terminals in the first and second grids 114, 124 of the package is particularly shown in
Moreover, it is possible for the grids of terminals to contain arrangements of terminals in groupings other than columns, such as in arrangements shaped like rings, polygons or even scattered distributions of terminals. As shown in
As seen in
The axis 131 about which the signal assignments of the first terminals are symmetric can be located at various positions on the substrate. In a particular embodiment, the axis can be a central axis of the package that is located equidistant from first and second opposed edges 140, 141 of the substrate particularly when the columns 136 of the first terminals extend in a direction parallel to the edges 140, 141 and the first and second grids are disposed at locations which are symmetric about this central axis. In one example, the axis 131 may be located within a distance no greater than three and one-half times a minimum pitch between any two adjacent columns of terminals from a line which is parallel to and equidistant from the first and second edges 140, 141 of the substrate. Alternatively, this axis of symmetry 131 can be offset in a horizontal direction 135 from the central axis that is equidistant between edges 140, 141.
In a particular example, terminals in the first and second grids can be located in a central region of the package. In one example, at least one column 136 of terminals in each of the first and second grids 114, 124 can be disposed within a distance not greater than three and one-half times the minimum pitch between any two adjacent parallel columns 136 of the terminals from a line which is equidistant from and parallel to the first and second edges 140, 141 of the substrate.
As mentioned above, the second terminals 106 can be configured to carry information other than the above-noted address information or other than signals of the above-noted command-address bus. In one example, the second terminals 106 can include terminals used for carrying uni-directional or bi-directional data signals to and or from the microelectronic element, and data strobe signals, as well as data masks and ODT or “on die termination” signals used to turn on or off parallel terminations to termination resistors. In particular examples, the second terminals may carry signals such as chip select, reset, clock enable, as well as reference potentials such as power supply voltages, e.g., Vdd, Vddq, or ground, e.g., Vss and Vssq. In some embodiments it is possible for some or all terminals that are configured to carry signals other than the command-address bus signals to be disposed as second terminals 106 on the package, wherever they can be suitably placed. For example, some or all of the second terminals 106 can be arranged in the same grids 114, 124 on the substrate 102 in which the first terminals 104 are arranged. Some or all of the second terminals 106 may be disposed in the same column or in different columns as some or all of the first terminals 104. In some cases, one or more second terminals can be interspersed with the first terminals in the same grids or column thereof.
In a particular example, some or all of the second terminals 106 can be disposed in a third grid 116 on the second surface 110 of the substrate, and another set of the second terminals can be disposed in a fourth grid 126 on the package surface 110. In a particular case, the signal assignments of the second terminals in the third grid 116 can be a mirror image of the signal assignments of the second terminals in the fourth grid 126, in like manner to that described above for the first and second grids. The third and fourth grids 116, 126 may in some cases extend in the direction 134 in which the first and second grids extend and can be parallel to one another. The third and fourth grids may also be parallel to the first and second grids 114, 124. Alternatively, referring to
Also, as shown in
As further shown in
In one example, “X” can be a number 2n (2 to the power of n), wherein n is greater than or equal to 2, or X can be 8×N, N being two or more. Thus, in one example, X may be equal to the number of bits in a half-byte (4 bits), byte (8 bits), multiple bytes (8−N, N being two or more), a word (32 bits) or multiple words. In such way, in one example, when there is modulo-8 symmetry as shown in
It is important to note that, although not shown, the modulo number “X” can be a number other than 211 (2 to the power of n) and can be any number greater than two. Thus, the modulo number X upon which the symmetry is based can depend upon how many bits are present in a data size for which the package is constructed or configured. For example, when the data size is 10 bits instead of 8, then the signal assignments may have modulo-10 symmetry. It may even be the case that when the data size has an odd number of bits, the modulo number X can have such number.
As particularly shown in
To be sure, the alignment of each pair of connected terminals can be within a tolerance, such that each pair of connected terminals can be aligned within one ball pitch of one another in orthogonal x and y directions along the first surface 150 of the circuit panel 154. As evident from
In a particular example, at least half of the positions of the aligned grids of the respective first and second packages 100A, 100B (e.g., the first grid 114A of the first package and the second grid 124B of the second package) can be aligned with one another in orthogonal x and y directions along the first surface 150 of the circuit panel 154.
Thus, as further shown in
In this way, as further seen in
Therefore, referring to
As further shown in
Thus, as further shown in
Similar to the connections between corresponding first terminals 104 of first and second packages as described above, in this embodiment, the lengths of the electrical connections through the circuit panel between pairs of electrically connected second terminals 106 of the first and second packages can be significantly reduced, in that the terminals in each of these pairs of electrically connected second terminals may be coincident with one another, or at least be aligned within one ball pitch of one another in orthogonal x and y directions parallel to the circuit panel surface. Moreover, benefits similar to those described above for reducing stub lengths and simplifying the construction of a circuit panel for the connections between the first and second packages may be obtained when the second terminals of a microelectronic package are arranged in this way, i.e., terminals which can be assigned to carry signals other than the above-noted signals of the command-address bus.
Such a configuration, particularly when the terminals of the first grid 104 of each microelectronic package are arranged in one or more columns extending in such direction 142, may help simplify the routing of signal conductors of one or more global routing layers on the circuit panel used to route the signals of the bus 36. For example, it may be possible to simplify routing of the command-address bus signals on a circuit panel when relatively few first terminals are disposed at the same vertical layout position on each package. Thus, in the example shown in
In one embodiment, the microelectronic assembly 354 can have a microelectronic element 358 that can include a semiconductor chip configured to perform buffering of at least some signals transferred to the microelectronic packages 100A, 100B of the assembly 354. Such a microelectronic element 358 having a buffering function can be configured to help provide impedance isolation for each of the microelectronic elements in the microelectronic packages 100A and 100B with respect to components external to the microelectronic assembly 354.
In an exemplary embodiment, the microelectronic assembly 354 can have a microelectronic element 358 that can include a semiconductor chip configured predominantly to perform a logic function, such as a solid state drive controller, and one or more of the microelectronic elements in the microelectronic packages 100A and 100B can each include memory storage elements such as nonvolatile flash memory. The microelectronic element 358 can include a special purpose processor that is configured to relieve a central processing unit of a system such as the system 2500 (
In such an embodiment of the microelectronic assembly 354 having a microelectronic element 358 that includes a controller function and/or a buffering function, the command-address bus signals can be routed between the microelectronic element 358 and each pair of packages 100A and 100B at respective connection sites I, II or III. In the particular example shown in
When the microelectronic package includes a vertically stacked arrangement of semiconductor chips such as seen in
Alternatively or in addition to regenerating signals as described above, in one example, the first chip in such a composite microelectronic element can be configured to partially or fully decode information that controls an operating mode of the microelectronic element. In a particular example, the first semiconductor chip in such composite microelectronic element can be configured to partially or fully decode at least one of address information or command information received at the terminals, such as at the first terminals of the microelectronic package. The first chip can then output the result of such partial or full decoding for transfer to the one or more second semiconductor chips 101A, 101B.
Signals or information received at the terminals of the package can be routed to substrate contacts 115 and through joining elements 118 to semiconductor chip 109. Semiconductor chip 109 can then regenerate and transfer the received signals or information to substrate contacts 117. From the substrate contacts 117, the signals or information may be routed by the substrate, such as through conductive traces thereon to substrate contacts 111, 113 where they are then routed to the semiconductor chips 101A, 101B such as through wirebonds 112. In a particular example, the semiconductor chip 109 can be configured to buffer the above-noted command signals, address signals and clock signals transferred to the semiconductor chips 101A, 101B.
In the microelectronic package 600 seen in
Alternatively, in another example, the one or more second semiconductor chips 634 may embody a greater number of active devices to provide memory storage array function than any other function, but the first semiconductor chip 632 may be a different type of chip. In this case, the first semiconductor chip 632 can be configured, e.g., designed, constructed, or set up, to buffer signals, i.e., regenerate signals received at the terminals for transfer to the one or more second semiconductor chips 634, or to regenerate signals received from one or more of the second semiconductor chips 634 for transfer to the terminals, or to regenerate signals being transferred in both directions from the terminals to the one or more second semiconductor chips 634; and from the one or more semiconductor chips to the terminals of the microelectronic package.
In a particular example, the first semiconductor chip can be configured to buffer address information or may be configured to buffer command signals, address signals and clock signals which are transferred to the one or more second semiconductor chips. For example, the first semiconductor chip 632 can be a buffer chip which embodies a greater number of active devices to provide a buffering function in transferring signals to other devices, e.g., to the one or more second semiconductor chips 634, than for any other function. Then, the one or more second semiconductor chips may be reduced function chips which have memory storage arrays but which can omit circuitry common to DRAM chips, such as buffer circuitry, decoders or predecoders or wordline drivers, among others. In that case, the first chip 632 may function as a “master” chip in the stack and to control operations in each of the second semiconductor chips 634. In a particular example, the second semiconductor chips may be configured such that they are not capable of performing the buffering function, and so the stacked arrangement of the first and second semiconductor chips is configured such that the buffering function required in the microelectronic package can be performed by the first semiconductor chip, and cannot be performed by any of the second semiconductor chips in the stacked arrangement. Similar to that described above, the first semiconductor chip may be configured to partially or fully decode information received at the first terminals that controls an operating mode of the microelectronic element made up of the first and second semiconductor chips. Alternatively, or in addition thereto, the first semiconductor chip may be configured to partially or fully decode at least one of address or command information received at the first terminals. In a particular example, one or more of the second semiconductor chips may not be configured to fully decode information received at the first terminals of the microelectronic package, such as address information, command information or information that controls an operating mode of the microelectronic element.
In any of the embodiments described herein, the one or more second semiconductor chips can be implemented in one or more of the following technologies: DRAM, NAND flash memory, RRAM (“resistive RAM” or “resistive random access memory”), phase-change memory (“PCM”), magnetoresistive random access memory, e.g. such as may embodiment tunnel junction devices, spin-torque RAM, or content-addressable memory, among others.
The electrical connections between the second semiconductor chips 634 may further include traces 644 which extend along front faces of the second semiconductor chips 634. As further shown in
In one example, information or signals received at terminals of the package 690, such as at the first terminals, the second terminals, or both, can be received by the first semiconductor chip 632 through wire bonds 645 which are joined to substrate contacts 636, which in turn are joined to such terminals of the microelectronic package. The first semiconductor chip 632, operating as a buffer element, can then regenerate the received information or signals and then transfer the regenerated information or signals to the one or more second semiconductor chips, e.g., through the connections between the first and second chips 632, 634 and through the TSVs 650 within the stack of second chips 634.
Semiconductor chip 664 can be electrically connected to terminals of the microelectronic package, e.g., to grids in which the first terminals 604 and the second terminals 606 are disposed, through electrically conductive structure, e.g., wire bonds 665, which partially overlies a front face 631 of semiconductor chip 663A and which connects to contacts 636 exposed at the first surface 108 of the substrate. The electrically conductive structure, e.g., wire bonds 665, can electrically connect to semiconductor chip 664 through contacts 638 on a chip 663A and through conductors (not shown) which extend along the face 631 of chip 663A or along confronting face 641 of chip 664, or which conductors extend along the faces 631, 641 of both of the chips 663A, 664. As indicated above, semiconductor chip 664 may be configured to regenerate or at least partially decode signals or information that it receives through the conductive structure, e.g., wire bonds 665, and be configured to transfer the regenerated or at least partially decoded signals or information to other chips within the package such as to chips 662, and 663A, 663B and 663C.
As further seen in
As further seen in
The microelectronic assembly 695 shown in
Providing duplicate sets of first terminals in first and second parallel grids in which the signal assignments in one grid are a mirror image of the signal assignments in the other grid can help reduce the lengths of stubs in an assembly of first and second microelectronic packages mounted opposite one another to a circuit panel. When first and second microelectronic packages are connected to opposite mounting surfaces of a circuit panel with the circuit panel electrically interconnecting the packages, each of the first terminals of the first grid of the first package can be aligned within one ball pitch of the corresponding first terminal of the second, mirror image grid of the second package to which it is electrically connected. In addition, each of the first terminals of the first grid of the second package can be so aligned within one ball pitch of the corresponding first terminals of the second, mirror image grid of the first package to which they connect. As a result, each first terminal of the first package can be electrically connected with a corresponding first terminal of the second package, with the mounting locations of each pair of terminals on the opposite circuit panel surfaces being within one ball pitch of each other in orthogonal x and y directions parallel to one of the surfaces of the circuit panel. In some cases, the mounting locations of each pair of connected terminals on the opposite circuit panel surfaces may even be coincident with one another. Accordingly, the lengths of the electrical connections through the circuit panel between pairs of electrically connected first terminals of the first and second packages can be significantly reduced, in that the terminals in each of these pairs of electrically connected first terminals may be coincident with one another, or otherwise aligned within one ball pitch of one another in x and y orthogonal directions along the first circuit panel surface.
The circuit panel construction may also be simplified in an assembly having this construction because the routing between each electrically connected pair of first terminals can be mostly in a vertical direction, i.e., in a direction through the thickness of the circuit panel. That is, via connections on the circuit panel may be all that is needed to electrically connect each pair of corresponding first terminals of the packages mounted to the opposite surfaces of the circuit panel.
Moreover, the number of global routing layers of wiring on the circuit panel required to route the above-noted address information on a bus 36 (
The microelectronic package may also have second terminals other than the first terminals, such terminals typically being configured to carry signals other than the above-noted command-address bus signals. In one example, the second terminals can include terminals used for carrying uni-directional or bi-directional data signals to and or from the microelectronic element, and data strobe signals, as well as data masks and ODT or “on die termination” signals used to turn on or off parallel terminations to termination resistors. Signals or reference potentials such as chip select, reset, power supply voltages, e.g., Vdd, Vddq, and ground, e.g., Vss and Vssq, may also be carried by the second terminals; none of the signals or reference potentials needs to be carried by the first terminals. In some embodiments it is possible for some or all terminals configured to carry signals other than the command-address bus signals to be disposed as second terminals in any locations on the package.
Alternatively, in some embodiments it is possible for some or all terminals which are configured to carry signals other than the command-address bus signals to also be disposed in the first grid and within the second, mirror image grid of first terminals on the package. In this way, it may be possible to reduce the stub lengths in the electrical connections provided on a circuit panel between these corresponding first terminals, as described above.
In other embodiments, some or all of the terminals which are configured to carry signals other than the command-address bus signals can be arranged as a set of second terminals in a third grid on the package surface, and another set of the second terminals can be arranged in a fourth grid on the same package surface, in which the signal assignments of the second terminals in the third grid are a mirror image of the signal assignments of the second terminals in the fourth grid. In this way, similar to the connections between corresponding first terminals of first and second packages as described above, the lengths of the electrical connections through the circuit panel between pairs of electrically connected second terminals of the first and second packages can be significantly reduced, in that the terminals in each of these pairs of electrically connected second terminals may be coincident with one another, or otherwise aligned within one ball pitch of one another. Moreover, benefits similar to those described above for reducing stub lengths and simplifying the construction of a circuit panel for the connections between the first and second packages may be obtained when second terminals of a microelectronic package are arranged in this way.
Referring to
As seen in
An arrangement of the first terminals in the first and second grids 1414, 1424 of the package can be as particularly shown in
The axial plane 1432 about which the signal assignments of the first terminals are symmetric can be located at various positions on the substrate. In a particular embodiment, the axial plane can intersect the surface 1410 of the substrate along a line on the surface that is located equidistant from first and second opposed edges 1440, 1442 of the substrate, particularly when the columns 1438 of the first terminals extend in a direction parallel to the edges 1440, 1442 and the first and second grids are disposed at locations which are symmetric about this central axis.
In a particular example, the first terminals 1404 of the first grid 1414 can be electrically connected with the first microelectronic element 1401, and the first terminals 1404 of the second grid 1424 can be electrically connected with the second microelectronic element 1403. In such case, the first terminals 1404 of the first grid 1414 may also be not electrically connected with the second microelectronic element 1403, and the first terminals 1404 of the second grid 1424 of the package 1400 may also be not electrically connected with the first microelectronic element 1401. In yet another example, the first terminals 1404 of each of the first and second grids 1414 can be electrically connected with each of the first and second microelectronic elements 1401, 1403.
As mentioned above, the second terminals 1406 can be configured to carry information or signals other than the above-noted address information or signals of the command-address bus. In one example, the second terminals 1406 can include terminals used for carrying uni-directional or bi-directional data signals to and or from the microelectronic element, and data strobe signals, as well as data masks and ODT or “on die termination” signals used by the chip to turn on or off parallel terminations to termination resistors. Signals such as chip select, reset, clock enable, as well as reference potentials such as power supply voltages, e.g., Vdd, Vddq, or ground, e.g., Vss and Vssq, can be among the signals carried by either the first terminals 1404 or the second terminals 1406. However, none of these signals or reference potentials needs to be carried by the first terminals 1404. As further shown in
As shown in
As particularly shown in
Thus, as further shown in
In this way, as further seen in
As further shown in
Thus, as further shown in
Similar to the connections between corresponding first terminals 1404 of first and second packages as described above, in this embodiment, the lengths of the electrical connections through the circuit panel between pairs of electrically connected second terminals 1406 of the first and second packages can be significantly reduced, in that the terminals in each of these pairs of electrically connected second terminals may overlie one another, or at least be aligned within one ball pitch of one another in orthogonal x and y directions parallel to the circuit panel surface. Moreover, benefits similar to those described above for reducing stub lengths and simplifying the construction of a circuit panel for the connections between the first and second packages may be obtained when the second terminals of a microelectronic package are arranged in this way, i.e., terminals which can be assigned to carry signals other than the above-noted signals of the command-address bus.
In a further variation of the embodiment shown in
In other variations, one or more of the microelectronic elements 1401, 1403 in the package 1490 can be constructed as described above with reference to
As shown in
As further seen in
As seen in
Grids 1651, 1653, 1655, 1657 of second terminals, which may overlie portions of respective microelectronic elements 1601, 1603, 1605, 1607 and are electrically connected therewith, can have terminals disposed in any suitable arrangement, there being no requirement to place these second terminals in grids in which the signal assignments in any one of the grids 1651, 1653, 1655, or 1657 are a mirror image of the signal assignments of the terminals in any one of the other grids 1651, 1653, 1655, or 1657.
In a particular example, the signal assignments of the second terminals in any one of the grids 1651, 1653, 1655, or 1657 can be a mirror image of the signal assignments of the second terminals in one or two other ones of the grids 1651, 1653, 1655, or 1657, in that the signal assignments of any one of the grids can be symmetric about a vertical axis 1680 in a vertical layout direction parallel to the substrate surface 1602 with respect to the signal assignments of another grid. Alternatively, or in addition thereto, the signal assignments of any one of the grids can be symmetric about a horizontal axis 1682 with respect to the signal assignments of another grid.
For example, as shown in
In the particular example shown in
Grids 1755, 1757 of second terminals, which may overlie portions of microelectronic elements 1705, 1707 and are electrically connected therewith, can have terminals disposed in any suitable arrangement, there being no requirement to place these second terminals in grids in which the signal assignments in one of the grids 1755 are a mirror image of the signal assignments of the terminals in the other grid 1757. However, in a particular example, the signal assignments of the second terminals in a grid 1755 can be a mirror image of the signal assignments of the second terminals in another grid 1757, in that the signal assignments can be symmetric about an axis 1735 extending in a direction 1722 between grids 1755 and 1758. In this case, there can be symmetry about an axis 1735 extending in the horizontal direction of
Moreover, such configuration can be provided in a microelectronic package in which symmetries in the signal assignments between the grids of first terminals or between the other grids 1751, 1753 of second terminals may optionally be provided. As further illustrated in
Alternatively or in addition thereto, the area of the substrate 1702 between the adjacent edges 1710, 1730 of the microelectronic elements may permit one or more decoupling capacitors to be provided on or in the package which are connected to internal power supply or ground buses of the package.
In addition, it is further seen that there is a plane 1840 normal to the substrate which contains one of the first edges 1810 of microelectronic element 1801, and which intersects the first edge 1830 of another microelectronic element 1805. Similarly, there is a plane 1842 normal to the substrate which contains one of the first edges 1830 of microelectronic element 1805, and which intersects the first edge 1810 of another microelectronic element 1803. From an inspection of
The microelectronic packages and microelectronic assemblies described above with reference to
In the exemplary system 2500 shown, the system can include a circuit panel, motherboard, or riser panel 2502 such as a flexible printed circuit board, and the circuit panel can include numerous conductors 2504, of which only one is depicted in
In a particular embodiment, the system 2500 can also include a processor such as the semiconductor chip 2508, such that each module or component 2506 can be configured to transfer a number N of data bits in parallel in a clock cycle, and the processor can be configured to transfer a number M of data bits in parallel in a clock cycle, M being greater than or equal to N.
In one example, the system 2500 can include a processor chip 2508 that is configured to transfer thirty-two data bits in parallel in a clock cycle, and the system can also include four modules 2506 such as the microelectronic package 100 described with reference to
In another example, the system 2500 can include a processor chip 2508 that is configured to transfer sixty-four data bits in parallel in a clock cycle, and the system can also include four modules 2506 such as the microelectronic package described with reference to any one of
In the example depicted in
Modules or components 2506 and components 2508 and 2511 can be mounted in a common housing 2501, schematically depicted in broken lines, and can be electrically interconnected with one another as necessary to form the desired circuit. The housing 2501 is depicted as a portable housing of the type usable, for example, in a cellular telephone or personal digital assistant, and screen 2510 can be exposed at the surface of the housing. In embodiments where a structure 2506 includes a light-sensitive element such as an imaging chip, a lens 2511 or other optical device also can be provided for routing light to the structure. Again, the simplified system shown in
Various features of the above-described embodiments of the invention can be combined in ways other than as specifically described above without departing from the scope or spirit of the invention. It is intended for the present disclosure to cover all such combinations and variations of embodiments of the invention described above.
This application is a continuation of U.S. patent application Ser. No. 13/440,280, filed Apr. 5, 2012, now U.S. Pat. No. 9,287,195, which claims the benefit of the filing date of U.S. Provisional Application No. 61/600,527 filed Feb. 17, 2012, and the benefit of the filing date of U.S. Provisional Application Nos. 61/542,488, 61/542,495, and 61/542,553, all filed Oct. 3, 2011, all of which are hereby incorporated herein by reference.
Number | Name | Date | Kind |
---|---|---|---|
3670208 | Hovnanian et al. | Jun 1972 | A |
4747081 | Heilveil et al. | May 1988 | A |
5148265 | Khandros et al. | Sep 1992 | A |
5148266 | Khandros et al. | Sep 1992 | A |
5163024 | Heilveil et al. | Nov 1992 | A |
5210639 | Redwine et al. | May 1993 | A |
5480840 | Barnes et al. | Jan 1996 | A |
5679977 | Khandros et al. | Oct 1997 | A |
5691570 | Kozuka | Nov 1997 | A |
5751553 | Clayton | May 1998 | A |
5777391 | Nakamura et al. | Jul 1998 | A |
5821614 | Hashimoto et al. | Oct 1998 | A |
5899705 | Akram | May 1999 | A |
5929517 | Distefano et al. | Jul 1999 | A |
5936305 | Akram | Aug 1999 | A |
5949700 | Furukawa et al. | Sep 1999 | A |
5973403 | Wark | Oct 1999 | A |
6086386 | Fjelstad et al. | Jul 2000 | A |
6130116 | Smith et al. | Oct 2000 | A |
6159837 | Yamaji et al. | Dec 2000 | A |
6177636 | Fjelstad | Jan 2001 | B1 |
6197665 | DiStefano et al. | Mar 2001 | B1 |
6252264 | Bailey et al. | Jun 2001 | B1 |
6255899 | Bertin et al. | Jul 2001 | B1 |
6261867 | Robichaud et al. | Jul 2001 | B1 |
6297960 | Moden et al. | Oct 2001 | B1 |
6313532 | Shimoishizaka et al. | Nov 2001 | B1 |
6323436 | Hedrick et al. | Nov 2001 | B1 |
6343019 | Jiang et al. | Jan 2002 | B1 |
6376769 | Chung | Apr 2002 | B1 |
6380318 | Saito et al. | Apr 2002 | B1 |
6384473 | Peterson et al. | May 2002 | B1 |
6426560 | Kawamura et al. | Jul 2002 | B1 |
6433422 | Yamasaki | Aug 2002 | B1 |
6445594 | Nakagawa et al. | Sep 2002 | B1 |
6452266 | Iwaya et al. | Sep 2002 | B1 |
6461895 | Liang et al. | Oct 2002 | B1 |
6462423 | Akram et al. | Oct 2002 | B1 |
6518794 | Coteus et al. | Feb 2003 | B2 |
6521981 | Miyazaki et al. | Feb 2003 | B2 |
6560134 | Brox et al. | May 2003 | B2 |
6577004 | Rumsey et al. | Jun 2003 | B1 |
6611057 | Mikubo et al. | Aug 2003 | B2 |
6617695 | Kasatani | Sep 2003 | B1 |
6619973 | Perino et al. | Sep 2003 | B2 |
6620648 | Yang | Sep 2003 | B2 |
6628528 | Schoenborn | Sep 2003 | B2 |
6633078 | Hamaguchi et al. | Oct 2003 | B2 |
6658530 | Robertson et al. | Dec 2003 | B1 |
6661089 | Huang | Dec 2003 | B2 |
6692987 | Lim et al. | Feb 2004 | B2 |
6707141 | Akram | Mar 2004 | B2 |
6720666 | Lim et al. | Apr 2004 | B2 |
6742098 | Halbert et al. | May 2004 | B1 |
6744137 | Kinsman | Jun 2004 | B2 |
6765288 | Damberg | Jul 2004 | B2 |
6781220 | Taube et al. | Aug 2004 | B2 |
6821815 | Smith et al. | Nov 2004 | B2 |
6836007 | Michii et al. | Dec 2004 | B2 |
6876088 | Harvey | Apr 2005 | B2 |
6894379 | Feurle | May 2005 | B2 |
6894381 | Hetzel et al. | May 2005 | B2 |
6906415 | Jiang et al. | Jun 2005 | B2 |
6943057 | Shim et al. | Sep 2005 | B1 |
6977440 | Pflughaupt et al. | Dec 2005 | B2 |
6982485 | Lee et al. | Jan 2006 | B1 |
7061092 | Akram et al. | Jun 2006 | B2 |
7061105 | Masuda et al. | Jun 2006 | B2 |
7061121 | Haba | Jun 2006 | B2 |
7074696 | Frankowsky et al. | Jul 2006 | B1 |
7091064 | Jiang | Aug 2006 | B2 |
7122897 | Aiba et al. | Oct 2006 | B2 |
7123497 | Matsui et al. | Oct 2006 | B2 |
7138709 | Kumamoto | Nov 2006 | B2 |
7141879 | Wakamiya et al. | Nov 2006 | B2 |
7145226 | Kumamoto | Dec 2006 | B2 |
7151319 | Iida et al. | Dec 2006 | B2 |
7164149 | Matsubara | Jan 2007 | B2 |
7170158 | Choi et al. | Jan 2007 | B2 |
7262507 | Hino et al. | Aug 2007 | B2 |
7272888 | DiStefano | Sep 2007 | B2 |
7294928 | Bang et al. | Nov 2007 | B2 |
7324352 | Goodwin | Jan 2008 | B2 |
7368319 | Ha et al. | May 2008 | B2 |
7372169 | Chang | May 2008 | B2 |
7389937 | Ito | Jun 2008 | B2 |
7405471 | Kledzik et al. | Jul 2008 | B2 |
7414312 | Nguyen et al. | Aug 2008 | B2 |
7420284 | Miyazaki et al. | Sep 2008 | B2 |
7476975 | Ogata | Jan 2009 | B2 |
7518226 | Cablao et al. | Apr 2009 | B2 |
7535110 | Wu et al. | May 2009 | B2 |
7550842 | Khandros et al. | Jun 2009 | B2 |
7589409 | Gibson et al. | Sep 2009 | B2 |
7633146 | Masuda et al. | Dec 2009 | B2 |
7633147 | Funaba et al. | Dec 2009 | B2 |
7642635 | Kikuchi et al. | Jan 2010 | B2 |
7692278 | Periaman et al. | Apr 2010 | B2 |
7692931 | Chong et al. | Apr 2010 | B2 |
7763964 | Matsushima | Jul 2010 | B2 |
7763969 | Zeng et al. | Jul 2010 | B2 |
RE41478 | Nakamura et al. | Aug 2010 | E |
RE41721 | Nakamura et al. | Sep 2010 | E |
RE41722 | Nakamura et al. | Sep 2010 | E |
7795721 | Kurita | Sep 2010 | B2 |
RE41972 | Lenander et al. | Nov 2010 | E |
7855445 | Landry et al. | Dec 2010 | B2 |
7989940 | Haba et al. | Aug 2011 | B2 |
RE42972 | Nakamura et al. | Nov 2011 | E |
8072037 | Murphy et al. | Dec 2011 | B2 |
8138015 | Joseph et al. | Mar 2012 | B2 |
8254155 | Crisp et al. | Aug 2012 | B1 |
8278764 | Crisp et al. | Oct 2012 | B1 |
8338963 | Haba et al. | Dec 2012 | B2 |
8345441 | Crisp et al. | Jan 2013 | B1 |
8378478 | Desai et al. | Feb 2013 | B2 |
8405207 | Crisp et al. | Mar 2013 | B1 |
8426983 | Takeda et al. | Apr 2013 | B2 |
8432046 | Miyata et al. | Apr 2013 | B2 |
8436457 | Crisp et al. | May 2013 | B2 |
8436477 | Crisp et al. | May 2013 | B2 |
8441111 | Crisp et al. | May 2013 | B2 |
8502390 | Crisp et al. | Aug 2013 | B2 |
8513813 | Crisp et al. | Aug 2013 | B2 |
8513817 | Haba et al. | Aug 2013 | B2 |
8525327 | Crisp et al. | Sep 2013 | B2 |
8610260 | Crisp et al. | Dec 2013 | B2 |
8629545 | Crisp et al. | Jan 2014 | B2 |
8653646 | Crisp et al. | Feb 2014 | B2 |
8659139 | Crisp et al. | Feb 2014 | B2 |
8659140 | Crisp et al. | Feb 2014 | B2 |
8659141 | Crisp et al. | Feb 2014 | B2 |
8659142 | Crisp et al. | Feb 2014 | B2 |
8659143 | Crisp et al. | Feb 2014 | B2 |
8670261 | Crisp et al. | Mar 2014 | B2 |
8823165 | Haba et al. | Sep 2014 | B2 |
8902680 | Yamamoto | Dec 2014 | B2 |
8917532 | Crisp et al. | Dec 2014 | B2 |
8981547 | Crisp et al. | Mar 2015 | B2 |
20010002727 | Shiraishi et al. | Jun 2001 | A1 |
20010013662 | Kudou et al. | Aug 2001 | A1 |
20010022740 | Nuxoll et al. | Sep 2001 | A1 |
20010038106 | Coteus et al. | Nov 2001 | A1 |
20020000583 | Kitsukawa et al. | Jan 2002 | A1 |
20020016056 | Corisis | Feb 2002 | A1 |
20020027019 | Hashimoto | Mar 2002 | A1 |
20020030261 | Rolda et al. | Mar 2002 | A1 |
20020043719 | Iwaya et al. | Apr 2002 | A1 |
20020053727 | Kimura | May 2002 | A1 |
20020053732 | Iwaya et al. | May 2002 | A1 |
20020066950 | Joshi | Jun 2002 | A1 |
20020105096 | Hirata et al. | Aug 2002 | A1 |
20020130412 | Nagai et al. | Sep 2002 | A1 |
20020171142 | Kinsman | Nov 2002 | A1 |
20030064547 | Akram et al. | Apr 2003 | A1 |
20030089978 | Miyamoto et al. | May 2003 | A1 |
20030089982 | Feurle | May 2003 | A1 |
20030107118 | Pflughaupt et al. | Jun 2003 | A1 |
20030107908 | Jang et al. | Jun 2003 | A1 |
20030168748 | Katagiri | Sep 2003 | A1 |
20030205801 | Baik et al. | Nov 2003 | A1 |
20030211660 | Lim et al. | Nov 2003 | A1 |
20040016999 | Misumi | Jan 2004 | A1 |
20040061211 | Michii et al. | Apr 2004 | A1 |
20040061577 | Breisch et al. | Apr 2004 | A1 |
20040090756 | Ho et al. | May 2004 | A1 |
20040112088 | Ueda et al. | Jun 2004 | A1 |
20040145042 | Morita et al. | Jul 2004 | A1 |
20040145054 | Bang et al. | Jul 2004 | A1 |
20040164382 | Gerber et al. | Aug 2004 | A1 |
20040168826 | Jiang et al. | Sep 2004 | A1 |
20040184240 | Su | Sep 2004 | A1 |
20040201111 | Thurgood | Oct 2004 | A1 |
20050116358 | Haba | Jun 2005 | A1 |
20050194672 | Gibson et al. | Sep 2005 | A1 |
20050206585 | Stewart et al. | Sep 2005 | A1 |
20050243590 | Lee et al. | Nov 2005 | A1 |
20050258532 | Yoshikawa et al. | Nov 2005 | A1 |
20060004981 | Bains | Jan 2006 | A1 |
20060081983 | Humpston et al. | Apr 2006 | A1 |
20060087013 | Hsieh | Apr 2006 | A1 |
20060091518 | Grafe et al. | May 2006 | A1 |
20060170093 | Pendse | Aug 2006 | A1 |
20060192282 | Suwa | Aug 2006 | A1 |
20060207788 | Yoon et al. | Sep 2006 | A1 |
20060290005 | Thomas et al. | Dec 2006 | A1 |
20070025131 | Ruckerbauer et al. | Feb 2007 | A1 |
20070108592 | Lai et al. | May 2007 | A1 |
20070120245 | Yoshikawa et al. | May 2007 | A1 |
20070143553 | LaBerge | Jun 2007 | A1 |
20070187836 | Lyne | Aug 2007 | A1 |
20070241441 | Choi et al. | Oct 2007 | A1 |
20070260841 | Hampel et al. | Nov 2007 | A1 |
20080012110 | Chong et al. | Jan 2008 | A1 |
20080052462 | Blakely et al. | Feb 2008 | A1 |
20080061423 | Brox et al. | Mar 2008 | A1 |
20080074930 | Kanda | Mar 2008 | A1 |
20080088030 | Eldridge et al. | Apr 2008 | A1 |
20080088033 | Humpston et al. | Apr 2008 | A1 |
20080098277 | Hazelzet | Apr 2008 | A1 |
20080150155 | Periaman et al. | Jun 2008 | A1 |
20080182443 | Beaman et al. | Jul 2008 | A1 |
20080185705 | Osborn et al. | Aug 2008 | A1 |
20080191338 | Park et al. | Aug 2008 | A1 |
20080230888 | Sasaki | Sep 2008 | A1 |
20080256281 | Fahr et al. | Oct 2008 | A1 |
20080265397 | Lin et al. | Oct 2008 | A1 |
20090001574 | Fang et al. | Jan 2009 | A1 |
20090065948 | Wang | Mar 2009 | A1 |
20090108425 | Lee et al. | Apr 2009 | A1 |
20090140442 | Lin | Jun 2009 | A1 |
20090200680 | Shinohara et al. | Aug 2009 | A1 |
20090250255 | Shilling et al. | Oct 2009 | A1 |
20090250822 | Chen et al. | Oct 2009 | A1 |
20090294938 | Chen | Dec 2009 | A1 |
20090314538 | Jomaa et al. | Dec 2009 | A1 |
20100052111 | Urakawa | Mar 2010 | A1 |
20100090326 | Baek et al. | Apr 2010 | A1 |
20100102428 | Lee et al. | Apr 2010 | A1 |
20100182040 | Feng et al. | Jul 2010 | A1 |
20100244272 | Lee et al. | Sep 2010 | A1 |
20100244278 | Shen | Sep 2010 | A1 |
20100295166 | Kim | Nov 2010 | A1 |
20100301466 | Taoka et al. | Dec 2010 | A1 |
20100327457 | Mabuchi | Dec 2010 | A1 |
20110042824 | Koide | Feb 2011 | A1 |
20110084758 | Shibata et al. | Apr 2011 | A1 |
20110110165 | Gillingham et al. | May 2011 | A1 |
20110140247 | Pagaila et al. | Jun 2011 | A1 |
20110149493 | Kwon et al. | Jun 2011 | A1 |
20110193178 | Chang et al. | Aug 2011 | A1 |
20110193226 | Kirby et al. | Aug 2011 | A1 |
20110254156 | Lin | Oct 2011 | A1 |
20120018863 | Oganesian et al. | Jan 2012 | A1 |
20120020026 | Oganesian et al. | Jan 2012 | A1 |
20120153435 | Haba et al. | Jun 2012 | A1 |
20120155049 | Haba et al. | Jun 2012 | A1 |
20120206181 | Lin et al. | Aug 2012 | A1 |
20120217645 | Pagaila | Aug 2012 | A1 |
20120313239 | Zohni | Dec 2012 | A1 |
20120313253 | Nakadaira et al. | Dec 2012 | A1 |
20130009308 | Kwon | Jan 2013 | A1 |
20130009318 | Chia et al. | Jan 2013 | A1 |
20130015590 | Haba et al. | Jan 2013 | A1 |
20130082394 | Crisp et al. | Apr 2013 | A1 |
20130083583 | Crisp et al. | Apr 2013 | A1 |
20130168843 | Zohni | Jul 2013 | A1 |
20130286707 | Crisp et al. | Oct 2013 | A1 |
20130307138 | Crisp et al. | Nov 2013 | A1 |
20140042644 | Haba et al. | Feb 2014 | A1 |
20140055941 | Crisp et al. | Feb 2014 | A1 |
20140055942 | Crisp et al. | Feb 2014 | A1 |
20140055970 | Crisp et al. | Feb 2014 | A1 |
20140362629 | Crisp et al. | Dec 2014 | A1 |
Number | Date | Country |
---|---|---|
1477688 | Feb 2004 | CN |
101149964 | Mar 2008 | CN |
1205977 | May 2002 | EP |
61-093694 | May 1986 | JP |
63-232389 | Sep 1988 | JP |
64-001257 | Jan 1989 | JP |
H11-087640 | Mar 1999 | JP |
2000196008 | Jul 2000 | JP |
2000315776 | Nov 2000 | JP |
2002-076252 | Mar 2002 | JP |
2002083897 | Mar 2002 | JP |
2003051545 | Feb 2003 | JP |
2004-063767 | Feb 2004 | JP |
2004063767 | Feb 2004 | JP |
2004152131 | May 2004 | JP |
2005340724 | Dec 2005 | JP |
2006310411 | Nov 2006 | JP |
2007013146 | Jan 2007 | JP |
2007149977 | Jun 2007 | JP |
2008016666 | Jan 2008 | JP |
2008135597 | Jun 2008 | JP |
2008-198841 | Aug 2008 | JP |
3143893 | Aug 2008 | JP |
2009182163 | Aug 2009 | JP |
2010-098098 | Apr 2010 | JP |
2010282510 | Dec 2010 | JP |
2011096268 | May 2011 | JP |
2011155203 | Aug 2011 | JP |
2001-0002214 | Jan 2001 | KR |
2005-0119414 | Dec 2005 | KR |
2006-0120365 | Nov 2006 | KR |
2007-0088177 | Aug 2007 | KR |
2009-0008341 | Jan 2009 | KR |
2009-0086314 | Aug 2009 | KR |
312044 | Aug 1997 | TW |
428258 | Apr 2001 | TW |
429561 | Apr 2001 | TW |
478137 | Mar 2002 | TW |
567593 | Dec 2003 | TW |
M338433 | Aug 2008 | TW |
200842998 | Nov 2008 | TW |
200901194 | Jan 2009 | TW |
200926312 | Jun 2009 | TW |
M363079 | Aug 2009 | TW |
M398313 | Feb 2011 | TW |
201115659 | May 2011 | TW |
201208004 | Feb 2012 | TW |
M426922 | Apr 2012 | TW |
201222684 | Jun 2012 | TW |
201234556 | Aug 2012 | TW |
2010120310 | Oct 2010 | WO |
Entry |
---|
International Search Report and Written Opinion for Application No. PCT/US2012/058423 dated Mar. 20, 2013. |
International Search Report and Written Opinion dated Mar. 21, 2013 for Application No. PCT/US2012/057911. |
International Search Report and Written Opinion for Application No. PCT/US2012/046255 dated Mar. 20, 2013. |
International Search Report and Written Opinion dated Mar. 21, 2013 for Application No. PCT/US2012/000425. |
International Search Report and Written Opinion for Application No. PCT/US2012/058407 dated Mar. 28, 2013. |
International Search Report and Written Opinion for Application No. PCT/US2012/057179 dated Apr. 4, 2013. |
International Search Report and Written Opinion for Application No. PCT/US2012/057895 dated Jun. 10, 2013. |
International Search Report and Written Opinion for Application No. PCT/US2012/058434 dated Jun. 21, 2013. |
International Search Report and Written Opinion for Application No. PCT/US2012/058398 dated Jul. 4, 2013. |
International Search Report and Written Opinion for Application No. PCT/US2012/058229 dated Jul. 3, 2013. |
International Search Report and Written Opinion for Application No. PCT/US2012/057810 dated Jul. 23, 2013. |
International Search Report for Application No. PCT/US2012/057173 dated Aug. 5, 2013. |
International Search Report for Application No. PCT/US2012/057905 dated Aug. 20, 2013. |
International Search Report and Written Opinion for Application No. PCT/US2012/057204 dated Aug. 30, 2013. |
International Search Report and Written Opinion for Application No. PCT/US2013/056773 dated Dec. 4, 2013. |
International Search Report and Written Opinion for Application PCT/US2013/056777 dated Jan. 2, 2014. |
U.S. Appl. No. 13/839,402, filed Mar. 15, 2013. |
U.S. Appl. No. 13/841,052, filed Mar. 15, 2013. |
U.S. Appl. No. 13/840,542, filed Mar. 15, 2013. |
U.S. Appl. No. 13/840,353, filed Mar. 15, 2013. |
U.S. Appl. No. 61/477,877, filed Apr. 21, 2011. |
Office Action from Taiwan for Application No. 101125197 dated May 19, 2014. |
Taiwanese Allowance and Search Report for Application No. 101136592 dated Jun. 27, 2014. |
Taiwanese Office Action for Application No. 101136594 dated Aug. 13, 2014. |
Taiwanese Office Action for Application No. 101136595 dated Oct. 27, 2014. |
International Search Report and Written Opinion for Application No. PCT/US2014/041709 dated Nov. 4, 2014. |
Taiwanese Office Action for Application No. 101136575 dated Oct. 28, 2014. |
International Search Report and Written Opinion for Application No. PCT/US2013/056777 dated Jan. 21, 2015. |
Taiwanese Office Action for Application No. 101136585 dated Jan. 21, 2015. |
Taiwanese Notice of Allowance for Application No. 102130518 dated Mar. 31, 2015. |
Taiwanese Office Action for Application No. 101136606 dated Mar. 27, 2015. |
Taiwanese Office Action for Application No. 101136578 dated May 12, 2015. |
Taiwanese Office Action for Application No. 101136577 dated May 12, 2015. |
Taiwanese Office Action for Application No. 102130519 dated May 7, 2015. |
Written Opinion of the International Preliminary Examining Authority for Application No. PCT/US2014/041709 dated Jun. 1, 2015. |
Taiwanese Office Action for Application No. 101125193 dated Aug. 4, 2015. |
International Search Report and Written Opinion for Application No. PCT/US2015/042726 dated Nov. 12, 2015. |
Chinese Office Action for Application No. 201280044482.X dated Jan. 25, 2016. |
Chinese Office Action for Application No. 201280044481.5 dated Dec. 25, 2015. |
Chinese Office Action for Application No. CN201280043482.8 dated Jan. 19, 2016. |
Kang, et al., 8Gb 3D DDR3 DRAM Using Through-Silicon-Via Technology, IEEE, International Solid-State Circuits Conference, 2009, Samsung Electronics, Hwasung, Korea. |
U.S. Appl. No. 13/306,300, filed Nov. 29, 2011. |
U.S. Appl. No. 13/346,201, filed Jan. 9, 2012. |
U.S. Appl. No. 13/080,876, filed Apr. 6, 2011. |
U.S. Appl. No. 13/306,068, filed Nov. 29, 2011. |
U.S. Appl. No. 13/346,185, filed Jan. 9, 2012. |
U.S. Appl. No. 13/337,565, filed Dec. 27, 2011. |
U.S. Appl. No. 13/440,313, filed Apr. 5, 2012. |
U.S. Appl. No. 13/439,317, filed Apr. 5, 2012. |
U.S. Appl. No. 13/440,212, filed Apr. 5, 2012. |
U.S. Appl. No. 13/439,286, filed Apr. 5, 2012. |
U.S. Appl. No. 13/354,747, filed Jan. 20, 2012. |
U.S. Appl. No. 13/354,772, filed Jan. 20, 2012. |
Kang, et al., 8Gb 3D DDR3 DRAM Using Through-Silicon-Via Technology, IEEE, International Solid-State Circuits Conference, 2009, pp. 130-132. |
U.S. Appl. No. 13/337,575, filed Dec. 27, 2011. |
U.S. Appl. No. 13/440,515, filed Apr. 5, 2012. |
Sandforce, “SF-2200 & SF-2100 Client SSD Processors”, 2011. |
U.S. Appl. No. 13/439,299, filed Apr. 4, 2012. |
U.S. Appl. No. 13/439,354, filed Apr. 4, 2012. |
U.S. Appl. No. 13/439,273, filed Apr. 4, 2012. |
U.S. Appl. No. 13/439,228, filed Apr. 4, 2012. |
U.S. Appl. No. 13/440,299, filed Apr. 5, 2012. |
U.S. Appl. No. 13/440,290, filed Apr. 5, 2012. |
U.S. Appl. No. 13/440,199, filed Apr. 5, 2012. |
U.S. Appl. No. 13/440,280, filed Apr. 5, 2012. |
Elpida User's Manual, “Introduction to GDDR5 SGRAM”, Document No. E1600E10 (Ver. 1.0), Published Mar. 2010, Japan, URL: http:'www.elpida.com. |
Hynix, “2GB (64Mx32) GDDR5 SGRAM HRGQ2H24AFR”, Nov. 2011-Feb. 2012. |
Partial International Search Report dated Oct. 26, 2012 in International Patent Appl. No. PCT/US2012/046049. |
Partial International Search Report dated Oct. 12, 2012 in International Patent Appl. No. PCT/US2012/046249. |
Partial International Search Report dated Oct. 12, 2012 in International Patent Appl. No. PCT/US2012/046255. |
US Non-Final Office Action for U.S. Appl. No. 13/440,199 dated Aug. 31, 2012. |
US Non-Final Office Action for U.S. Appl. No. 13/440,280 dated Aug. 31, 2012. |
US Amendment for U.S. Appl. No. 13/440,280 dated Nov. 30, 2012. |
US Amendment for U.S. Appl. No. 13/440,199 dated Nov. 30, 2012. |
US Non Final Office Action dated Oct. 18, 2012 for U.S. Appl. No. 13/439,299. |
International Search Report and Written Opinion for Application No. PCT/US2012/046049 dated Jan. 10, 2013. |
International Search Report and Written Opinion for Application No. PCT/US2012/046049 dated Nov. 29, 2012. |
US Amendment for U.S. Appl. No. 13/439,299 dated Jan. 18, 2013. |
Partial Search Report for Application No. PCT/US2012/057554 dated Jan. 24, 2013. |
Partial Search Report for Application No. PCT/US2012/058273 dated Jan. 24, 2013. |
Partial Search Report for Application No. PCT/US2012/057170 dated Jan. 31, 2013. |
Partial Search Report for Application No. PCT/US2012/000425 dated Jan. 30, 2013. |
Partial Search Report for Application No. PCT/US2012/058557 dated Feb. 4, 2013. |
International Search Report and Written Opinion for Application No. PCT/US2012/057563 dated Mar. 5, 2013. |
International Search Report and Written Opinion for Application No. PCT/US2012/057554 dated Feb. 28, 2013. |
International Search Report and Written Opinion for Application No. PCT/US2012/057200 dated Mar. 1, 2013. |
International Search Report and Written Opinion for Application No. PCT/US2012/058273 dated Mar. 6, 2013. |
International Search Report and Written Opinion for Application No. PCT/US2012/058557 dated Mar. 12, 2013. |
International Search Report and Written Opinion for Application No. PCT/US2012/046249 dated Mar. 20, 2013. |
International Search Report and Written Opinion for Application No. PCT/US2012/057170 dated Mar. 22, 2013. |
Number | Date | Country | |
---|---|---|---|
20160197058 A1 | Jul 2016 | US |
Number | Date | Country | |
---|---|---|---|
61600527 | Feb 2012 | US | |
61542488 | Oct 2011 | US | |
61542553 | Oct 2011 | US | |
61542495 | Oct 2011 | US |
Number | Date | Country | |
---|---|---|---|
Parent | 14186380 | Feb 2014 | US |
Child | 15069131 | US | |
Parent | 13440280 | Apr 2012 | US |
Child | 14186380 | US |