Multilayer interconnection substrate, semiconductor device, and solder resist

Abstract

A multilayer interconnection substrate includes a resin laminated structure in which plural build-up layers are laminated, each of the plural build-up layers comprising an insulation layer and an interconnection pattern, and first and second solder resist layers provided on a top surface and a bottom surface of the resin laminated structure, wherein each of the first and second solder resist layers includes a glass cloth.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a diagram showing the construction of a semiconductor device that uses a multilayer resin substrate having a core according to a related art of the present invention;

FIG. 2 is a diagram showing the construction of a semiconductor device in which the core part is eliminated in the construction of FIG. 1;

FIG. 3 is a diagram showing the construction of a semiconductor device according to an embodiment of the present invention;

FIGS. 4A-4G are diagrams showing the fabrication process of the semiconductor device of FIG. 3.

Claims

1. A multilayer interconnection substrate, comprising: a resin laminated structure in which plural build-up layers are laminated, each of said plural build-up layers comprising an insulation layer and an interconnection pattern; andfirst and second solder resist layers provided on a top surface and a bottom surface of said resin laminated structure,wherein each of said first and second solder resist layers includes therein a glass cloth.

2. The multilayer interconnection substrate as claimed in claim 1, wherein each of said first and second solder resist layers has an elastic modulus larger than an elastic modulus of said resin laminated structure.

3. The multilayer interconnection structure as claimed in claim 1, wherein each of said first and second solder resist layers has an elastic modules of 10-30 GPa.

4. The multilayer interconnection structure as claimed in claim 1, wherein each of said first and second solder resist layers has a thickness of 30-60 μm.

5. The multilayer interconnection substrate as claimed in claim 1, wherein said multilayer interconnection substrate has a thickness from a surface of said first solder resist layer to a surface of said second solder resist layer of 500 μm or less.

6. The multilayer interconnection substrate as claimed in claim 1, wherein said first and second solder resist layers are formed with respective electrode pads.

7. The multilayer interconnection substrate as claimed in claim 1, wherein said glass cloth comprises a highly opened fabric cloth.

8. A semiconductor device, comprising: a multilayer interconnection substrate; anda semiconductor chip mounted upon said multilayer interconnection substrate in a face-down state,said multilayer interconnection substrate comprising:a resin laminated structure in which plural build-up layers are laminated, each of said plural build-up layers comprising an insulation layer and an interconnection pattern;first and second solder resist layers provided on a top surface and a bottom surface of said resin laminated structure, each of said first and second solder resist layers including therein a glass cloth; andan electrode pad formed to said of said first and second solder resist layers.

9. The semiconductor device as claimed in claim 8, wherein each of said first and second solder resist layers has an elastic modulus larger than an elastic modulus of said resin laminated structure.

10. The semiconductor device as claimed in claim 8, wherein each of said first and second solder resist layers has an elastic modulus of 10-30 GPa.

11. A solder resist, comprising: a layer having a solder resist resin composition; anda glass cloth impregnated in said layer of said solder resist resin composition.

12. The solder resist as claimed in claim 11, wherein said solder resist resin composition comprises any of an epoxy resin, an acrylic ester resin, and epoxy acrylate.