Patent Grant
11791216
Semiconductor devices are used in a variety of electronic applications, such as, for example, personal computers, cell phones, digital cameras, and other electronic equipment. Semiconductor devices are typically fabricated by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor layers of material over a semiconductor substrate, and patterning the various material layers using lithography to form circuit components and elements thereon.
The semiconductor industry continues to improve the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continual reductions in minimum feature size, which allow more components to be integrated into a given area. However, as the minimum features sizes are reduced, additional problems arise that should be addressed.
Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact.
Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.
In accordance with some embodiments, a method of forming a semiconductor device includes: forming, in a first device region of the semiconductor device, first nanostructures (e.g., nanosheets or nanowires) over a first fin, the first fin protruding above a substrate; forming, in a second device region of the semiconductor device, second nanostructures over a second fin, the second fin protruding above the substrate, where the first nanostructures and the second nanostructures comprise a first semiconductor material and extend parallel to a major upper surface of the substrate. The method further includes: forming an interfacial layer (e.g., a gate oxide layer) around the first nanostructures and around the second nanostructures; forming a patterned hard mask layer in the first device region but not in the second device region; and performing an oxidization process to increase a first thickness of the interfacial layer in the second device region. Due to the patterned hard mask layer shielding the first device region from the oxidization process, a second thickness of the interfacial layer in the first device region remains unchanged by the oxidization process, or is increased by a lesser amount than the first thickness of the interfacial layer in the second device region. The disclosed embodiments allow gate oxide layer having different thicknesses to be formed in different device regions (e.g., logic device region and I/O device region) to achieve different performance targets, such as leakage current and power consumption.
In
A multi-layer stack 64 is formed on the substrate 50. The multi-layer stack 64 includes alternating layers of a first semiconductor material 52 and a second semiconductor material 54. In
In some embodiments, the first semiconductor material 52 is an epitaxial material appropriate for forming channel regions of p-type FETs, such as silicon germanium (SixGe1-x, where x is in the range of 0 to 1), and the second semiconductor material 54 is an epitaxial material appropriate for forming channel regions of n-type FETs, such as silicon. The multi-layer stacks 64 (which may also be referred to as an epitaxial material stack) will be patterned to form channel regions of an NSFET in subsequent processing. In particular, the multi-layer stacks 64 will be patterned and etched to form horizontal nanostructures (e.g., nanosheets or nanowires), with the channel regions of the resulting NSFET including multiple horizontal nanostructures.
The multi-layer stacks 64 may be formed by an epitaxial growth process, which may be performed in a growth chamber. During the epitaxial growth process, the growth chamber is cyclically exposed to a first set of precursors for selectively growing the first semiconductor material 52, and then exposed to a second set of precursors for selectively growing the second semiconductor material 54, in some embodiments. The first set of precursors includes precursors for the first semiconductor material (e.g., silicon germanium), and the second set of precursors includes precursors for the second semiconductor material (e.g., silicon). In some embodiments, the first set of precursors includes a silicon precursor (e.g., silane) and a germanium precursor (e.g., a germane), and the second set of precursors includes the silicon precursor but omits the germanium precursor. The epitaxial growth process may thus include continuously enabling a flow of the silicon precursor to the growth chamber, and then cyclically: (1) enabling a flow of the germanium precursor to the growth chamber when growing the first semiconductor material 52; and (2) disabling the flow of the germanium precursor to the growth chamber when growing the second semiconductor material 54. The cyclical exposure may be repeated until a target quantity of layers is formed.
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Note that for simplicity, in some of the subsequent figures, when the processing is the same for both the first device region 200 and the second device region 300, the cross-sectional views (e.g.,
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The fin structures 91 may be patterned by any suitable method. For example, the fin structures 91 may be patterned using one or more photolithography processes, including double-patterning or multi-patterning processes. Generally, double-patterning or multi-patterning processes combine photolithography and self-aligned processes, allowing patterns to be created that have, for example, pitches smaller than what is otherwise obtainable using a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed alongside the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers may then be used to pattern, e.g., the fin structures 91.
In some embodiments, the remaining spacers are used to pattern a mask 94, which is then used to pattern the fin structure 91. The mask 94 may be a single layer mask, or may be a multilayer mask such as a multilayer mask that includes a first mask layer 94A and a second mask layer 94B. The first mask layer 94A and second mask layer 94B may each be formed from a dielectric material such as silicon oxide, silicon nitride, a combination thereof, or the like, and may be deposited or thermally grown according to suitable techniques. The first mask layer 94A and second mask layer 94B are different materials having a high etching selectivity. For example, the first mask layer 94A may be silicon oxide, and the second mask layer 94B may be silicon nitride. The mask 94 may be formed by patterning the first mask layer 94A and the second mask layer 94B using any acceptable etching process. The mask 94 may then be used as an etching mask to etch the substrate 50 and the multi-layer stack 64. The etching may be any acceptable etch process, such as a reactive ion etch (RIE), neutral beam etch (NBE), the like, or a combination thereof. The etching is an anisotropic etching process, in some embodiments. After the etching process, the patterned multi-layer stack 64 forms the layer stack 92, and the patterned substrate 50 forms the fin 90, as illustrated in
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In some embodiments, the insulation material is formed such that excess insulation material covers the fin structures 91. In some embodiments, a liner is first formed along surfaces of the substrate 50 and fin structures 91, and a fill material, such as those discussed above is formed over the liner. In some embodiments, the liner is omitted.
Next, a removal process is applied to the insulation material to remove excess insulation material over the fin structures 91. In some embodiments, a planarization process such as a chemical mechanical polish (CMP), an etch back process, combinations thereof, or the like may be utilized. The planarization process exposes the layer stacks 92 such that top surfaces of the layer stacks 92 and the insulation material are level after the planarization process is complete. Next, the insulation material is recessed to form the STI regions 96. The insulation material is recessed such that the layer stacks 92 protrude from between neighboring STI regions 96. Top portions of the fins 90 may also protrude from between neighboring STI regions 96. Further, the top surfaces of the STI regions 96 may have a flat surface as illustrated, a convex surface, a concave surface (such as dishing), or a combination thereof. The top surfaces of the STI regions 96 may be formed flat, convex, and/or concave by an appropriate etch. The STI regions 96 may be recessed using an acceptable etching process, such as one that is selective to the material of the insulation material (e.g., etches the material of the insulation material at a faster rate than the material of the fins 90 and the layer stack 92). For example, a chemical oxide removal with a suitable etchant such as dilute hydrofluoric (dHF) acid may be used.
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Masks 104 are then formed over the dummy gate layer. The masks 104 may be formed from silicon nitride, silicon oxynitride, combinations thereof, or the like, and may be patterned using acceptable photolithography and etching techniques. In the illustrated embodiment, the mask 104 includes a first mask layer 104A (e.g., a silicon oxide layer) and a second mask layer 104B (e.g., a silicon nitride layer). The pattern of the masks 104 is then transferred to the dummy gate layer by an acceptable etching technique to form the dummy gates 102, and then transferred to the dummy dielectric layer by acceptable etching technique to form dummy gate dielectrics 97. The dummy gates 102 cover respective channel regions of the layer stacks 92. The pattern of the masks 104 may be used to physically separate each of the dummy gates 102 from adjacent dummy gates. The dummy gates 102 may also have a lengthwise direction substantially perpendicular to the lengthwise direction of the fin structures 91. The dummy gate 102 and the dummy gate dielectric 97 are collectively referred to as dummy gate structure, in some embodiments.
Next, a gate spacer layer 108 is formed by conformally depositing an insulating material over the layer stacks 92, STI regions 96, and dummy gates 102. The insulating material may be silicon nitride, silicon carbonitride, a combination thereof, or the like. In some embodiments, the gate spacer layer 108 includes multiple sublayers. For example, a first sublayer (sometimes referred to as a gate seal spacer layer) may be formed by thermal oxidation or a deposition, and a second sublayer (sometimes referred to as a main gate spacer layer) may be conformally deposited on the first sublayer.
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After the formation of the gate spacers 108, implantation for lightly doped source/drain (LDD) regions (not shown) may be performed. Appropriate type (e.g., p-type or n-type) impurities may be implanted into the exposed layer stacks 92 and/or fins 90. The n-type impurities may be any suitable n-type impurities, such as phosphorus, arsenic, antimony, or the like, and the p-type impurities may be any suitable p-type impurities, such as boron, BF2, indium, or the like. The lightly doped source/drain regions may have a concentration of impurities of from about 1015 cm−3 to about 1016 cm−3. An anneal process may be used to activate the implanted impurities.
Next, openings 110 (which may also be referred to as recesses) are formed in the layer stacks 92. The openings 110 may extend through the layer stacks 92 and into the fins 90. The openings 110 may be formed by any acceptable etching technique, using, e.g., the dummy gates 102 as an etching mask.
After the openings 110 are formed, a selective etching process is performed to recess end portions of the first semiconductor material 52 exposed by the openings 110 without substantially attacking the second semiconductor material 54. After the selective etching process, recesses are formed in the first semiconductor material 52, such that sidewalls of the first semiconductor material 52 are recessed from respective sidewalls of the second semiconductor material 54. Therefore, the recesses in the first semiconductor material 52 are also referred to as sidewall recesses.
Next, an inner spacer layer is formed (e.g., conformally) in the opening 110. The inner spacer layer also fills the sidewall recesses in the first semiconductor material 52 formed by the previous selective etching process. The inner spacer layer may be a suitable dielectric material, such as silicon carbon nitride (SiCN), silicon oxycarbonitride (SiOCN), or the like, formed by a suitable deposition method such as PVD, CVD, ALD, or the like. Next, an etching process, such as an anisotropic etching process, is performed to remove portions of the inner spacer layers disposed outside the sidewall recesses in the first semiconductor material 52. The remaining portions of the inner spacer layers (e.g., portions disposed inside the sidewall recesses in the first semiconductor material 52) form the inner spacers 55.
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The epitaxial source/drain regions 112 are epitaxially grown in the openings 110. The epitaxial source/drain regions 112 may include any acceptable material, such as appropriate for n-type or p-type device. For example, when n-type devices are formed, the epitaxial source/drain regions 112 may include materials exerting a tensile strain in the channel regions, such as silicon, SiC, SiCP, SiP, or the like. Likewise, when p-type devices are formed, the epitaxial source/drain regions 112 may include materials exerting a compressive strain in the channel regions, such as SiGe, SiGeB, Ge, GeSn, or the like. The epitaxial source/drain regions 112 may have surfaces raised from respective surfaces of the fins and may have facets.
The epitaxial source/drain regions 112 and/or the fins may be implanted with dopants to form source/drain regions, similar to the process previously discussed for forming lightly-doped source/drain regions, followed by an anneal. The source/drain regions may have an impurity concentration of between about 1019 cm−3 and about 1021 cm−3. The n-type and/or p-type impurities for source/drain regions may be any of the impurities previously discussed. In some embodiments, the epitaxial source/drain regions 112 may be in situ doped during growth.
As a result of the epitaxy processes used to form the epitaxial source/drain regions 112, upper surfaces of the epitaxial source/drain regions 112 have facets which expand laterally outward beyond sidewalls of the fins 90. In the illustrated embodiment, adjacent epitaxial source/drain regions 112 remain separated (see
Next, a contact etch stop layer (CESL) 116 is formed (e.g., conformally) over the source/drain regions 112 and over the dummy gate 102, and a first inter-layer dielectric (ILD) 114 is then deposited over the CESL 116. The CESL 116 is formed of a material having a different etch rate than the first ILD 114, and may be formed of silicon nitride using PECVD, although other dielectric materials such as silicon oxide, silicon oxynitride, combinations thereof, or the like, and alternative techniques of forming the CESL 116, such as low pressure CVD (LPCVD), PVD, or the like, could alternatively be used.
The first ILD 114 may be formed of a dielectric material, and may be deposited by any suitable method, such as CVD, plasma-enhanced CVD (PECVD), or FCVD. Dielectric materials for the first ILD 114 may include silicon oxide, Phospho-Silicate Glass (PSG), Boro-Silicate Glass (BSG), Boron-Doped Phospho-Silicate Glass (BPSG), undoped Silicate Glass (USG), or the like. Other insulation materials formed by any acceptable process may be used.
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Next, the dummy gates 102 are removed in an etching step(s), so that recesses 103 (also referred to as gate trenches) are formed. In some embodiments, the dummy gates 102 are removed by an anisotropic dry etch process. For example, the etching process may include a dry etch process using reaction gas(es) that selectively etch the dummy gates 102 without etching the first ILD 114 or the gate spacers 108. Each recess 103 exposes a channel region of the NSFET. Each channel region is disposed between neighboring pairs of the epitaxial source/drain regions 112. During the removal of the dummy gates 102, the dummy gate dielectric 97 may be used as an etch stop layer when the dummy gates 102 are etched. The dummy gate dielectric 97 may then be removed after the removal of the dummy gates 102. An etching process, such as an isotropic etching process, may be performed to remove the dummy gate dielectric 97. In an embodiment, an isotropic etching process using an etching gas that comprises HF and NH3 is performed to remove the dummy gate dielectric 97.
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In some embodiments, the first semiconductor material 52 is removed by a selective etching process using an etchant that is selective to (e.g., having a higher etch rate for) the first semiconductor material 52, such that the first semiconductor material 52 is removed without substantially attacking the second semiconductor material 54. In some embodiments, an isotropic etching process is performed to remove the first semiconductor material 52. The isotropic etching process is performed using an etching gas, and optionally, a carrier gas, where the etching gas comprises F2 and HF, and the carrier gas may be an inert gas such as Ar, He, N2, combinations thereof, or the like. The isotropic etching process may include a first step to remove the first semiconductor material 52, and a second step after the first step to reshape the profile of the nanostructures 54.
As illustrated in
In some embodiments, the layers of the second semiconductor material 54 in the multi-layer stack 64 (see
As feature sizes continue to shrink in advanced processing nodes, the distance between adjacent nanostructures 54 may become so small that it may be difficult to form layers (e.g., gate dielectric layer) around the nanostructures 54 in subsequent processing. By forming dumbbell-shaped nanostructures 54, the distance between adjacent nanostructures 54 is increased, thus making it easier to form, e.g., gate dielectric layer 122 (see
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In an embodiment, to form the interfacial layer 120, a chemical oxidization through a wet etch process is performed using an oxidizing agent such as SPM (a mixture of H2SO4 and H2O2), SC1 (a mixture of NH4OH and H2O2), or ozone-deionized water (a mixture of O3 and deionized water) to oxidize exterior portions of the nanostructures 54 and the fins 90. In another embodiment, to form the interfacial layer 120, a thermal oxidization is performed by treating (e.g., soaking) the nanostructures 54 and the fins 90 in an oxygen-containing gas source, where the oxygen-containing gas source includes, e.g., N2O, O2, a mixture of N2O and H2, or a mixture of O2 and H2, as examples. The thermal oxidization may be performed at a temperature between about 500° C. and about 1000° C. Note that in the illustrated embodiment, the interfacial layer 120 is formed by converting (e.g., oxidizing) the exterior portions of the nanostructure 54 and the fins 90 into an oxide, and therefore, the interfacial layer 120 is selectively formed on the exposed surfaces of the nanostructures 54 and the fins 90, and is not formed over other surfaces, such as the sidewalls of the inner spacers 55 and the gate spacers 108.
In some embodiments, at the processing stage of
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In the illustrated embodiment of
Next, an oxidization process 129 is performed to increase the thickness of the interfacial layer 120 (e.g., gate oxide layer) around nanostructures 54. Due to the first device region 200 and the second device region 300 having different numbers of hard mask layers (which hard mask layers reduce the effect of the oxidization process on the nanostructures 54/interfacial layer 120), the effect of the oxidization process on the interfacial layer 120 are different in the first device region 200 and the second device region 300, which results in different thicknesses of the interfacial layer 120 in the first device region 200 and the second device region 300. Details are discussed below.
In some embodiments, the oxidization process is a plasma process (also referred to as a plasma oxidization process) performed by treating the NSFET device 100 (e.g., the nanostructures 54) using a plasma of an oxygen-containing gas source. The oxygen-containing gas source may be, e.g., oxygen gas (O2), nitrous oxide gas (N2O), a mixture of nitrous oxide gas (N2O) and nitrogen gas (N2), a mixture of oxygen gas (O2) and nitrogen gas (N2), a mixture of oxygen gas (O2) and an inert gas, or a mixture of nitrous oxide gas (N2O) and an inert gas, where the inert gas may be, e.g., argon (Ar) or helium (He). The oxygen-containing gas source may be ignited into a plasma by, e.g., a capacitively coupled plasma (CCP) system or an inductive coupled plasma (ICP) system, and the nanostructures 54 are then treated by the plasma. In some embodiments, a pressure of the plasma process is between about 1 mTorr to about 10 Torr, and a temperature of the plasma process is between room temperature and about 500° C. A duration of the plasma process is determined (e.g., adjusted) by requirements (e.g., thickness) of the interfacial layer 120, in some embodiments.
In some embodiments, the oxidization process is a thermal process (also referred to as a thermal oxidization process) performed by soaking the NSFET device 100 (e.g., the nanostructures 54) in an oxygen-containing gas source. In an example embodiment, the oxygen-containing gas source is ozone (O3) gas, and the ozone gas is supplied to be in contact with the NSFET device 100 for the thermal oxidization process. In some embodiments, a temperature of the thermal oxidization process is between room temperature and about 500° C. A duration of the plasma process is determined (e.g., adjusted) by requirements (e.g., thickness) of the interfacial layer 120, in some embodiments.
The oxidizing agent (e.g., plasma of the oxygen-containing gas source, or the oxygen-containing gas source) of the oxidization process penetrates or diffuses through the layers (e.g., 128, 124, 122, 120) around the nanostructures 54 in the second device region 300, and converts (e.g., oxidizes) exterior portions of the nanostructures 54 into an oxide of the material of the nanostructures 54, thereby increasing the thickness of the interfacial layer 120 in the second device region 300. Since the exterior portions of the nanostructures 54 in the second device region 300 are converted into an oxide, the height of the nanostructures 54 (e.g., the remaining un-oxidized portions of the semiconductor material of the nanostructure 54) in the second device region 300 is reduced, details of which are discussed below with reference to
Note that the nanostructures 54 in the first device region 200 are shielded (covered) by more (e.g., thicker) hard mask layers (e.g., 126 and 128) than the nanostructures 54 in the second device region 300, and therefore, the oxidizing agent of the oxidization process may not reach the nanostructures 54 in the first device region 200, or may be partially blocked by the hard mask layers. As a result, the thickness of the interfacial layer 120 around the nanostructures 54 in the first device region 200 may remain unchanged before and after the oxidization process, or may increase by a lesser amount than that of the interfacial layer 120 in the second device region 300. For embodiments where the second hard mask layer 128 is omitted, the different effects of the oxidization process on the interfacial layer 120 in the first device region 200 and the second device region 300 are similar to those discussed above, thus not repeated. In subsequent discussion, the interfacial layer 120 in the first device region 200 may also be referred to as interfacial layer 120A, and the interfacial layer 120 in the second device region 300 may also be referred to as interfacial layer 120B.
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In some embodiments, the oxidization process has different effects on the thickness of the interfacial layer 120 (e.g., 120A, 120B) at different vertical levels. In an embodiment, the thickness (e.g., average thickness) of the interfacial layer 120B around the nanostructures 54 (e.g., 54A, 54B, and 54C) in the second device region 300 increases along the vertical direction Z in
In some embodiments, due to the anisotropicity of the oxidization process, the thickness of the interfacial layer 120 (e.g., 120A, 120B) around a nanostructure 54 (e.g., 54C, 54B, or 54A) may vary at different locations. For example, the top portion 120T of the interfacial layer 120B (e.g., a portion along the upper surface of the nanostructure 54) may be thicker than the sidewall portion 120S of the interfacial layer 120B (e.g., a portion along the sidewall of the nanostructure 54), and the sidewall portion 120S may be thicker than the bottom portion 120L of the interfacial layer 120B (e.g., a portion along the lower surface of the nanostructure 54). In some embodiments, the difference between the thicknesses of the top portion 120T, the sidewall portion 120S, and the bottom portion 120L of a same nanostructure 54 in the second device region 300 may be between about 0 angstroms and about 15 angstroms. For this reason, in the discussion herein, when the thicknesses of the interfacial layer 120 around a first nanostructure (e.g., 54C) is said to be thicker than the thickness of the interfacial layer 120 around a second nanostructure (e.g., 54A), it means that the average thickness (e.g., an average of the thicknesses of portions 120T, 120S, and 120L) of the interfacial layer 120 around the first nanostructure is thicker than the average thickness of the interfacial layer 120 around the second nanostructure. In addition, or alternatively, it may mean that a particular portion (e.g., 120T, 120S, or 120L) of the interfacial layer 120 around the first nanostructure is thicker than the same portion (e.g., 120T, 120S, or 120L) of the interfacial layer 120 around the second nanostructure.
In some embodiments, the heights (e.g., T1, T2, T3) of the nanostructures 54 in the second device region 300 may decrease along the vertical direction Z (e.g., T1<T2<T3) in
As discussed above, due to the first device region 200 being shielded by thicker hard mask layer(s) (e.g., 128 and 126) in the oxidization process, the oxidization process has reduced effect on the interfacial layer 120 in the first device region 200, or has no effect on the interfacial layer 120 in the first device region 200 if the hard mask layers (e.g., 128 and 126) completely blocks out the oxidizing agent of the oxidization process. As a result, the interfacial layer 120A at a specific vertical level (e.g., around the nanostructure 54C) in the first device region 200 is thinner than the interfacial layer 120B at the same vertical level (e.g., around the nanostructure 54C) in the second device region 300. Conversely, the height of a nanostructure (e.g., 54C) at a specific vertical level in the first device region 200 is larger than the height of a nanostructure (e.g., 54C) at the same vertical level in the second device region 300. Here the phrase “the same vertical level” is used to describe two nanostructures (e.g., 54C) having a same vertical distance from the substrate but in different device regions (e.g., 200, 300), where the vertical distance is between a horizontal center axis of the nanostructure and a major upper surface of the substrate. In some embodiments, a difference between the heights of nanostructures 54 (e.g., at the same vertical level) in the first device region 200 and the second device region 300 is between about 0 nm and about 6 nm. In some embodiments, a difference between the thicknesses of the interfacial layers 120A and 120B (e.g., at the same vertical level) in the first device region 200 and the second device region 300 is between about 0 angstroms and about 30 angstroms. In some embodiments where the oxidization process has no effect on the interfacial layer 120 in the first device region 200, all the nanostructures 54 in the first device region 200 have a same height T, which is larger than the heights of the nanostructures 54 in the second device region 300 (e.g., T>T3>T2>T1), and the thicknesses of the interfacial layer 120A around all the nanostructures 54 in the first device region 200 have a same value, which is smaller than the smallest thickness of the interfacial layer 120B around all the nanostructures 54 in the second device region 300. In some embodiments, the sheet height gap of nanostructures 54 in the first device region 200 is smaller than the sheet height gap of nanostructures 54 in the second device region 300. The difference between the sheet height gap of nanostructures 54 in the first device region 200 and the sheet height gap of nanostructures 54 in the second device region 300 is between about 0 nm and about 10 nm, in some embodiments.
In some embodiments, the thicknesses of the gate dielectric layer 122 (e.g., along the sidewalls of the gate spacers 108 and along the nanostructures 54) in the first device region 200 and in the second device regions 300 are substantially the same, with the difference between the thicknesses being between about 0 angstroms and about 5 angstroms. In some embodiments, the compositions (e.g., the atomic percentage of nitrogen and oxygen) of the sidewalls of the gate spacers 108 facing the recesses 103 in the first device region 200 and in the second device regions 300 are different, which may be caused by the different amount of oxidizing agent reaching the gate spacers 108 (e.g., due to the different numbers of hard mask layers used) during the oxidization process. For example, the oxidization process may change the composition of the gate spacer 108 from a nitride-rich composition to an oxygen-rich composition. As a result, after the oxidization process, the gate spacer 108 in the first device region 200 may have a higher atomic percentage of nitrogen and a lower atomic percentage of oxygen than the gate spacer 108 in the second device region 300, due to the first device region 200 being shielded by thicker hard mask layer(s) (e.g., 128 and 126) in the oxidization process. In addition, in subsequent etching processes to remove the hard mask layers, the gate spacers 108 in the second device region 300, which has a higher atomic concentration of oxygen, may be damaged (e.g., etched) more easily than the gate spacer 108 in the first device region 200, and therefore, in the final product of the NSFET device 100, a thickness of the gate spacer 108 in the first device region 200 may be larger than a thickness of the gate spacer 108 in the second device region 300.
Besides using different numbers of hard mask layers (e.g., 126, 128) for the first device region 200 and the second device region 300 to achieve different thicknesses for the interfacial layers 120 (e.g., 120A, 120B) (e.g., gate oxide layer), other ways to modulate (e.g., change) the thickness of the interfacial layer 120 are also possible. As an example, the seed layer 124 may be formed to have different thicknesses in the first device region 200 and in the second device region 300. The seed layer 124 may function as another hard mask layer to affect the thickness of the interfacial layer 120. For example, the seed layer 124 may help to control the thickness of the top portion 120T of the interfacial layer 120. The seed layer 124 may also increase thickness uniformity of the interfacial layer 120 at different vertical levels. To achieve different thicknesses of the seed layer 124, a first patterned mask layer (e.g., a patterned photoresist layer) may be used to cover the first device region 200 while the seed layer 124 is formed in the second device region 300 to a first thickness. Next, the first patterned mask layer is removed, and a second patterned mask layer may be formed to cover the second device region 300 while the seed layer 124 is formed in the first device region 200 to a second thickness. Other methods for achieving different thicknesses for the seed layer 124 are possible and are fully intended to be included within the scope of the present disclosure. As another example to achieve different thicknesses for the interfacial layers 120, the parameters of the oxidization process, such as the temperature, the flow rate, or the RF power for the plasma process, may also be adjusted to achieve different thicknesses for the interfacial layers 120A/120B in different device regions (e.g., 200 and 300). By allowing different device regions (e.g., 200, 300) to have different thicknesses for the gate oxide 120, the leakage current and the power consumption of different device regions can be tuned to achieve different performance targets, thus allowing for improved performance and versatility in the design of the NSFET device 100.
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Additional processing may be performed to finish fabrication of the NSFET device 100, as one of ordinary skill readily appreciates, thus details may not be repeated here. For example, a second ILD may be deposited over the first ILD 114. Further, gate contacts and source/drain contacts may be formed through the second ILD and/or the first ILD 114 to electrically couple to the gate electrode 130 and the source/drain regions 112, respectively.
In particular, to form the NSFET device 100A, the processing steps in
Variations of the disclosed embodiments are possible and are fully intended to be included within the scope of the present disclosure. For example, for the NSFET devices 100 and 100A, the second hard mask layer 128 is optional and may be omitted. In addition, the seed layer 124 is optional and may be omitted. As another example, depending on the type of device (e.g., n-type or p-type device) formed, the second semiconductor material 54 may be removed, and the first semiconductor material 52 may remain to form the nanostructures, which nanostructures function as the channel regions of the NSFET device formed. In embodiments where the first semiconductor material 52 remains to form the nanostructures, inner spacers are formed in sidewall recesses of the second semiconductor material 54 before the second semiconductor material 54 is removed, as one of ordinary skill readily appreciates.
Referring to
Embodiments may achieve advantages. The disclosed embodiments allow for different thicknesses for the gate oxide in different device regions of a semiconductor device. This allows devices with different performance targets, such as leakage current and power consumption, to be formed in different devices regions of a same semiconductor device. The disclosed embodiments offers various ways to modulate the gate oxide thickness in different device regions, such as by changing the number of hard mask layers, forming or not forming the seed layers 124, and adjusting the oxidization process conditions. Advantages of forming the seed layer 124 include the ability to adjust the thickness of the gate oxide at upper surfaces of the nanostructures 54, and improved thickness uniformity of the gate oxide at different vertical levels.
In an embodiment, a method of forming a semiconductor device includes: forming, in a first device region of the semiconductor device, first nanostructures over a first fin, the first fin protruding above a substrate; forming, in a second device region of the semiconductor device, second nanostructures over a second fin, the second fin protruding above the substrate, wherein the first nanostructures and the second nanostructures comprise a semiconductor material and extend parallel to a major upper surface of the substrate; forming a dielectric material around the first nanostructures and around the second nanostructures; forming a first hard mask layer in the first device region around the first nanostructures and in the second device region around the second nanostructures; removing the first hard mask layer from the second device region after forming the first hard mask layer; and after removing the first hard mask layer from the second device region, increasing a first thickness of the dielectric material around the second nanostructures by performing an oxidization process. In an embodiment, a second thickness of the dielectric material around the first nanostructures remains unchanged before and after the oxidization process, or is increased less by the oxidization process than the first thickness of the dielectric material around the second nanostructures. In an embodiment, the dielectric material is an oxide of the semiconductor material. In an embodiment, the oxidization process converts exterior portions of the second nanostructures into the dielectric material, wherein the first hard mask layer shields the first nanostructures from the oxidization process. In an embodiment, performing the oxidization process comprises soaking the first nanostructures and the second nanostructures in a gas source comprising ozone. In an embodiment, the oxidization process is a plasma process. In an embodiment, performing the oxidization process comprises: igniting a gas source into a plasma, wherein the gas source comprises oxygen gas, nitrous oxide gas, a mixture of nitrous oxide gas and nitrogen gas, a mixture of oxygen gas and nitrogen gas, a mixture of oxygen gas and an inert gas, or a mixture of nitrous oxide gas and an inert gas; and treating the first nanostructures and the second nanostructures with the plasma. In an embodiment, the method further includes before forming the first hard mask layer, forming a high-k gate dielectric material on the dielectric material. In an embodiment, the method further includes after forming the high-k gate dielectric material and before forming the first hard mask layer, forming a seed layer on the high-k gate dielectric material. In an embodiment, the method further includes, after removing the first hard mask layer from the second device region and before increasing the first thickness of the dielectric material, forming a second hard mask layer in the first device region on the first hard mask layer and in the second device region around the second nanostructures. In an embodiment, the method further includes, after increasing the first thickness of the dielectric material: removing the first hard mask layer from the first device region; and forming a gate electrode around the first nanostructures and around the second nanostructures. In an embodiment, the method further includes, after removing the first hard mask layer from the first device region and before forming the gate electrode, forming a high-k gate dielectric material around the first nanostructures and around the second nanostructures.
In an embodiment, a method of forming a semiconductor device includes: forming first nanostructures over a first fin and forming second nanostructures over a second fin, wherein the first fin and the second fin protrude above a substrate, wherein the first nanostructures and the second nanostructures comprise a first semiconductor material and extend parallel to a major upper surface of the substrate; forming an interfacial dielectric material around the first nanostructures and around the second nanostructures; forming a first hard mask layer over the first fin but not over the second fin, wherein the first hard mask layer covers the interfacial dielectric material around the first nanostructures, wherein the interfacial dielectric material around the second nanostructures is exposed by the first hard mask layer; after forming the first hard mask layer, performing an oxidization process, wherein a thickness of the interfacial dielectric material around the second nanostructures is increased after the oxidization process; and removing the first hard mask layer after performing the oxidization process. In an embodiment, the method further includes, after removing the first hard mask layer, forming a gate electrode around the first nanostructures and around the second nanostructures. In an embodiment, the interfacial dielectric material is an oxide of the first semiconductor material, wherein the oxidization process converts exterior portions of the second nanostructures into the oxide of the first semiconductor material. In an embodiment, performing the oxidization process comprises soaking the first nanostructures and the second nanostructures in an oxygen-containing gas source. In an embodiment, performing the oxidization process comprises treating the first nanostructures and the second nanostructures using a plasma of an oxygen-containing gas source.
In an embodiment, a semiconductor device includes: a first fin and a second fin that protrude above a substrate; first nanostructures and second nanostructures over the first fin and the second fin, respectively, wherein the first nanostructures and the second nanostructures comprise a first semiconductor material and extend parallel to a major upper surface of the substrate; a first interfacial dielectric layer around the first nanostructures and a second interfacial dielectric layer around the second nanostructures, wherein the second interfacial dielectric layer around the second nanostructures is thicker than the first interfacial dielectric layer around the first nanostructures; a gate dielectric layer on the first interfacial dielectric layer around the first nanostructures and on the second interfacial dielectric layer around the second nanostructures; and a gate electrode around the first nanostructures and around the second nanostructures. In an embodiment, the first interfacial dielectric layer and the second interfacial dielectric layer comprise an oxide of the first semiconductor material. In an embodiment, a first nanostructure of the first nanostructures has a first height measured between an upper surface of the first nanostructure distal from the substrate and a lower surface of the first nanostructure facing the substrate, and a second nanostructure of the second nanostructures has a second height measured between an upper surface of the second nanostructure distal from the substrate and a lower surface of the second nanostructure facing the substrate, wherein the first height is larger than the second height, wherein the first nanostructure and the second nanostructure have a same vertical distance from the substrate.
The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.
This application claims the benefit of U.S. Provisional Application No. 63/078,453, filed on Sep. 15, 2020 and entitled “Method of Multiple Gate Oxide Fabrication on Nanosheet Device,” which application is hereby incorporated herein by reference.
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