Patent Grant
11967617
The present application claims priority under 37 U.S.C. § 371 to International Patent Application No. PCT/JP2018/029720, filed Aug. 8, 2018, which claims priority to and the benefit of Japanese Patent Application No. 2017-208139, filed on Oct. 27, 2017. The contents of these applications are hereby incorporated by reference in their entireties.
The present invention relates to a nitride semiconductor substrate, a semiconductor laminate, a substrate selection program, a substrate data output program, a nitride semiconductor substrate provided with a substrate data output program, an off-angle coordinate map, a nitride semiconductor substrate provided with an off-angle coordinate map, a semiconductor device selection program, a nitride semiconductor substrate manufacturing method, a semiconductor laminate manufacturing method, a semiconductor device manufacturing method, and a substrate data output method.
In a nitride semiconductor substrate including a group III nitride semiconductor crystal such as gallium nitride (GaN), an off-angle, which is an angle formed by a main axis of the crystal with respect to a normal of a main surface, may have a predetermined distribution within the main surface, due to a manufacturing method of the substrate (for example, see Patent Document 1).
An object of the present invention is to provide a technique to easily control a surface morphology of a semiconductor layer, which depends on an off-angle in a main surface of a nitride semiconductor substrate.
According to an aspect of the present invention, there is provided
According to the present invention, it is possible to easily control a surface morphology of a semiconductor layer, which depends on an off-angle in a main surface of a nitride semiconductor substrate.
Hereinafter, an embodiment of the present invention will be described with reference to the drawings.
First, a nitride semiconductor substrate 10 (sometimes abbreviated as a “substrate 10” hereafter) according to this embodiment will be described, with reference to
The substrate 10 of this embodiment is constituted, for example, as a base substrate for epitaxially growing a semiconductor layer including a group III nitride semiconductor described later. The substrate 10 is a free-standing substrate including a group III nitride semiconductor crystal (single crystal). In this embodiment, the substrate 10 is, for example, a GaN free-standing substrate.
A diameter of the substrate 10 is, for example, 2 inches or more, and a thickness of the substrate 10 is, for example, 300 μm or more and 4 mm or less. Conductivity of the substrate 10 is not particularly limited. However, in the case of manufacturing a semiconductor device as a vertical Schottky barrier diode (SBD) using the substrate 10, the substrate 10 is, for example, n-type; n-type impurity in the substrate 10 is, for example, silicon (Si) or germanium (Ge); and the n-type impurity concentration in the substrate 10 is, for example, 1.0×1018 cm−3 or more and 1.0×1019 cm−3 or less.
Hereinafter, in a group III nitride semiconductor crystal having a wurtzite structure, <0001> axis (for example, [0001] axis) is referred to as “c-axis”, and (0001) plane is referred to as “c-face”. The (0001) plane is sometimes referred to as “+c-face (group III element polar face)”, and (000-1) plane is sometimes referred to as “−c-face (nitrogen (N) polar face)”. Further, <1-100> axis (for example, [1-100] axis) is referred to as “m-axis”, and (1-100) plane is referred to as “m-face”. Further, <11-20> axis (for example, [11-20] axis) is referred to as “a-axis”, and (11-20) plane is referred to as “a-face”.
The substrate 10 has, for example, a main surface (front surface) 10s which is to be an epitaxial growth surface. In this embodiment, the low index crystal plane nearest to the main surface 10s is, for example, a c-face 10f (+c-face). Surface roughness (arithmetic average roughness Ra) of the main surface 10s of the substrate 10 is, for example, 10 nm or less, preferably 5 nm or less.
Further, the substrate 10 has, for example, an orientation flat 10of (sometimes abbreviated as “Ori-fla 10of” hereinafter) as a flat surface constituting a part of a side surface (numeral not shown) connected to the main surface 10s and a back surface (numeral not shown). In this embodiment, the Ori-fla 10of is, for example, a-face. The Ori-fla 10of may be other than the a-face as long as it is perpendicular to the c-face.
Hereinafter, a direction parallel to the Ori-fla 10of among the directions along the main surface 10s of the substrate 10 is referred to as “x direction”, and the coordinate in the direction parallel to the Ori-fla 10of at a position in the main surface 10s of the substrate 10 is referred to as “x”. Meanwhile, a direction perpendicular to the Ori-fla 10of among the directions along the main surface 10s of the substrate 10 is referred to as “y direction”, and the coordinate in the direction perpendicular to the Ori-fla 10of at a position in the main surface 10s of the substrate 10 is referred to as “y”. The coordinate (x, y) of the center of the main surface 10s of the substrate 10 is (0, 0). In this embodiment, for example, the Ori-fla 10of is the a-face, and therefore the x direction is the direction along m-axis (approximately m-axis direction), and the y direction is the direction along a-axis (approximately a-axis direction).
In this embodiment, the c-face 10f as the low index crystal plane nearest to the main surface 10s of the substrate 10 is, for example, curved in a concave spherical shape with respect to the main surface 10s due to a manufacturing method of the substrate 10 described later. The term “spherical shape” as used herein means a curved surface shape which is approximated to a spherical surface. Further, the phrase “to be approximated to a spherical surface” used herein means to be approximated to a true spherical surface or an elliptical spherical surface within a predetermined error range.
In this embodiment, the c-face 10f of the substrate 10 is, for example, a curved surface shape that is approximated to a spherical surface in each of its cross-sections along m-axis and along a-axis.
In this embodiment, the radius of curvature of the c-face 10f is sufficiently larger than the radius of the substrate 10, for example, in each of cross-sections along m-axis and along a-axis. Specifically, the radius of curvature of the c-face 10f is, for example, 100 times or more the radius of the substrate 10. More specifically, the radius of curvature of the c-face 10f is, for example, 1 μm or more, preferably 4 μm or more, and more preferably 10 μm or more.
In this embodiment, the c-face 10f is curved in a concave spherical shape as described above, and therefore at least some of c-axes 10c is inclined with respect to the normal of the main surface 10s. The “off-angle” which is an angle formed by c-axis 10c with respect to the normal of the main surface 10s has a predetermined distribution within the main surface 10s.
Hereinafter, in the off-angle of c-axis 10c with respect to the normal of the main surface 10s, a directional component along m-axis is referred to as “θm”, and is sometimes abbreviated as “off-angle m-axis component θm”. Further, in the off-angle of c-axis 10c with respect to the normal of the main surface 10s, a directional component along a-axis is referred to as “θa”, and is sometimes abbreviated as “off-angle a-axis component θa”. When c-axis 10c is inclined, m-axis and a-axis are also inclined. Therefore the directional component along m-axis and the directional component along a-axis, can be strictly called in other words as the directional component obtained by orthogonally projecting m-axis onto the main surface 10s and the directional component obtained by orthogonally projecting a-axis on the main surface 10s, respectively. Further, in the following description, the off-angle is represented as (θm, θa) as a vector, and a size of the off-angle (off amount) is represented as “θ”. Incidentally, θ2=θm2+θa2.
As illustrated in
Now, an off-angle m-axis component θm in a cross-section along m-axis of the substrate 10 of this embodiment will be described with reference to
As illustrated in
Since the normal of the main surface 10s passing through the point A is parallel to the normal of the main surface 10s passing through the center of curvature O′ and the point C, the angle AOC is equal to the off-angle m-axis component θm at the point A. Therefore, the distance between A and C can be determined by the following formula using θm:
x+x0=R sin θm.
In this embodiment, as described above, since the radius of curvature R of the c-face 10f is sufficiently larger than the radius r of the substrate 10, the off-angle (off-angle m-axis component θm) of c-axis 10c with respect to the normal of the main surface 10s is sufficiently small. Since the off-angle is sufficiently small, the following approximation can hold: sin θm≈θm. Thereby, the distance between A and C, R sin θm, can be approximated by the distance between A and B on the arc, Rθm.
Therefore, the above formula can be approximated by the following formula:
x+x0=Rθm.
This formula is transformed into a formula for θm as follows:
θm=x/R+x0/R
According to the above formula, at an arbitrary point on the main surface 10s in the cross-section along m-axis of the substrate 10 of this embodiment, the off-angle m-axis component θm can be approximately represented by the linear formula of x. That is, in a cross-section along m-axis of the substrate 10, θm can be considered to vary in a substantially linear manner with respect to x (varying in proportion to x).
In this embodiment, as described above, the c-face 10f of the substrate 10 is a curved surface shape that is approximated to a spherical surface, in a cross-section along a-axis as well. Accordingly, at an arbitrary point on the main surface 10s in the cross-section along a-axis of the substrate 10 of this embodiment, the off-angle a-axis component θa can be approximately represented by the linear formula of y. That is, in a cross-section along a-axis of the substrate 10, θa can be considered to vary in a substantially linear manner with respect to y (varying in proportion to y).
As described above, the off-angle (θm, θa) at an arbitrary position (x, y) in the main surface 10s of the substrate 10 is approximately represented by the following formula using a matrix (matrix equation) (1):
The off-angle (θm, θa) at an arbitrary position (x, y) in the main surface 10s of the substrate 10 is approximately represented by the following formula (1)′:
Hereafter, the description relating to the formula (1) can apply to the formula (1)′.
In each of the formulas (1) and (1)′, M1 and A1 correspond to the reciprocal of the radius of curvature of the c-face 10f in the direction along m-axis and the reciprocal of the radius of curvature of the c-face 10f in the direction along a-axis, respectively, where the unit of M1 and the like is required to be converted from ° to radian.
The off-angle (θm, θa) at an arbitrary position (x, y) in the main surface 10s of the substrate 10 is approximately represented by the aforementioned formula (1), so that the off-angle (θm, θa) at the arbitrary position (x, y) in the main surface of the substrate can be immediately obtained.
The off-angle (θm, θa) at an arbitrary position (x, y) in the main surface 10s of the substrate 10 is approximately represented by the aforementioned formula (1), so that a range (outline) of the main surface 10s of the substrate 10 can be displayed on the off-angle coordinate map (off-angle coordinate map information) 20 which is an orthogonal coordinate system wherein the off-angle m-axis component θm and the off-angle a-axis component θa are coordinate axes.
Now, with reference to
In the off-angle coordinate map 20 illustrated in
In the range of the main surface 10s of the substrate 10 on the off-angle coordinate map 20, the diameter in the θm-axis direction is 2|M1|r and the diameter in the θa-axis direction is 2|A1|r. The range of the main surface 10s of the substrate 10 on the off-angle coordinate map 20 is an ellipse as long as |M1|≠|A1|.
For example, an arbitrary point P other than the center O in the main surface 10s of the actual substrate 10 illustrated in
In this embodiment, as described above, the off-angle (θm, θa) at an arbitrary position (x, y) in the main surface 10s of the substrate 10 is approximately represented by the aforementioned formula (1). That is, the off-angle (θm, θa) varies in a substantially linear manner with respect to (x, y). Thus, the positional relation of the point P relative to the center O of the actual substrate (the substrate in a real space) 10 in
When the Ori-fla 10of is a face other than the a-face, the positional relation of the point P relative to the center O of the main surface 10s of the actual substrate 10 is rotated by γ, which is an angle of Ori-fla 10of relative to the a-face, so that it may be associated with the positional relation of the point P relative to the center O in the range of the main surface 10s of the substrate 10 on the off-angle coordinate map 20.
As described above, in the off-angle coordinate map 20, the range of the main surface 10s of the substrate 10 is displayed, so that the off-angle distribution of the main surface 10s of the substrate 10 can be easily grasped. For example, in the off-angle coordinate map 20, when the range of the main surface 10s of the substrate 10 is large, it can be grasped that the off-angle distribution of the main surface 10s of the substrate 10 is wide. On the other hand, when the range of the main surface 10s of the substrate 10 is small, it can be grasped that the off-angle distribution of the main surface 10s of the substrate 10 is narrow.
Further, in the off-angle coordinate map 20, the range of the main surface 10s of the substrate 10 is displayed, so that it is possible to easily grasp the surface morphology distribution of the semiconductor layer in a range of the main surface 10s of the substrate 10, so as to correspond to the dependence of the surface morphology of the semiconductor layer, grown on the main surface 10s of the substrate 10, on the off-angle of the main surface 10s of the substrate 10.
Here, the dependence of the surface morphology of the semiconductor layer on the off-angle of the main surface 10s of the substrate 10 will be described with reference to
In order to evaluate the dependence of the surface morphology of the semiconductor layer on the off-angle of the main surface of the substrate, a semiconductor laminate (epitaxial wafer) constituting SBD is fabricated. The semiconductor laminate has a laminate structure including a substrate and a semiconductor layer. The substrate is an n-type GaN free-standing substrate having a diameter of 2 inches and a thickness of 400 μm. Further, a base n-type semiconductor layer and a drift layer are sequentially formed as semiconductor layers. The base n-type semiconductor layer is a Si-doped GaN layer, Si concentration in the base n-type semiconductor layer is 2×1018 cm−3, and the thickness of the base n-type semiconductor layer is 2 μm. Further, the drift layer is a Si-doped GaN layer, Si concentration in the drift layer is 0.9×1016 cm−3, and the thickness of the drift layer is 13 μm.
In the off-angle coordinate map of
Further, the off-angle coordinate map of
As a trend of the observation result, stripe-shaped step bunching in the direction along m-axis is observed, on the whole surface of 2.25 square field of view in the portion including the black diamonds. This is remarkably observed when the off-angle (θm, θa) of the just-off substrate is close to (0, 0) as described later. Further, in the portion of the open triangles and the portion of the open squares, in this order, the proportion of the step bunching in the 2.25 mm square field of view is gradually decreased. Further, in the portion of the black circles, it is a flat surface on almost the whole surface of the 2.25 mm square field of view.
As measured by an atomic force microscope (AFM), it is found that the portion of the black diamonds corresponds to a surface roughness (arithmetic average roughness Ra) of 70 nm or more, and the portion of the open triangles corresponds to the surface roughness of 30 nm or more and 70 nm or less, and the portion of the open squares corresponds to a surface roughness of 10 nm or more and 30 nm or less, and the portion of the black circles corresponds to a surface roughness of 10 nm or less. It is also confirmed that the surface morphology distribution result similar to the visual evaluation result obtained by the Nomarski microscope can also be obtained through the surface morphology measurement by measuring a scattered light distribution when the surface of the semiconductor layer is irradiated with laser light.
As illustrated in
Further, as illustrated in
Next, classification of the good surface morphology region will be described with reference to
Region A shows a concentric circle region (donut-shaped region) in which the off-angle size θ is within a predetermined range, including at least a part of the good surface morphology region. Specifically, region A is represented by the following formula, for example:
0.28≤θ≤0.76
that is,
0.0784≤θm2+θa2≤0.578 (2)
Region B represents a region that is away from (0, 0), close to the θm-axis, and entirely included in the good surface morphology region. That is, region B can be considered as a good surface morphology region on the m-off side. Specifically, region B is represented by, for example, the following formulas (3-1) and (3-2):
0.47≤θm≤0.71 (3-1)
−0.20≤θa≤0.26 (3-2)
Region C represents a region that is away from (0, 0), close to the a-axis, and entirely included in the good surface morphology region. That is, region C can be considered as a good surface morphology region on the a-off side. Specifically, region C is represented by, for example, the following formulas (4-1) and (4-2):
−0.05≤θm≤0.21 (4-1)
0.36≤θa≤0.65 (4-2)
Next, with reference to
The main surface 10s of the substrate 10 of this embodiment does not include, for example, a region where the off-angle (θm, θa) is (0,0). When the off-angle (θm, θa) of the main surface 10s of the substrate 10 is close to (0, 0), the surface morphology of the semiconductor layer tends to be rough, as described above. Therefore, since the main surface 10s of the substrate 10 is constituted to avoid this region, roughening of the surface morphology of the semiconductor layer can be suppressed.
The off-angle (θm, θa) at least at a part of the main surface 10s of the substrate 10 of this embodiment is, for example, included in region A and satisfies the above formula (2). Thereby, it is possible to obtain a portion where the surface morphology of the semiconductor layer is good, from at least a part of the semiconductor laminate in which the substrate 10 is used.
Further, the off-angle (θm, θa) at least at the center O of the main surface 10s of the substrate 10 of this embodiment, that is, (M2, A2) is, for example, included in region A and satisfies the above formula (2). Thereby, it is possible to widen a portion in which the off-angle (θm, θa) is included in region A in the main surface 10s of the substrate 10. As a result, it is possible to obtain many portions where the surface morphology of the semiconductor layer is good, from the semiconductor laminate in which the substrate 10 is used.
Further, the proportion of the area of the region where the off-angle (θm, θa) satisfies the formula (2), with respect to a total area of the main surface 10s of the substrate 10 of this embodiment is, for example, more than 50%, preferably 80% or more. Thereby, it is possible to stably obtain a portion where the surface morphology of the semiconductor layer is good, from the semiconductor laminate in which the substrate 10 is used. As a result, it is possible to improve the yield of the semiconductor device.
The off-angle (θm, θa) at least at a part of the main surface 10s of the substrate 10 of this embodiment is for example included in region B and satisfies the above formulas (3-1) and (3-2). Thereby, it is possible to obtain a portion where the surface morphology of the semiconductor layer is good, from at least a part of the semiconductor laminate in which the substrate 10 is used.
Further, the off-angle (θm, θa) at least at the center O of the main surface 10s of the substrate 10 of this embodiment, that is, (M2, A2) is, for example, included in region B and satisfies the above formulas (3-1) and (3-2). Thereby, it is possible to widen a portion where the off-angle (θm, θa) is included in region B in the main surface 10s of the substrate 10. As a result, it is possible to obtain many portions where the surface morphology of the semiconductor layer is good, from the semiconductor laminate in which the substrate 10 is used.
Further, the proportion of the area of the region where the off-angle (θm, θa) satisfies the above formulas (3-1) and (3-2), with respect to the total area of the main surface 10s of the substrate 10 of this embodiment is, for example, more than 50%, preferably 80% or more. Thereby, it is possible to stably obtain a portion where the surface morphology of the semiconductor layer is good, from the semiconductor laminate in which the substrate 10 is used. As a result, it is possible to improve the yield of the semiconductor device.
In the substrate 11 as an ideal first example, for example, the entire range of the main surface 10s is included in region B in the off-angle coordinate map 20. The proportion of the area of the region where the off-angle (θm, θa) satisfies the formulas (3-1) and (3-2), with respect to the total area of the main surface 10s of the substrate 11 is, for example, 100%. Thereby, it is possible to reliably obtain a portion where the surface morphology of the semiconductor layer is good, from the entire semiconductor laminate in which the substrate 10 is used.
Alternatively, the off-angle (θm, θa) at least at a part of the main surface 10s of the substrate 10 of this embodiment is, for example, included in region C and satisfies the above formulas (4-1) and (4-2). Thereby, it is possible to obtain a portion where the surface morphology of the semiconductor layer is good, from at least a part of the semiconductor laminate in which the substrate 10 is used.
Further, the off-angle (θm, θa) at least at the center O of the main surface 10s of the substrate 10 of this embodiment, that is, (M2, A2) is, for example, included in region C and satisfies the above formulas (4-1) and (4-2). Thereby, it is possible to widen a portion where the off-angle (θm, θa) is included in region C in the main surface 10s of the substrate 10. As a result, it is possible to obtain many portions where the surface morphology of the semiconductor layer is good, from the semiconductor laminate in which the substrate 10 is used.
Further, the proportion of the area of the region where the off-angle (θm, θa) satisfies the above formulas (4-1) and (4-2), with respect to the total area of the main surface 10s of the substrate 10 of this embodiment is, for example, more than 50%, preferably 80% or more. Thereby, it is possible to stably obtain a portion where the surface morphology of the semiconductor layer is good, from the semiconductor laminate in which the substrate 10 is used. As a result, it is possible to improve the yield of the semiconductor device.
In the substrate 12 as an ideal second example, for example, the entire range of the main surface 10s is included in region C in the off-angle coordinate map 20. The proportion of the area of the region where the off-angle (θm, θa) satisfies the formulas (4-1) and (4-2), with respect to the total area of the main surface 10s of the substrate 12 is, for example, 100%. Thereby, it is possible to reliably obtain a portion where the surface morphology of the semiconductor layer is good, from the entire semiconductor laminate in which the substrate 10 is used.
Further, in the substrate 10 of this embodiment, an absolute value of a rate of change in the off-angle m-axis component θm, |M1|, is different, for example, from an absolute value of a rate of change in the off-angle a-axis component θa, |A1|. This corresponds to that the radius of curvature of the c-face 10f in the direction along m-axis is different from the radius of curvature of the c-face 10f in the direction along a-axis in the substrate 10. Thereby, the range of the main surface 10s of the substrate 10 can be easily adjusted so as to correspond to a complicated distribution of the good surface morphology region in the off-angle coordinate map 20. As a result, the portion where the surface morphology of the semiconductor layer is good can be widened efficiently in the main surface 10s of the substrate 10.
Furthermore, in the substrate 10 of this embodiment, the absolute value of the rate of change in the off-angle m-axis component θm, |M1|, is smaller than, for example, the absolute value of the rate of change of the off-angle a-axis component θa, |A1|. This corresponds to that the radius of curvature of the c-face 10f in the direction along m-axis is larger than the radius of curvature of the c-face 10f in the direction along a-axis in the substrate 10. Here, in the good surface morphology region of the off-angle coordinate map 20 described above, there are many regions that are short in the θm-axis direction and long in the θa-axis direction. Therefore, in this embodiment, since |M1|<|A1|, the range of the main surface 10s of the substrate 10 can be easily adjusted so as to correspond to the region that is short in the θm-axis direction and long in the θa-axis direction in the good surface morphology region in the off-angle coordinate map 20. As a result, the portion where the surface morphology of the semiconductor layer is good can be widened more efficiently in the main surface 10s of the substrate 10.
Moreover, in this embodiment, an error of the off-angle actually measured with respect to the off-angle obtained by the formula (1), Δθ (hereinafter referred to as “off-angle error”), at arbitrary position in the main surface 10s of the substrate 10 is within ±0.12°, preferably within ±0.06°. When the off-angle error Δθ is more than ±0.12°, the range of the main surface 10s of the substrate 10 based on the off-angle actually measured is wider than the range of the main surface 10s of the substrate 10 obtained by the formula (1) in the off-angle coordinate map 20. Therefore, the off-angle (θm, θa) in at least a part of the main surface 10s of the actual substrate 10 may deviate from the aforementioned region A, B, or C. In contrast, in this embodiment, since the off-angle error Δθ is within ±0.12°, it is possible to suppress the range of the main surface 10s of the substrate 10 based on the off-angle actually measured from being excessively wider than the range of the main surface 10s of the substrate 10 obtained by the formula (1) in the off-angle coordinate map 20. Thereby, it is possible to suppress the off-angle (θm, θa) in at least a part of the main surface 10s of the actual substrate 10 from deviating from the aforementioned region A, B, or C. In addition, in this embodiment, since the off-angle error Δθ is within ±0.06°, it is possible to make the range of the main surface 10s of the substrate 10 based on the off-angle actually measured approximate the range of the main surface 10s of the substrate 10 obtained by the formula (1) in the off-angle coordinate map 20. Thereby, in the main surface 10s of the actual substrate 10, it is possible to stably widen a portion, where the off-angle (θm, θa) is included in the aforementioned region A, B, or C.
Further, in this embodiment, the off-angle error Δθ of the substrate 10 has an off-direction dependence, for example, due to the manufacturing method described later.
Specifically, in this embodiment, for example, when the off-angle m-axis component θm is larger than the off-angle a-axis component θa at the center of the main surface 10s of the substrate 10, a maximum absolute value of an error of the off-angle m-axis component θm actually measured with respect to the off-angle m-axis component θm obtained by the formula (1) (hereinafter referred to as a “θm maximum error”) is smaller than a maximum absolute value of an error of the off-angle a-axis component θa actually measured with respect to the off-angle a-axis component θa obtained by the formula (1) (hereinafter referred to as a “θa maximum error”). Specifically, in the substrate 10 of this embodiment, for example, the θm maximum error is 0.06°, whereas the θa maximum error is 0.12°. Thereby, in the off-angle coordinate map 20, the span of the range of the main surface 10s of the substrate 10 based on the off-angle actually measured, with respect to the range of the main surface 10s of the substrate 10 obtained by the formula (1), can be short in the θm-axis direction. As a result, in the off-angle coordinate map 20, the accuracy of adjustment in the θm-axis direction can be improved, for example, when adjusting the range of the main surface 10s of the substrate 10 based on the off-angle actually measured so as to correspond to region B.
Alternatively, in this embodiment, for example, when the off-angle a-axis component θa is larger than the off-angle m-axis component θm at the center of the main surface 10s of the substrate 10, the θa maximum error is smaller than the θm maximum error. Thereby, in the off-angle coordinate map 20, the span of the range of the main surface 10s of the substrate 10 based on the off-angle actually measured, with respect to the range of the main surface 10s of the substrate 10 obtained by the formula (1), can be short in the θa-axis direction. As a result, in the off-angle coordinate map 20, the accuracy of adjustment in the θa-axis direction can be improved, for example, when adjusting the range of the main surface 10s of the substrate 10 based on the off-angle actually measured so as to correspond to region C.
Next, the substrate selection program, the substrate data output program, the semiconductor device selection program, and the off-angle coordinate map according to this embodiment, and a computer for executing them will be described with reference to
The substrate selection program according to this embodiment is used, for example, on the side of manufacturers of a substrate 10 or a semiconductor laminate, and makes the computer execute selection of the substrate 10 after fabrication of the substrate 10. Specifically, the substrate selection program selects the substrates 10 by ranking, for example, based on the proportion of the area of the region where the off-angle (θm, θa) obtained by the formula (1) satisfies a predetermined condition in the main surface 10s of the aforementioned substrate 10 with respect to the total area of the main surface 10s. In addition, the substrate selection program can determine that each substrate 10 is, for example, excluded from shipment based on a rank given to the substrate 10, or included in shipment corresponding to a price predetermined for each rank of the substrate 10.
The substrate data output program according to this embodiment is used, for example, on the side of users (semiconductor device manufacturers) to whom the substrate 10 or the semiconductor laminate is provided, and makes a computer execute output of data regarding the state of the main surface 10s of the substrate 10. Specifically, for example, when an arbitrary position (x, y) in the main surface 10s of the aforementioned substrate 10 is input, the substrate data output program outputs an off-angle (θm, θa) at the position (x, y) by the formula (1) to a display unit described later. Further, the substrate data output program causes the display unit to display, for example, an off-angle coordinate map 20 wherein the off-angle m-axis component θm and the off-angle a-axis component θa are coordinate axes, and causes a range of the main surface 10s of the substrate 10 to be displayed on the off-angle coordinate map 20 based on the off-angle (θm, θa) at a position (x, y) on an outer edge of the main surface 10s of the substrate 10, output by the formula (1).
Furthermore, a semiconductor device selection program according to this embodiment is used, for example, on the side of users to whom a substrate 10 or the semiconductor laminate is provided, and makes a computer to cause the pick-up apparatus to execute selective pick-up of a semiconductor device, when the semiconductor device is manufactured using the substrate 10. Specifically, the substrate selection program makes the computer cause the pick-up apparatus to execute selective pick-up of the semiconductor device at a predetermined position (x, y) as a good product when the off-angle (θm, θa) obtained at the predetermined position in the main surface 10s of the substrate 10 by the formula (1) satisfies a predetermined condition.
A manufacturing method using the aforementioned various programs will be described in detail later.
As illustrated in
The storage device 73 is constituted as a computer-readable recording medium, and includes, for example, a flash memory, a hard disk drive (HDD), and the like. In the storage device 73, various programs according to this embodiment, the off-angle coordinate map 20, and the like are stored so as to be readable.
The RAM 72 is constituted to temporarily hold various programs, etc., that are read out from the storage device 73 by the CPU 71.
The CPU 71 is constituted to read and execute various programs and the like stored in the storage device 73.
The external storage device 77 is constituted as a portable and computer-readable recording medium, and includes, for example, a magnetic tape, a magnetic disk, an optical disk, an optical magnetic disk, a flash memory, and the like. The aforementioned various programs can be installed in the computer 70 using, for example, the external storage device 77.
The transceiver unit 78 is constituted to transceive information to the outside via the Internet or a dedicated line, for example. The aforementioned various programs may be installed in the computer 70 using, for example, the transceiver unit 78 via the Internet or the dedicated line.
The display unit 75 is constituted to display an off-angle at a predetermined position in the main surface 10s of the substrate 10, an off-angle coordinate map 20, or the like, to the aforementioned manufacturer, user, or the like, and examples thereof include, for example, a liquid crystal display. The input unit 76 is constituted such that the aforementioned manufacturer or user or the like inputs information (e.g., input of a position of the main surface 10s of the substrate 10) to the computer 70, and examples thereof include a mouse and a keyboard. It should be noted that the display unit 75 and the input unit 76 may be constituted to be combined as a touchscreen display. Alternatively, the display unit 75 may be a printer for outputting printed matter.
The I/O port 74 is connected to the pick-up apparatus 80, for example. Thereby, the computer 70 can control the pick-up apparatus 80.
The pick-up apparatus 80 is constituted to pick-up, for example, a semiconductor device cut from the semiconductor laminate.
On the side of the manufacturer of the substrate 10 or the semiconductor laminate, the semiconductor device selection program does not have to be installed in the computer 70 that causes the substrate selection program to be executed. In this case, the computer 70 does not have to be connected to the pick-up apparatus 80 via the I/O port 74.
Meanwhile, on the side of the user to whom the substrate 10 or the semiconductor laminate is provided, the semiconductor device selection program does not have to be installed in the computer 70 that causes the substrate data output program or the substrate selection program to be executed.
The aforementioned substrate 10 of this embodiment is provided together with, for example, a substrate data output program, a semiconductor device selection program, or an off-angle coordinate map 20. A substrate 10 provided along with a substrate data output program, a semiconductor device selection program, or an off-angle coordinate map 20 is referred to as a “substrate provided with a substrate data output program”, a “substrate provided with a semiconductor device selection program” or a “substrate provided with an off-angle coordinate map”, respectively.
The expression “provided with” used herein means to include the cases: (1) where a tray containing the substrate 10 or an enclosed material is accompanied by a program, an information to be entered therein, or the like; and (2) where at least one of a program, an information to be entered therein, and the like is provided so as to be downloadable via the Internet, a dedicated line, or the like. The same applies to the expression “provided with” in the context of an off-angle coordinate map 20 output by the program. Note that, the off-angle coordinate map 20 in this case may be a printed matter.
A semiconductor laminate of this embodiment explained later may also be provided together with, for example, a substrate data output program, a semiconductor device selection program, or an off-angle coordinate map 20. In this case, a semiconductor laminate provided along with a substrate data output program, a semiconductor device selection program, or an off-angle coordinate map 20 is referred to as a “semiconductor laminate provided with a substrate data output program”, a “semiconductor device selection program” or a “semiconductor laminate provided with an off-angle coordinate map”, respectively.
Next, explanation is given for a nitride semiconductor substrate manufacturing method according to this embodiment, a semiconductor laminate manufacturing method according to this embodiment, a semiconductor device manufacturing method according to this embodiment, and a substrate data output method according to this embodiment, with reference to
As illustrated in
A nitride semiconductor substrate fabricating step S100 is performed to fabricate the substrate 10 according to this embodiment. In the nitride semiconductor substrate fabricating step S100 of this embodiment, for example, the substrate 10 is fabricated by a VAS (Void-Assisted Separation) method.
As illustrated in
First, as illustrated in
In this embodiment, the c-face 1f of the substrate 1 is inclined with respect to the main surface 1s. The c-axis 1c of the substrate 1 is inclined at a predetermined off-angle θ0 with respect to the normal of the main surface 1s. The off-angle θ0 in the main surface is of the substrate 1 is uniform over the entire main surface is. The off-angle θ0 in the main surface is of the substrate 1 affects (M2, A2) as the off-angle (θm, θa) at the center O of the main surface 10s of the substrate 10.
Next, as illustrated in
Next, as illustrated in
Next, as illustrated in
In this case, for example, a “void formation rate (volume porosity)” indicative of the proportion in volume of the voids in the void-containing first crystal layer 4 is made concentrically equal in the circumferential direction of a circle or ellipse sharing the center with the substrate 1. The phrase “to be concentrically equal in the circumferential direction of a circle or ellipse sharing the center with the substrate 1” can be restated as “to be equal in the circumferential direction of a circle concentric with the substrate 1 or an ellipse concentric with the substrate 1”. In a specific method, for example, the aforementioned heat treatment is performed while rotating the susceptor on which the substrate 1 is placed. It is also possible to, for example, adjust the degree to which the heater heats in the face of the substrate 1, thereby making the temperature of the substrate 1 in the temperature distribution of the substrate 1 concentrically equal in the circumferential direction of a circle or ellipse sharing the center with the substrate 1. Thereby, voids can be equally formed in the circumferential direction in the void-containing first crystal layer 4. As a result, the void formation rate of the void-containing first crystal layer 4 can be made concentrically equal in the circumferential direction of a circle or ellipse sharing the center with the substrate 1.
At this time, for example, the void formation rate of the void-containing first crystal layer 4 is monotonically (e.g., linearly) increased from the center side toward the outer circumference side in a radial direction of the substrate 1. Specifically, for example, in the temperature distribution of the substrate 1, the temperature of the substrate 1 is monotonically increased from the center side toward the outer circumference side in the radial direction of the substrate 1. Examples of a method to obtain the temperature distribution of the substrate 1 include: a method of adjusting the degree to which the heater heats in the face of the substrate 1 to obtain the aforementioned temperature distribution; a method of bringing only the outer circumference side of the substrate 1 into contact with the susceptor by utilizing convex warpage generated on the front surface side of the substrate 1 due to the linear expansion coefficient difference between the substrate 1 and the first crystal layer 2 when the first crystal layer 2 is formed, to obtain the aforementioned temperature distribution; a method of making the placement surface of the susceptor concavely curved so that only the outer circumference side of the substrate 1 is brought into contact with the susceptor, to obtain the aforementioned temperature distribution; and the like. As described above, since the temperature of the substrate 1 is monotonically increased from the center side to the outer circumference side in the radial direction of the substrate 1, the void formation rate of the void-containing first crystal layer 4 can be monotonically increased from the center side to the outer circumference side in the radial direction of the substrate 1.
At this time, for example, the void formation rate of the void-containing first crystal layer 4 is 10% or more and 90% or less from the center side toward the outer circumference side in a radial direction of the substrate 1. With the void formation rate of 10% or more, the second crystal layer 6 can be stably peeled in the peeling step S160 described later. On the other hand, with the void formation rate of 90% or less, the peeling can be suppressed from occurring during growth of the second crystal layer 6 in the second crystal layer forming step S150 described later.
Next, for example, Si-doped GaN layer as a second crystal layer (full-growth layer) 6 is epitaxially grown on the void-containing first crystal layer 4 and the metal nitride layer 5, by supplying gallium chloride (GaCl) gas, NH3 gas and dichlorosilane (SiH2Cl2) gas as n-type dopant gas, to the substrate 1 heated to a predetermined growth temperature, by a hydride vapor phase epitaxy (HVPE) method. A Ge-doped GaN layer may also be epitaxially grown as the second crystal layer 6 by supplying tetrachlorogermane (GeCl4) gas or the like as the n-type dopant gas, instead of the SiH2Cl2 gas.
At this time, the second crystal layer 6 grows on the void-containing first crystal layer 4 and the metal nitride layer 5, from the void-containing first crystal layer 4 through the holes of the metal nitride layer 5. Although a part of the voids in the void-containing first crystal layer 4 is buried by the second crystal layer 6, the other part of the voids in the void-containing first crystal layer 4 is remained. A flat air gap is formed between the second crystal layer 6 and the metal nitride layer 5, due to the voids remaining in the void-containing first crystal layer 4. A flat air gap (size and density thereof) formed between the second crystal layer 6 and the metal nitride layer 5 depends on the void formation rate in the aforementioned void-containing first crystal layer 4. This air gap causes peeling of the second crystal layer 6 in a peeling step S160 described later.
At this time, an “initial nucleus” which is a crystal nucleus in an early stage of growth of the second crystal layer 6 is generated corresponding to the void formation rate of the void-containing first crystal layer 4. The higher the void formation rate of the void-containing first crystal layer 4, the lower the density of the initial nucleus in the second crystal layer 6. The density of the initial nucleus in the second crystal layer 6 affects, for example, tensile stress generated in the second crystal layer 6, and a difference in dislocation density in the thickness direction of the second crystal layer 6.
The tensile stress generated in the second crystal layer 6 has the following tendency. In the growth process of the second crystal layer 6, when the island-shaped initial nucleus grows laterally and gets closer to the adjacent initial nuclei, it is energetically stable for two surfaces of initial nuclei to be united rather than to exist separately. Therefore, the adjacent initial nuclei are forcibly attracted (associated) with each other. Since the initial nuclei are bound to the substrate 1 side, tensile stress is introduced between adjacent initial nuclei. This is described in W. D. Nix and B. M. Clemens, J. Mater. Res., 14 (1999) 3467. The lower the density of the initial nuclei in the second crystal layer 6, the larger the island-shaped initial nuclei grow until being associated. The larger the size of the island-shaped initial nucleus just before being associated, the lower the density of the associated portion of the adjacent initial nuclei and the lower the tensile stresses between the adjacent initial nuclei.
The difference in dislocation density in the thickness direction of the second crystal layer 6 has the following tendency. In the growth process of the second crystal layer 6, when the density of the initial nucleus in the second crystal layer 6 is low, the island-shaped initial nuclei grow larger until being associated so that the lateral growth of the initial nuclei is promoted, as described above. Thereby, as the second crystal layer 6 grows, the dislocation in the second crystal layer 6 is reduced rapidly. As the result, the lower the density of the initial nucleus in the second crystal layer 6, the smaller the difference in dislocation density in the thickness direction of the second crystal layer 6.
In this embodiment, according to the distribution of the void formation rate of the void-containing first crystal layer 4, the density of the initial nucleus in the second crystal layer 6 is made concentrically equal in the circumferential direction of a circle or ellipse sharing the center with the substrate 1, and, at the same time, the density of the initial nucleus is monotonically (e.g., linearly) decreased from the center side toward the outer circumference side in a radial direction of the substrate 1. Thereby, the tensile stress generated in the second crystal layer 6 is made concentrically equal in the circumferential direction of a circle or ellipse sharing the center with the substrate 1, and, at the same time, the tensile stress is monotonically decreased from the center side toward the outer circumference side in a radial direction of the substrate 1. Further, the difference in dislocation density in the thickness direction of the second crystal layer 6 can be made concentrically equal in the circumferential direction of a circle or ellipse sharing the center with the substrate 1, and, at the same time, the difference in dislocation density in the thickness direction can be monotonically decreased from the center side toward the outer circumference side in a radial direction of the substrate 1.
Further, at this time, the second crystal layer 6 is grown incorporating an orientation of the substrate 1. That is, the off-angle θ1 in the main surface of the second crystal layer 6 is uniform over the entire main surface, like the off-angle θ0 in the main surface is of the substrate 1.
Further, at this time, after the second crystal layer 6 is flattened, the flat second crystal layer 6 is grown with only the c-face as a growth surface, without causing facets other than the c-face to generate on the main surface of the second crystal layer 6 (without three-dimensional growth).
Further, at this time, the thickness of the second crystal layer 6 is, for example, 600 μm or more, preferably 1 mm or more. An upper limit value of the thickness of the second crystal layer is not particularly limited. However, it is preferable that the thickness of the second crystal layer 6 be 50 mm or less, from a viewpoint of productivity improvement.
After completion of the growth of the second crystal layer 6, the second crystal layer 6 spontaneously peels from the substrate 1, with the void-containing first crystal layer 4 and the metal nitride layer 5 serving as boundaries, in the process of cooling the HVPE apparatus used for growing the second crystal layer 6.
At this time, tensile stress is introduced into the second crystal layer 6, as described above. Therefore, internal stress acts on the second crystal layer 6 such that the front surface side of the second crystal layer 6 is concave due to the tensile stress generated in the second crystal layer 6. Further, the dislocation density on the main surface (front surface) side of the second crystal layer 6 is low, whereas the dislocation density on the back surface side of the second crystal layer 6 is high. Therefore, the internal stress acts on the second crystal layer 6 such that the front surface side of the second crystal layer 6 is concave also due to a difference in dislocation density in the thickness direction of the second crystal layer 6.
As a result, as illustrated in
At this time, in the aforementioned second crystal layer forming step S150, the tensile stress generated in the second crystal layer 6 is made concentrically equal in the circumferential direction of a circle or ellipse sharing the center with the substrate 1, and, at the same time, the tensile stress is monotonically decreased from the center side toward the outer circumference side in a radial direction of the substrate 1, according to the distribution of the density of the initial nucleus in the second crystal layer 6. Further, the difference in dislocation density in the thickness direction of the second crystal layer 6 is made concentrically equal in the circumferential direction of a circle or ellipse sharing the center with the substrate 1, and, at the same time, the difference in dislocation density in the thickness direction is monotonically decreased from the center side toward the outer circumference side in a radial direction of the substrate 1. Thereby, the internal stress warping the second crystal layer 6 so as to be concave can be made concentrically equal in the circumferential direction of a circle or ellipse sharing the center with the substrate 1, and, at the same time, the internal stress warping the second crystal layer 6 so as to be concave can be monotonically decreased from the center side toward the outer circumference side in a radial direction of the substrate 1.
As described above, since the internal stress warping the second crystal layer 6 so as to be concave is generated, the second crystal layer 6 can be warped symmetrically around the normal of the center of the main surface 6s, for example, in each of the cross-section along m-axis and the cross-section along a-axis. Thereby, the c-face 6f of the second crystal layer 6 can be a curved surface shape that is approximated to a spherical surface in each of its cross-sections along m-axis and along a-axis. As a result, in the finally obtained substrate 10, the off-angle (θm, θa) at an arbitrary position (x, y) in the main surface 10s can be approximately represented by the aforementioned formula (1).
Moreover, at this time, since the void formation rate of the void-containing first crystal layer 4 is made concentrically equal in the circumferential direction of a circle or ellipse sharing the center with the substrate 1 in the aforementioned void forming step S140, the second crystal layer 6 can be peeled equally from the outer circumference in the circumferential direction of the substrate 1.
Moreover, at this time, since the void formation rate of the void-containing first crystal layer 4 is monotonically increased from the center side toward the outer circumference side in a radial direction of the substrate 1 in the aforementioned void forming step S140, the second crystal layer 6 can be gradually peeled from the outer circumference side toward the center side in the circumferential direction of the substrate 1. When the second crystal layer 6 is gradually peeled from the outer circumference side in the radial direction of the substrate 1, N of GaN included in the void-containing first crystal layer 4 is eliminated from where the second crystal layer 6 is peeled, while metal θa remains. Further, the second crystal layer 6 is gradually peeled toward the center side in the radial direction of the substrate 1, so that the central position of the final contact range which remains as (a liquid film of) metal θa between the second crystal layer 6 and the substrate 1 can be an approximate center of the substrate 1. Specifically, for example, the diameter of the final contact range between the second crystal layer 6 and the substrate 1 can be 10 mm or more and 20 mm or less. Moreover, for example, the central position of the final contact range between the second crystal layer 6 and the substrate 1 can be within 5 mm, preferably within 1 mm from the center of the substrate 1.
As described above, since the second crystal layer 6 is peeled from the substrate 1, the second crystal layer 6 can be warped symmetrically around the normal of the center of the main surface 6s, for example, in each of the cross-section along m-axis and the cross-section along a-axis.
Further, at this time, since the second crystal layer 6 is grown with only the c-face as a growth surface in the aforementioned second crystal layer forming step S150, the stress toward the center of the radial direction in the second crystal layer 6 can be approximately equal in the circumferential direction when the second crystal layer 6 is peeled from the substrate 1. Since the stress in the second crystal layer 6 is equal, the second crystal layer 6 can be warped symmetrically around the normal of the center of the main surface 6s, for example, in each of the cross-section along m-axis and the cross-section along a-axis.
Further, at this time, the warpage of the second crystal layer 6 may have direction dependence in some cases. For example, when the void formation rate of the void-containing first crystal layer 4 is made concentrically equal in the circumferential direction of a ellipse sharing the center with the substrate 1, the direction dependence can be caused in the density of the initial nucleus in the second crystal layer 6. Thereby, it is possible to cause direction dependence in the tensile stress generated in the second crystal layer 6 and in the difference in dislocation density in the thickness direction of the second crystal layer 6. As a result, the warpage in the direction along m-axis of the second crystal layer 6 can be different from the warpage in the direction along a-axis of the second crystal layer 6.
Since the direction dependence in the warpage of the second crystal layer 6 is utilized, the radius of curvature of the c-face 6f in the direction along m-axis can be different from the radius of curvature of the c-face 6f in the direction along a-axis, in the second crystal layer 6. As a result, in the finally obtained substrate 10, an absolute value of a rate of change in the off-angle m-axis component θm, |M1|, can be different from an absolute value of a rate of change in the off-angle a-axis component θa, |A1|.
Furthermore, since the direction dependence in the warpage of the second crystal layer 6 is utilized, for example, the radius of curvature of the c-face 6f in the direction along m-axis can be larger than the radius of curvature of the c-face 6f in the direction along a-axis, in the second crystal layer 6. As a result, in the finally obtained substrate 10, the absolute value of a rate of change in the off-angle m-axis component θm, |M1|, can be smaller than an absolute value of a rate of change in the off-angle a-axis component θa, |A1|.
Moreover, at this time, since the thickness of the second crystal layer 6 is 1 mm or more in the aforementioned second crystal layer forming step S150, the warpage of the second crystal layer 6 can be reduced. Thereby, the radius of curvature of the c-face 6f in the second crystal layer 6 can be suppressed from becoming excessively small, and thus the deviation of the c-face 6f in the second crystal layer 6 from the curved surface ideally approximated to a spherical surface can be reduced. As a result, at an arbitrary position on the main surface 10s of the finally obtained substrate 10, an error of the off-angle actually measured with respect to the off-angle obtained by the formula (1), Δθ, can be within ±0.12°, preferably within 0.060.
Next, as illustrated in
In this situation, even when the wire saw is guided to a cut surface SS perpendicular to the normal direction of the center of the main surface 6s of the second crystal layer 6, the wire saw may be actually deflected in some cases. Therefore, the actual cut surface SS may be, for example, concavely curved only in a predetermined direction with respect to the ideally perpendicular surface with respect to the normal of the center of the main surface 6s of the second crystal layer 6.
Accordingly, in this embodiment, the direction dependence of the aforementioned wire saw is actively utilized. For example, the direction, in which the actual cut surface SS is concavely curved with respect to ideally perpendicular surface with respect to the normal of the center of the main surface 6s of the second crystal layer 6, is oriented to a direction along m-axis or a direction along a-axis in the second crystal layer 6. Thereby, in the substrate 7, the radius of curvature of the c-face 7f in the direction along m-axis can be different from the radius of curvature of the c-face 7f in the direction along a-axis. As a result, in the finally obtained substrate 10, an absolute value of a rate of change in the off-angle m-axis component θm, |M1|, can be different from an absolute value of a rate of change in the off-angle a-axis component θa, |A1|.
In this embodiment, for example, since the direction in which the actual cut surface SS is concavely curved is the direction along m-axis of the second crystal layer 6, the degree of curvature of the c-face 7f in the direction along m-axis can be reduced, in the substrate 7. That is, the radius of curvature of the c-face 7f in the direction along m-axis can be larger than the radius of curvature of the c-face 7f in the direction along a-axis, in the substrate 7. As a result, in the finally obtained substrate 10, the absolute value of a rate of change in the off-angle m-axis component θm, |M1|, can be smaller than an absolute value of a rate of change in the off-angle a-axis component θa, |A1|.
According to this step, as illustrated in
Next, both surfaces of the substrate 7 are polished by the polishing apparatus.
At this time, in this embodiment, for example, both surfaces of the substrate 7 are polished so that the radius of curvature of the c-face 7f in the surface 7 becomes larger. Further, in this embodiment, for example, both surfaces of the substrate 7 are polished so that the radius of curvature of the c-face 7f in the direction along m-axis is different from the radius of curvature of the c-face 7f in the direction along a-axis, in the substrate 7.
Specifically, as illustrated in
At this time, the attachment surface of the holder 82 is, for example, curved in a concave spherical shape. Since the main surface 7s side of the substrate 7 is attached to the attachment surface of the holder 82, the substrate 7 is warped so that the main surface 7s side of the substrate is curved in a convex spherical shape. Thereby, the radius of curvature of the c-face 7f of the substrate 7 can be larger than that in the state after the slicing step S170.
At this time, the attachment surface of the holder 82 is, for example, in an elliptical spherical surface. In the attachment surface of the holder 82, the axial direction in which a radius of curvature is small, for example, is oriented to the direction along m-axis or along a-axis of the substrate 7. Thereby, the substrate 7 can be warped so that the main surface 7f side thereof is curved in a convex elliptical spherical shape. As a result, in the substrate 7, the radius of curvature of the c-face 7f in the direction along m-axis can be different from the radius of curvature of the c-face 7f in the direction along a-axis.
In this embodiment, in the attachment surface of the holder 82, the axial direction in which a radius of curvature is small, for example, is oriented to the direction along m-axis of the substrate 7. Thereby, in the substrate 7, the radius of curvature of the c-face 7f in the direction along m-axis can be larger than the radius of curvature of the c-face 7f in the direction along a-axis.
After the substrate 7 is attached to the holder 82, each of the holder 82 holding the substrate 7 and the surface plate 84 having a polishing pad 86 is rotated, and the back surface 7b side of the substrate 7 is pressed against the polishing pad 86 while supplying a slurry. Thereby, the concave back surface 7b of the substrate 7 is polished to be a flat surface perpendicular to the normal of the center of the main surface 7f of the substrate 7.
After the back surface 7b of the substrate 7 is polished, the back surface 7b side of the substrate 7 is attached to the holder 82 with a wax, as illustrated in
After the substrate 7 is attached to the holder 82, each of the holder 82 holding the substrate 7 and the surface plate 84 having a polishing pad 86 is rotated, and the main surface 7s side of the substrate 7 is pressed against the polishing pad 86 while supplying a slurry. Thereby, the convex main surface 7s of the substrate 7 is polished (mirror polished) to be a flat surface perpendicular to the normal of the center of the main surface 7f of the substrate 7.
Since the substrate 7 is polished in this way, the substrate 10 is obtained as illustrated in
At this time, in the polishing step S180, since the substrate 7 is polished in the state where the radius of curvature of the c-face 7f of the substrate 7 is larger than that in the state after the slicing step S170, the radius of curvature of the c-face 10f in the finally obtained substrate 10 can be a desired size. That is, the rate of change in the off-angle m-axis component θm, M1, and the rate of change in the off-angle a-axis component θa, A1, can be adjusted.
In the polishing step S180, since the substrate 7 is polished in the state where the radius of curvature of the c-face 7f in the direction along m-axis in the substrate 7 is different from the radius of curvature of the c-face 7f in the direction along a-axis, the radius of curvature of the c-face 10f in the direction along m-axis can be different from the radius of curvature of the c-face 10f in the direction along a-axis in the finally obtained substrate 10 as well. Thereby, in the substrate 10, an absolute value of a rate of change in the off-angle m-axis component θm, |M1|, can be different from an absolute value of a rate of change in the off-angle a-axis component θa, |A1|.
In the polishing step S180, since the substrate 7 is polished in the state where the radius of curvature of the c-face 7f in the direction along m-axis in the substrate 7 is larger than the radius of curvature of the c-face 7f in the direction along a-axis, the radius of curvature of the c-face 10f in the direction along m-axis can be larger than the radius of curvature of the c-face 10f in the direction along a-axis in the finally obtained substrate 10. Thereby, in the substrate 10, the absolute value of a rate of change in the off-angle m-axis component θm, |M1|, can be smaller than the absolute value of a rate of change in the off-angle a-axis component θa, |A1|.
Through the nitride semiconductor substrate fabricating step S100 described above, the substrate 10 can be fabricated so that the off-angle (θm, θa) at a position (x, y) in the main surface 10s is approximated by the formula (1).
After fabricating the substrate 10, the off-angle (θm, θa) is measured at two or more points on the main surface 10s of the substrate 10 by a rocking curve measurement of X-ray diffraction. At this time, when the off-angle (θm, θa) is measured at only two points, it is preferable that the x coordinate and the y coordinate at the two points are different. It is preferable to measure the off-angle (θm, θa) at five or more points on the main surface 10s of the substrate 10, from a viewpoint of more accurate measurement. At this time, five or more measuring points preferably include, for example, center O, two points across the center O in the direction along m-axis, and two points across the center O in the direction along a-axis.
After the off-angle (θm, θa) is measured at two or more points on the main surface 10s of the substrate 10, the constants M1, A1, M2, and A2 in the formula (1) are obtained. When the off-angle (θm, θa) is measured at three or more points in each of the x direction and the y direction, the constants M1, A1, M2, and A2 are obtained by the least-square method.
After the constants M1, A1, M2, and A2 are obtained, a substrate data output program and a semiconductor device selection program are prepared based on the formula (1) including the constants M1, A1, M2, and A2.
After the constants M1, A1, M2, and A2 of the formula (1) are obtained, the manufacturer who have manufactured the substrates 10, for example, makes the computer 70 execute the substrate selection program, and ranks the substrate 10 based on the proportion of the area of the region where the off-angle (θm, θa) obtained by the formula (1) satisfies a predetermined condition in the main surface 10s of the substrate 10 with respect to the total area of the main surface 10s, to select the substrate.
Specifically, when the proportion of the area of the region where the off-angle (θm, θa) satisfies the above formula (2) with respect to the total area of the main surface 10s of the substrate 10 is a predetermined value or more, the substrate 10 is ranked as a good product.
Alternatively, when the proportion of the area of the region where the off-angle (θm, θa) satisfies the above formulas (3-1) and (3-2) with respect to the total area of the main surface 10s of the substrate 10 is a predetermined value or more, the substrate 10 is ranked as a good product.
Alternatively, when the proportion of the area of the region where the off-angle (θm, θa) satisfies the above formulas (4-1) and (4-2) with respect to the total area of the main surface 10s of the substrate 10 is a predetermined value or more, the substrate 10 is ranked as a good product.
In this case, the product with higher proportion of the area is higher ranked. For example, when the proportion of the area is 50% or more and less than 80%, the product is ranked as a good product, and when the proportion of the area is 80% or more and 100% or less, the product is ranked as a best product. Further, when the proportion of the area is, for example, 10% or less, the substrate 10 is ranked as a defective product and prohibited from being shipped. A relation between the proportion of the area and the rank can be appropriately set.
After ranking the substrate 10, information regarding the rank of the substrate 10 is recorded in the external storage device 77 as a predetermined recording medium. The information regarding the rank of the substrate 10 may be provided so as to be downloadable via the Internet, a dedicated line, or the like, or may be output as a printed matter.
Further, after ranking the substrate 10, the substrate 10 is set as a shipping target in correspondence with a price for the substrate 10 for each predetermined rank, in a case when the substrate 10 is not a defective product. At this time, as the rank of the substrate 10 is higher, a higher price is set, but the price can be appropriately set.
After setting the price of the substrate 10, the information regarding the price of the substrate 10 may be, for example, recorded in the external storage device 77 together with an information regarding the rank of the substrate 10.
Next, a semiconductor layer 50 including a group III nitride semiconductor is epitaxially grown on the substrate 10, and a semiconductor laminate 30 is fabricated. In this embodiment, for example, a laminate constituting SBD is fabricated as the semiconductor laminate 30.
Specifically, as illustrated in
After forming the base n-type semiconductor layer 51, an n-type GaN layer as the drift layer 52 is formed on the base n-type semiconductor layer 51. At this time, the n-type impurity in the drift layer 52 is, for example, Si or Ge. Further, the concentration of the n-type impurity in the drift layer 52 is lower than the concentration of the n-type impurity in the substrate 10 and the concentration of the n-type impurity in the base n-type semiconductor layer 51, and it is 1.0×1015 cm−3 or more and 5.0×1016 cm−3 or less. Further, the thickness of the drift layer 52 is thicker than the thickness of the base n-type semiconductor layer 51, and it is 3 μm or more and 40 μm or less. Thus, ON resistance of the semiconductor device 40 described later can be reduced, and a withstand voltage of the semiconductor device 40 can be secured.
As described above, the semiconductor laminate 30 according to this embodiment is fabricated.
In the semiconductor laminate 30 according to this embodiment, for example, when the proportion of the area of the region where the off-angle (θm, θa) satisfies the formulas (3-1) and (3-2) with respect to the total main surface of the substrate 10, is more than 50% and preferably 80% or more, the proportion of the area of the region where an arithmetic average roughness Ra of the main surface of the semiconductor layer 50 is 30 nm or less and preferably 10 nm or less with respect to the total area of the main surface of the semiconductor layer 50, is more than 50% and preferably 80% or more.
Alternatively, in the semiconductor laminate 30 according to this embodiment, for example, when the proportion of the area of the region where the off-angle (θm, θa) satisfies the formulas (4-1) and (4-2), with respect to the total main surface of the substrate 10, is more than 50% and preferably 80% or more, the proportion of the area of the region where an arithmetic average roughness Ra of the main surface of the semiconductor layer 50 is 30 nm or less and preferably 10 nm or less, with respect to the total area of the main surface of the semiconductor layer 50, is more than 50% and preferably 80% or more.
The semiconductor laminate 30 of this embodiment is, for example, sold to a user at a price based on the price set to the substrate 10 in the aforementioned substrate selecting step S240. At this time, the semiconductor laminate 30 is provided to the user side together with the information regarding the rank of the aforementioned substrate 10 and the like.
The aforementioned substrate 30 of this embodiment is provided to the user side together with, for example, the aforementioned substrate data output program or semiconductor device selection program. The semiconductor laminate 30 of this embodiment may be provided to the user side together with, for example, the aforementioned off-angle coordinate map 20.
Next, for example, on the side of user side to whom the semiconductor laminate 30 has been provided, the semiconductor device 40 is fabricated using the semiconductor laminate 30.
Specifically, as illustrated in
Further, an n-type electrode 66 is formed on the back surface side of the substrate 10. At this time, the n-type electrode 66 is, for example, a Ti/aluminum (Al) film.
After forming the p-type electrode 61 and the n-type electrode 66, infrared rays are irradiated to the semiconductor laminate 30 in an inert gas atmosphere to anneal the semiconductor laminate 30. Thereby, the adhesiveness of each of the p-type electrode 61 and the n-type electrode 66 is improved, and a contact resistance of each of the p-type electrode 61 and the n-type electrode 66 is reduced.
After annealing the semiconductor laminate 30, the semiconductor laminate 30 is diced and cut into chips of a predetermined size.
As described above, as illustrated in
After fabricating the semiconductor device 40, a semiconductor device selecting step S500 is performed, which is the step of selecting the semiconductor device 40 based on the off-angle (θm, θa) at a position (x, y) in the main surface 10s of the substrate 10. The semiconductor device selecting step S500 of this embodiment includes, for example, an off-angle outputting step S520, a map displaying step S540, and a good product determining step S560.
Specifically, the user who has fabricated the semiconductor device 40 using the semiconductor laminate 30, for example, makes the computer 70 execute the substrate data output program so that, when an arbitrary position (x, y) in the main surface 10s of the aforementioned substrate 10 is input, the off-angle (θm, θa) at the position (x, y) is output to a display unit 75 by the formula (1). Specifically, for example, a position (x, y) on an outer edge of the main surface 10s of the substrate 10 is input, and the off-angle (θm, θa) at the position (x, y) on the outer edge of the main surface 10s is output to a display unit described later.
Next, as illustrated in
At this time, the region where the off-angle (θm, θa) satisfies the formula (2), that is, the region overlapping region A in the range of the main surface 10s of the substrate 10 is colored and displayed on the off-angle coordinate map 20. Thereby, it is possible to grasp that the surface morphology of the semiconductor layer 50 is good in at least a part of the region where the off-angle (θm, θa) satisfies the formula (2).
Further, at this time, the region where the off-angle (θm, θa) satisfies the formulas (3-1) and (3-2), that is, the region overlapping region B in the range of the main surface 10s of the substrate 10 is colored and displayed on the off-angle coordinate map 20. Thereby, it is possible to grasp that the surface morphology of the semiconductor layer 50 is good over the entire region where the off-angle (θm, θa) satisfies the formulas (3-1) and (3-2).
Further, at this time, the region where the off-angle (θm, θa) satisfies the formulas (4-1) and (4-2), that is, the region overlapping region C in the range of the main surface 10s of the substrate 10 is colored and displayed on the off-angle coordinate map 20. Thereby, it is possible to grasp that the surface morphology of the semiconductor layer 50 is good over the entire region where the off-angle (θm, θa) satisfies the formulas (4-1) and (4-2).
It should be noted that the region where the off-angle (θm, θa) satisfies the formula (2), the region where the off-angle (θm, θa) satisfies the formulas (3-1) and (3-2), and the region where the off-angle (θm, θa) satisfies the formulas (4-1) and (4-2) may be displayed in different colors.
When the off-angle coordinate map 20 is provided in advance, the off-angle outputting step S420 and the map displaying step S440 do not have to be performed.
After causing a range of the main surface 10s of the substrate 10 to be displayed on the off-angle coordinate map 20, the computer 70 makes the pick-up apparatus 80 cause to execute the semiconductor device selection program to selectively pick-up the semiconductor device 40 based on the off-angle coordinate map 20. For example, when the off-angle (θm, θa) obtained by the formula (1) satisfies a predetermined condition at a predetermined position (x, y) in the main surface 10s of the substrate 10, the semiconductor device 40 is selectively picked up at the predetermined position.
Specifically, in the semiconductor device 40 cut from the region where the off-angle (θm, θa) satisfies the formula (2) in the main surface 10s of the actual substrate 10, it is determined that the surface morphology of the semiconductor layer 50 is possibly good, and the semiconductor device 40 is selectively picked up as a good product.
Alternatively, in the semiconductor device 40 cut from the region where the off-angle (θm, θa) satisfies the formulas (3-1) and (3-2) in the main surface 10s of the actual substrate 10, it is determined that the surface morphology of the semiconductor layer 50 is surely good, and the semiconductor device 40 is selectively picked up as a best product.
Alternatively, in the semiconductor device 40 cut from the region where the off-angle (θm, θa) satisfies the formulas (4-1) and (4-2) in the main surface 10s of the actual substrate 10, it is determined that the surface morphology of the semiconductor layer 50 is surely good, and the semiconductor device 40 is selectively picked up as a best product.
Meanwhile, in the semiconductor device 40 cut from the region where the off-angle (θm, θa) does not satisfy the above conditions in the main surface 10s of the actual substrate 10, it is determined that the surface morphology of the semiconductor layer 50 is rough and the semiconductor device 40 is excluded as a defective product.
As described above, the semiconductor device 40 as the SBD of this embodiment is manufactured.
According to this embodiment, one or more of the following effects can be obtained.
(a) In this embodiment, the c-face 10f of the substrate 10 is a curved surface shape that is approximated to a spherical surface in each of its cross-sections along m-axis and along a-axis. In addition, the radius of curvature of the c-face 10f is sufficiently larger than the radius of the substrate 10 in each of cross-sections along m-axis and along a-axis. Thereby, the off-angle (θm, θa) at an arbitrary position (x, y) in the main surface 10s of the substrate 10 can be approximately represented by the formula (1). The constants M1, A1, M2, and A2 in the formula (1) are adjusted, so that the off-angle distribution (variation in the off-angle) in the main surface 10s of the substrate 10 can be easily adjusted within a predetermined range. As a result, it is possible to easily control the surface morphology of a semiconductor layer 50, which depends on the off-angle in the main surface 10s of the substrate 10.
(b) The off-angle (θm, θa) in the main surface 10s of the substrate 10 is approximately represented by the formula (1), that is, each of the off-angle m-axis component θm and the off-angle a-axis component θa is approximately represented by the linear formula of x and y, so that the constants M1, A1, M2, and A2 in the formula (1) can be determined by only measuring the off-angle (θm, θa) at several points on the main surface 10s of the substrate 10, in the off-angle measuring step S220. In other words, the formula (1) can be easily derived from the measurement of the off-angle at several points.
(c) The off-angle (θm, θa) in the main surface 10s of the substrate 10 is approximately represented by the formula (1), so that the off-angle (θm, θa) at an arbitrary position (x, y) in the main surface 10s of the substrate 10 can be immediately obtained by the formula (1). For example, in the semiconductor device selecting step S500, the user provided with to whom the substrate 10 or the semiconductor laminate 30 has been provided can refer to the off-angle (θm, θa) at an arbitrary position (x, y) in the main surface 10s of the substrate 10 without measuring the off-angle of the entire substrate 10.
(d) The off-angle (θm, θa) in the main surface 10s of the substrate 10 is approximately represented by the formula (1), so that a range of the main surface 10s of the substrate 10 can be displayed on the off-angle coordinate map 20 wherein the off-angle m-axis component θm and the off-angle a-axis component θa are coordinate axes.
Incidentally, when the off-angles are discretely distributed within the main surface of the substrate or non-linearly distributed with respect to the position of the main surface of the substrate, there is a possibility that the range of the main surface of the substrate cannot be displayed on the off-angle coordinate map in correspondence with the range of the main surface of the actual substrate. Therefore, it is difficult to grasp how the off-angles are distributed within the main surface of the substrate.
In contrast, in this embodiment, the off-angle (θm, θa) in the main surface 10s of the substrate 10 is approximately represented by the formula (1), so that the range of the main surface 10s of the substrate 10 can be displayed on the off-angle coordinate map 20 in correspondence with the range of the main surface 10s of the actual substrate 10. Thereby, it is possible to easily grasp the off-angle distribution in the main surface 10s of the substrate 10. For example, in the off-angle coordinate map 20, when the range of the main surface 10s of the substrate 10 is large, it can be grasped that the off-angle distribution of the main surface 10s of the substrate 10 is wide. On the other hand, when the range of the main surface 10s of the substrate 10 is small, it can be grasped that the off-angle distribution of the main surface 10s of the substrate 10 is narrow.
(e) In the off-angle coordinate map 20, the range of the main surface 10s of the substrate 10 is displayed, so that it is possible to easily grasp the surface morphology distribution of the semiconductor layer 50 in a range of the main surface 10s of the substrate 10, so as to correspond to the dependence of the surface morphology of the semiconductor layer 50 on the off-angle of the main surface 10s of the substrate 10. In other words, the surface morphology of the semiconductor layer 50 can be predicted based on the off-angle (θm, θa) at an arbitrary position (x, y) in the main surface 10s of the substrate 10. Thereby, the semiconductor device 40 where the surface morphology of the semiconductor layer 50 is good can be selected in the semiconductor device selecting step S500 without actually performing the surface morphology measurement (AFM, etc.) of the semiconductor layer 50.
(f) In the substrate 10 of this embodiment, an absolute value of a rate of change in the off-angle m-axis component m, |M1|, is different, for example, from an absolute value of a rate of change in the off-angle a-axis component θa, |A1|. Thereby, the range of the main surface 10s of the substrate 10 can be easily adjusted to correspond to a complicated distribution of the good surface morphology region in the off-angle coordinate map 20.
Here, as illustrated in
Thus, in this embodiment, since |M1|# |A1|, the off-angle distribution in the main surface 10s of the substrate 10 can be anisotropic, that is, the range of the main surface 10s of the substrate 10 can be an ellipse on the off-angle coordinate map 20. Thereby, it is possible to easily adjust the off-angle distribution in the main surface 10s of the substrate 10, so as to correspond to the complicated distribution of the good surface morphology region on the off-angle coordinate map 20. As a result, the portion where the surface morphology of the semiconductor layer is good can be widened efficiently in the main surface 10s of the substrate 10.
(g) Furthermore, in the substrate 10 of this embodiment, the absolute value of the rate of change in the off-angle m-axis component θm, |M1|, is smaller than, for example, the absolute value of the rate of change in the off-angle a-axis component θa, |A1|. Here, in the good surface morphology region of the off-angle coordinate map 20 described above, there are many regions that are short in the m-axis direction and long in the θa-axis direction. Therefore, in this embodiment, since |M1|<|A1|, the range of the main surface 10s of the substrate 10 can be easily adjusted to correspond to the region that is short in the m-axis direction and long in the θa-axis direction among the good surface morphology regions in the off-angle coordinate map 20. As a result, the portion where the surface morphology of the semiconductor layer is good can be widened more efficiently in the main surface 10s of the substrate 10.
(h) The off-angle (θm, θa) in at least a part of the main surface 10s of the substrate 10 of this embodiment is included in at least any one of regions A, B, and C. Thereby, the portion where the surface morphology of the semiconductor layer 50 is good can be obtained from at least a part of the semiconductor laminate 30 in which the substrate 10 is used. Since the semiconductor device 40 is fabricated from the portion where the surface morphology of the semiconductor layer 50 is good, it is possible to suppress local electric field concentration on the surface of the semiconductor layer 50. As a result, the withstand voltage of the semiconductor device 40 can be improved.
(i) In this embodiment, at arbitrary position in the main surface 10s of the substrate 10, an error of the off-angle actually measured with respect to the off-angle obtained by the formula (1), Δθ, is within ±0.12°. Thereby, it is possible to suppress the range of the main surface 10s of the substrate 10 based on the off-angle actually measured from being excessively wider than the range of the main surface 10s of the substrate 10 obtained by the formula (1) in the off-angle coordinate map 20. As a result, it is possible to suppress the off-angle (θm, θa) in at least a part of the main surface 10s of the actual substrate 10 from deviating from the aforementioned region A, B, or C.
Embodiments of the present invention have been specifically described above. However, the present invention is not limited to the aforementioned embodiments, and can be variously modified in a range not departing from the gist of the invention.
The aforementioned embodiments have been described for the case where the substrate 10 is a GaN free-standing substrate. However, the substrate 10 is not limited to the GaN free-standing substrate. For example, the substrate 10 may be the free-standing substrate including a group III nitride semiconductor such as aluminum nitride (AN), aluminum gallium nitride (AlGaN), indium nitride (InN), indium gallium nitride (InGaN), or aluminum indium gallium nitride (AlInGaN), that is, a group III nitride semiconductor represented by a composition formula of AlxInyGa1-x-yN (0≤x≤1, 0≤y≤1, 0≤x+y≤1).
The aforementioned embodiments have been described for the case where the substrate 10 is n-type. However, the substrate 10 may be p-type, or may have semi-insulating property. For example, in the case of manufacturing a semiconductor device as a high electron mobility transistor (HEMT) using the substrate 10, it is preferable that the substrate 10 has the semi-insulating property.
The aforementioned embodiments have been described for the case where the semiconductor layer 50 includes GaN. However, the semiconductor layer 50 is not limited to include GaN, and the semiconductor layer 50 may include, for example, a group III nitride semiconductor such as AlN, AlGaN, InN, InGaN, or AlInGaN, that is, a group III nitride semiconductor represented by a composition formula of AlxInyGa1-x-yN (0≤x≤1, 0≤y≤1, 0≤x+y≤1).
The aforementioned embodiments have been described for the case where the semiconductor layer 50 includes the same group III nitride semiconductor as that of the substrate 10. However, at least one of the semiconductor layers 50 may include a group III nitride semiconductor different from that of the substrate 10.
The aforementioned embodiments have been described for the case where the semiconductor device 40 fabricated from the semiconductor laminate 30 is SBD. However, the semiconductor device 40 may be the one other than SBD. Specifically, the semiconductor device 40 may be, for example, a pn junction diode, a junction barrier Schottky diode, HEMT, or the like.
In the case that the semiconductor device 40 is a pn junction diode as a light emitting element and the light emitting layer includes In, since the off-angle distribution (variation in the off-angle) in the main surface 10s of the substrate 10 is adjusted within a predetermined range, it is possible to suppress the variation in the In content in the light emitting layer.
The aforementioned embodiments have been described for the case where the absolute value of a rate of change in the off-angle m-axis component θm, |M1|, is smaller than the absolute value of a rate of change in the off-angle a-axis component θa, |A1|. However, the absolute value of the rate of change in the off-angle a-axis component θa, |A1|, may be smaller than the absolute value of the rate of change in the off-angle m-axis component θm, |M1|. Thereby, in the off-angle coordinate map 20, the range of the main surface 10s of the substrate 10 can be easily adjusted so as to correspond to the region that is short in the θa-axis direction and long in the θm-axis direction in the good surface morphology regions.
The aforementioned embodiments have been described for the case where the substrate 10 is fabricated by the VAS method in the nitride semiconductor substrate fabricating step S100. However, a method other than the VAS method may be used as long as it is a method for fabricating the substrate 10 by using a heterogeneous substrate including a material different from that of the group III nitride semiconductor and by peeling the crystal layer from the heterogeneous substrate.
The aforementioned embodiments have been described for the case where the second crystal layer 6 is sliced using a wire saw in the slicing step S170. However, for example, an outer peripheral blade slicer, an inner peripheral blade slicer, an electric discharge machine, or the like may be used.
The aforementioned embodiments have been described for the case where (a) a method of utilizing the direction dependence of the warpage of the second crystal layer 6 in the peeling step S160, (b) a method of utilizing the direction dependence of the wire saw in the slicing step S170, and (c) a method of making the attachment surface of the holder 82 an elliptical spherical surface in the polishing step S180 are used as methods to attain |M1|≠|A1|. However, as the method to attain |M1|≠|A1|, at least any one of the methods (a), (b), and (c) may be used.
The aforementioned embodiments have been described for the case where the semiconductor laminate 30 is provided to the user side together with the substrate data output program and the semiconductor device selection program, and, after the semiconductor device fabricating step S400, the off-angle outputting step S520, the map displaying step S540, and the good product determining step S560 are performed as the semiconductor device selecting step S500 on the user side, but are not limited thereto. In addition to the aforementioned cases, for example, the following two modified examples can be contemplated.
In modified example 1, first, the off-angle outputting step S520 and the map displaying step S540 are performed after the nitride semiconductor substrate fabricating step S100 or the semiconductor laminate fabricating step S300, to obtain the off-angle coordinate map 20. After the off-angle coordinate map 20 is obtained, the semiconductor laminate 30 is provided to the user side together with, for example, the off-angle coordinate map 20. Next, the semiconductor device fabricating step S400 is performed on the user side. After the semiconductor device fabricating step S400, the good product determining step S560 is performed based on the off-angle coordinate map 20 which has been already provided, without performing the off-angle outputting step S520 and the map displaying step S540.
In modified example 2, after the constants M1, A1, M2, and A2 are obtained in the off-angle measuring step S220, only a semiconductor device selection program is prepared based on the formula (1) including the constants M1, A1, M2, and A2. Namely, a substrate data output program and an off-angle coordinate map 20 are not prepared. After the semiconductor laminate fabricating step S300, the semiconductor laminate 30 is provided to the user side together with the semiconductor device selection program. Next, the semiconductor device fabricating step S400 is performed on the user side. After the semiconductor device fabricating step S400, the good product determining step S560 is performed without performing the off-angle outputting step S520 and the map displaying step S540. In the good product determining step S560, when the off-angle (θm, θa) obtained by the formula (1) satisfies a previously set condition at a predetermined position (x, y) in the main surface 10s of the substrate 10, the semiconductor device 40 at the predetermined position is selectively picked up.
As in modified examples 1 and 2, the program and the like to be provided when the semiconductor laminate 30 is provided to the user side may be appropriately selected, and each step may be modified according to the selected program and the like.
Hereinafter, various experimental results which support the effect of the present invention will be described.
Using the VAS method as in the aforementioned embodiment, the nitride semiconductor substrates of Examples 1 to 3 (sometimes referred to as substrates hereafter) having the following constitutions were prepared under almost the same growth conditions.
Substrate: GaN free-standing substrate
Diameter of substrate: 4 inches
Thickness of substrate: 400 μm
Conductivity type of substrate: n-type
N-type impurity in substrate: Si
N-type impurity concentration in substrate: (Example 1) Non-doped, (Example 2) 1.21×1018 cm−3, (Example 3) Non-doped
Main surface of substrate: +c-face
Oli-fla of substrate: m-face, i.e., γ=900
X direction of substrate: approximately a-axis direction
Y direction: approximately m-axis direction
The thicknesses of the substrates of Examples 1 to 3 were 472 μm, 504 μm, and 501 μm, respectively. Further, the dislocation densities (average dislocation density) in the substrates of Examples 1 to 3 were almost the same with each other, and 1.39×106 cm−2. Furthermore, the electron mobilities in the substrates of Examples 1 to 3 were 337 cm2/Vs, 323 cm2/Vs, and 342 cm2/Vs, respectively.
The off-angle (θm, θa) was measured at a plurality of points on each of x-axis and y-axis in the main surface of the substrate of Example 1 to Example 3 by a rocking curve measurement of X-ray diffraction.
A result of a measurement of an off-angle of the nitride semiconductor substrate in Examples 1 to 3 will be described, with reference to
As illustrated in
As illustrated in
In Example 1 to Example 3, linear approximation of the off-angle m-axis component θm with respect to the position on y-axis by the least-square method provided the constants M1 and M2 in the formula (1)′. Further, linear approximation of the off-angle a-axis component θa with respect to the position on x-axis by the least-square method provided the constants A1 and A2 in the formula (1)′.
The following Table 1 illustrates constants M1, A1, M2 and A2 of Examples 1 to 3.
The following Table 2 illustrates a maximum absolute value of an error of the off-angle m-axis component θm actually measured with respect to the off-angle m-axis component θm obtained by the formula (1)′ (θm maximum error), and a maximum absolute value of an error of the off-angle a-axis component θa actually measured with respect to the off-angle a-axis component θa obtained by the formula (1)′ (θa maximum error), in each of Example 1 to Example 3.
As illustrated in Table 2, in Example 1 to Example 3, each of the θm maximum error and the θa maximum error was 0.12° or less. That is, in Example 1 to Example 3, it is confirmed that an error of the off-angle actually measured with respect to the off-angle obtained by the formula (1), Δθ, is within ±0.12°. Therefore, in Example 1 to Example 3, it is confirmed that the c-face of the substrate is approximated to a spherical surface with high accuracy in each of its cross-sections along m-axis and along a-axis.
Further, in Example 1 to Example 3, the θm maximum error was about 0.02°, whereas the θa maximum error was about 0.12°. That is, in Example 1 to Example 3, it is confirmed that, at the center of the main surface of the substrate, θm>θa (i.e., M2> A2), and the θm maximum error is smaller than the θa maximum error.
Next, the off-angle coordinate map for Example 2 will be described as a representative example, with reference to
As illustrated in
Further, it is confirmed that the off-angle (θm, θa) at least at a part of the main surface of the substrate of Example 2 is included in region A and satisfies the aforementioned formula (2). Moreover, it is confirmed that the off-angle (θm, θa) at least at the center of the main surface of the substrate of Example 2, that is, (M2, A2) is, for example, included in region A and satisfies the aforementioned formula (2). Furthermore, it is confirmed that the proportion of the area of the region where the off-angle (θm, θa) satisfies the formula (2) with respect to the total area of the main surface of the substrate of Example 2 is more than 50%, preferably 90% or more.
It is confirmed that the off-angle (θm, θa) at least at a part of the main surface of the substrate of Example 2 is included in region B and satisfies the aforementioned formulas (3-1) and (3-2). Moreover, it is confirmed that the off-angle (θm, θa) at least at the center of the main surface of the substrate of Example 2, that is, (M2, A2) is, for example, included in region B and satisfies the aforementioned formulas (3-1) and (3-2). Furthermore, it is confirmed that the proportion of the area of the region (colored region) where the off-angle (θm, θa) satisfies the formulas (3-1) and (3-2) with respect to the total area of the main surface of the substrate of Example 2 is more than 50%, preferably 80% or more.
Although not illustrated in figures, it is confirmed that the off-angle coordinate maps in Examples 1 and 3 are similar to the off-angle coordinate map in Example 2.
The semiconductor laminate having the following constitution was fabricated using the substrate of Example 2.
Structure of layer: (from the substrate side) base n-type semiconductor layer, drift layer
Constitution of base n-type semiconductor layer: Si-doped GaN layer
Si concentration in base n-type semiconductor layer: 2×1018 cm−3
Thickness of base n-type semiconductor layer: 2 μm
Constitution of drift layer: Si-doped GaN layer
Si concentration in drift layer: 0.9×1016 cm−3
Thickness of drift layer: 13 μm
Further, the semiconductor device as the SBD having the following constitution was fabricated using the semiconductor laminate of Example 2.
(Constitution of Semiconductor Device)
P-type electrode: Pd/Ni film
Diameter of p-type electrode: 100 μm
N-type electrode: Ti/Al film
The surface morphology of the semiconductor layer was measured by AFM in the predetermined region of the semiconductor laminate of Example 2.
In the semiconductor device of Example 2, a reverse bias was applied and the dielectric breakdown withstand voltage (hereinafter, abbreviated as withstand voltage) was measured.
In the semiconductor laminate of Example 2, it is confirmed that the surface roughness Ra of the semiconductor layer is about 7 nm in the region where the off-angle (θm, θa) of the substrate satisfies the formulas (3-1) and (3-2). That is, it is confirmed that the surface morphology of the semiconductor layer is good in the region where the off-angle (θm, θa) of the substrate satisfies the formulas (3-1) and (3-2).
In the semiconductor device of Example 2, it is confirmed that the withstand voltage is at least 1 kV or more in the region where the off-angle (θm, θa) of the substrate satisfies the formulas (3-1) and (3-2). That is, in the region, it is confirmed that since the surface roughness of the semiconductor device is small, it is possible to suppress local electric field concentration and to improve the withstand voltage of the semiconductor device.
Preferable aspects of the present invention will be supplementarily described hereafter.
A nitride semiconductor substrate including a group III nitride semiconductor crystal and having a main surface,
The nitride semiconductor substrate according to the supplementary description 1,
The nitride semiconductor substrate according to supplementary description 2,
The nitride semiconductor substrate according to any one of the supplementary descriptions 1 to 3,
The nitride semiconductor substrate according to any one of the supplementary descriptions 1 to 4,
The nitride semiconductor substrate according to the supplementary description 5, wherein the off-angle (θm, θa) at least at the center of the main surface satisfies the formula (2).
The nitride semiconductor substrate according to the supplementary description 5 or 6,
The nitride semiconductor substrate according to any one of the supplementary descriptions 1 to 4,
The nitride semiconductor substrate according to the supplementary description 8,
The nitride semiconductor substrate according to the supplementary description 8 or 9,
The nitride semiconductor substrate according to any one of the supplementary descriptions 1 to 10,
The nitride semiconductor substrate according to any one of the supplementary descriptions 1 to 4,
The nitride semiconductor substrate according to the supplementary description 12,
The nitride semiconductor substrate according to the supplementary description 12 or 13,
The nitride semiconductor substrate according to any one of the supplementary descriptions 1 to 7, and 12 to 14,
The nitride semiconductor substrate according to any one of the supplementary descriptions 1 to 15,
The nitride semiconductor substrate according to the supplementary description 16,
A nitride semiconductor substrate including a group III nitride semiconductor crystal, and having a main surface and an orientation flat constituting a part of a side surface connected to the main surface,
A semiconductor laminate including:
The semiconductor laminate according to the supplementary description 19,
The semiconductor laminate according to the supplementary description 19,
A substrate selection program for making a computer execute selection of a nitride semiconductor substrate including a group III nitride semiconductor crystal and having a main surface, after fabrication of the nitride semiconductor substrate;
The substrate selection program, or recording medium according to the supplementary description 22,
The substrate selection program, or recording medium according to the supplementary description 22 or 23,
The substrate selection program, or recording medium according to the supplementary description 22 or 23,
The substrate selection program, or recording medium according to the supplementary description 22 or 23,
A substrate data output program provided along with a nitride semiconductor substrate including a group III nitride semiconductor crystal and having a main surface, for making a computer execute output of data regarding a state of the main surface of the nitride semiconductor substrate;
The substrate data output program, or recording medium according to the supplementary description 27,
The substrate data output program, or recording medium according to the supplementary description 28,
The substrate data output program, or recording medium according to the supplementary description 28,
The substrate data output program, or recording medium according to the supplementary description 28,
A nitride semiconductor substrate provided with a substrate output program,
An off-angle coordinate map output by the substrate data output program according to any one of the supplementary descriptions 28 to 31.
A nitride semiconductor substrate provided with an off-angle coordinate map,
A semiconductor device selection program for making a computer cause a pick-up apparatus to execute selective pick-up of a semiconductor device, when the semiconductor device is manufactured using a nitride semiconductor substrate including a group III nitride semiconductor crystal and having a main surface;
A nitride semiconductor substrate provided with a semiconductor device selection program, which is provided along with the semiconductor device selection program according to the supplementary description 35.
A manufacturing method of a nitride semiconductor substrate, including
The manufacturing method of a nitride semiconductor substrate according to the supplementary description 37,
The manufacturing method of a nitride semiconductor substrate according to the supplementary description 38,
The manufacturing method of a nitride semiconductor substrate according to the supplementary description 38 or 39,
The manufacturing method of a nitride semiconductor substrate according to any one of the supplementary descriptions 37 to 40, including: measuring the off-angles at two or more points in the main surface after the fabrication of the nitride semiconductor substrate, and thus obtaining the M1, the M2, the A1, and the A2 in the formula (1).
A manufacturing method of a semiconductor laminate, including:
A manufacturing method of a semiconductor device, including:
The manufacturing method of a semiconductor device according to the supplementary description 43,
A substrate data output method for outputting data regarding a state of a main surface of the nitride semiconductor substrate including a group III nitride semiconductor crystal and having the main surface;
| Number | Date | Country | Kind |
|---|---|---|---|
| 2017-208139 | Oct 2017 | JP | national |
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/JP2018/029720 | 8/8/2018 | WO |
| Publishing Document | Publishing Date | Country | Kind |
|---|---|---|---|
| WO2019/082472 | 5/2/2019 | WO | A |
| Number | Name | Date | Kind |
|---|---|---|---|
| 6413627 | Motoki et al. | Jul 2002 | B1 |
| 9209021 | Okuno | Dec 2015 | B2 |
| 10312409 | Li | Jun 2019 | B2 |
| 20020137249 | Ishida | Sep 2002 | A1 |
| 20050026398 | Nakamura | Feb 2005 | A1 |
| 20050224783 | Matsuyama et al. | Oct 2005 | A1 |
| 20080308814 | Nakahata et al. | Dec 2008 | A1 |
| 20130292688 | Ueno | Nov 2013 | A1 |
| 20170352721 | Iso et al. | Dec 2017 | A1 |
| Number | Date | Country |
|---|---|---|
| 2000-022212 | Jan 2000 | JP |
| 2005-056979 | Mar 2005 | JP |
| 2008-098664 | Apr 2008 | JP |
| 2008-308377 | Dec 2008 | JP |
| WO-2016136552 | Sep 2016 | WO |
| Entry |
|---|
| International Searching Authority, “International Search Report,” issued in connection with International Patent Application No. PCT/JP2018/029720, dated Oct. 30, 2018. |
| International Searching Authority, “Written Opinion,” issued in connection with International Patent Application No. PCT/JP2018/029720, dated Oct. 30, 2018. |
| Number | Date | Country | |
|---|---|---|---|
| 20210184003 A1 | Jun 2021 | US |
