Patent Application
20240397610
Vias and associated voids or gaps in conductor layers in substrates may have mechanical, electrical, or other issues, which may degrade system performance, waste package or board space, or otherwise constrain device or system layouts.
New structures and techniques are needed to improve system performance or reduce system or device sizes.
The material described herein is illustrated by way of example and not by way of limitation in the accompanying figures. For simplicity and clarity of illustration, elements illustrated in the figures are not necessarily drawn to scale. For example, the dimensions of some elements may be exaggerated relative to other elements for clarity. Further, where considered appropriate, reference labels have been repeated among the figures to indicate corresponding or analogous elements, e.g., with the same or similar functionality. The disclosure will be described with additional specificity and detail through use of the accompanying drawings:
In the following detailed description, reference is made to the accompanying drawings that show, by way of illustration, specific embodiments in which the claimed subject matter may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the subject matter. The various embodiments, although different, are not necessarily mutually exclusive. For example, a particular feature, structure, or characteristic described herein, in connection with one embodiment, may be implemented within other embodiments without departing from the spirit and scope of the claimed subject matter.
References within this specification to “one embodiment” or “an embodiment” mean that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one implementation encompassed within the present description. Therefore, the use of the phrase “one embodiment” or “in an embodiment” does not necessarily refer to the same embodiment. In addition, the location or arrangement of individual elements within each disclosed embodiment may be modified without departing from the spirit and scope of the claimed subject matter. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the subject matter is defined only by the appended claims, appropriately interpreted, along with the full range of equivalents to which the appended claims are entitled.
The terms “over,” “to,” “between,” and “on” as used herein may refer to a relative position of one layer with respect to other layers. One layer “over” or “on” another layer or bonded “to” another layer may be directly in contact with the other layer or may have one or more intervening layers. One layer “between” layers may be directly in contact with the layers or may have one or more intervening layers.
The terms “coupled” and “connected,” along with their derivatives, may be used herein to describe structural relationships between components. These terms are not intended as synonyms for each other. Rather, in particular embodiments, “connected” may be used to indicate that two or more elements are in direct physical or electrical contact with each other. “Coupled” may be used to indicated that two or more elements are in either direct or indirect (with other intervening elements between them) physical or electrical contact with each other, and/or that the two or more elements co-operate or interact with each other (e.g., as in a cause an effect relationship, an electrical relationship, a functional relationship, etc.).
The term “circuit” or “module” may refer to one or more passive and/or active components that are arranged to cooperate with one another to provide a desired function. The term “signal” may refer to at least one current signal, voltage signal, magnetic signal, or data/clock signal. The meaning of “a,” “an,” and “the” include plural references. The meaning of “in” includes “in” and “on.”
The vertical orientation is in the z-direction and recitations of “top,” “bottom,” “above,” and “below” refer to relative positions in the z-dimension with the usual meaning. However, embodiments are not necessarily limited to the orientations or configurations illustrated in the figure.
The terms “substantially,” “close,” “approximately,” “near,” and “about,” generally refer to being within +/−10% of a target value (unless specifically specified). Unless otherwise specified in the specific context of use, the term “predominantly” means more than 50%, or more than half. For example, a composition that is predominantly a first constituent means more than half of the composition is the first constituent. The term “primarily” means the most, or greatest, part. For example, a composition that is primarily a first constituent means the composition has more of the first constituent than any other constituent. A composition that is primarily first and second constituents means the composition has more of the first and second constituents than any other constituent.
Unless otherwise specified the use of the ordinal adjectives “first,” “second,” and “third,” etc., to describe a common object, merely indicate that different instances of like objects to which are being referred and are not intended to imply that the objects so described must be in a given sequence, either temporally, spatially, in ranking or in any other manner.
For the purposes of the present disclosure, phrases “A and/or B” and “A or B” mean (A), (B), or (A and B). For the purposes of the present disclosure, the phrase “A, B, and/or C” means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B and C).
Views labeled “cross-sectional,” “profile,” and “plan” correspond to orthogonal planes within a cartesian coordinate system. Thus, cross-sectional and profile views are taken in the x-z and y-z planes, and plan views are taken in the x-y plane. Typically, profile views in the x-z plane are cross-sectional views. Where appropriate, drawings are labeled with axes to indicate the orientation of the figure.
Structures and techniques are disclosed that improve the performance of integrated circuit (IC) devices with vias in packages having IC dies. An improved via antipad profile provides electrical and mechanical benefits in these IC packages. A via with a tapered antipad void profile may approximate the electrical performance of a wide, stacked void profile while having improved mechanical performance. This enhanced mechanical performance may allow for increased routing flexibility and enable high interconnect densities, for example, under an IC die in an IC package substrate. Tighter routing and interconnect layouts may allow for smaller IC package sizes.
Conductive vias in IC packages may be used to connect structures in different levels of the IC package. For example, vias may make electrical connections (e.g., to conductive traces) at one or more levels of the package. Vias may also have pads (e.g., conductive discs centered on the via) at one or more levels of the package, for example, at any level(s) where the conductive via connects to a conductive trace. The conductive pads may provide advantages (for example, electrical, mechanical, manufacturing, or reliability advantages). A via may also have antipads around the via at one or more levels along the via.
Antipads are regions around a via where certain conductive structures are not present. For example, an antipad may be an opening or void in a conductive plane, such as a circular hole in a plane or thin layer of copper. During design of the IC package (e.g., when laying out a package substrate coupled to an IC die and including a conductive via), antipads may be “keepout” areas around a via where conductors are generally forbidden from being placed. A keepout area may be defined by a radius around, or diameter centered on, the via. These keepouts may be defined by other means or dimensions. While the conductive via (and structures, such as traces, electrically connected to the via) may be within the antipad, other conductors are excluded. Such excluded conductors may be adjacent conductive traces that are routed nearby, but that should maintain the antipad's minimum required distance from the via. As discussed, in otherwise continuous layers of copper (or other conductors), an antipad may present as a hole in the conductive layer. These holes or voids without excluded conductors may instead be filled with an insulator material, such as a dielectric material separating conductive layers in a package substrate.
In contrast to a tapered void profile, stacked (or vertically aligned) antipad voids in IC packages may have mechanical issues, e.g., susceptibility to shear forces. For this reason, manufacturing design rules may forbid voids with aligned edges in vertically adjacent conductor layers in certain regions, for example, under IC dies. These design rules may address problem regions when a package is subjected to vertical forces, e.g., clamping or other retention forces in a socketed system, such as during product validation testing. But these design rules may also interfere with package routing. For example, multilevel vias may be problematic as both vital for input/output (I/O) interconnects under IC dies and especially vulnerable to shear forces. High-speed interconnects may be sensitive to impedance mismatches and particularly problematic as increased void sizes (e.g., with larger diameters or radii) may improve impedance matching and signaling performance, but also increase susceptibility to vertical forces. The package routing or other layout issues caused by these mechanical vulnerabilities and/or associated design rules may result in wasted area during layout. Traces may need to be routed out from under an IC die to a via and back under the IC die. I/O interconnects may need to be laid out less densely to allow for a single, tall via to be replaced by more and shorter vias spread out laterally. An improved via antipad profile would enable smaller IC packages while permitting robust reliability (and validation, etc.) results while not degrading device electrical performance.
The disclosed antipad profile allows for wider antipad voids at the top and bottom of a via (e.g., around conductive pads there) while having one or more narrower antipad voids between the top and bottom. An improved antipad profile provides sufficient mechanical strength (such as resilience against shear, vertical forces), as well as the electrical benefits of increased void sizes. A tapered or concave profile reduces capacitance between conductors adjacent the via and conductive pads at via ends with more spacious antipads, while allowing for smaller antipads and gaps between conductors vertically further from the conductive pads (e.g., between the via and a ground plane near a midpoint of the via). A concave profile may have one or more narrowest antipad void(s) at a waist (or midpoint) of the via, antipad voids with increasing diameters moving away from the waist, and widest antipad voids at the top and bottom. Other profiles may have antipads with borders otherwise vertically misaligned.
A tapered profile reduces constraints on vertical routing, allowing routing between nearby or even the uppermost and lowermost levels in a package substrate, and even directly under an IC die. A tapered profile enables a smaller package form factor by this improved vertical routing, as well as by eliminating otherwise necessary lateral routing back and forth from under and to the sides of an IC die. A tapered profile also enables a smaller package by allowing for dense layouts of I/O interconnects under IC dies. A smaller package provides packaging and layout flexibility and reduces costs. A tapered profile also improves signaling performance, e.g., insertion loss (IL), reflection loss (RL), and impedance (Z) continuity for a single via or pair of vias, as will be discussed elsewhere herein, and by allowing for increased spacing between traces (e.g., in a same-sized package) by reducing the need for extra routing.
The profile of antipad voids 125 with a narrower diameter near a midpoint of via 130 may be characterized as a tapered or concave void or antipad profile. With the improved mechanical performance of the tapered void profile, vias 130 may be located under IC die 110 without the need for a keepout area in a die shadow. With the improved structure of via 130 and tapered profile of antipad voids 125, IC package 100 has increased routing flexibility and I/O interconnect density (e.g., under IC die 110) and decreased package size (e.g., in an x-y plane). In some embodiments, the tapered antipad profile is employed throughout package substrate 101 and package 100. In some embodiments, the tapered antipad profile is used under die 110. In some such embodiments, the stacked or vertically aligned profile is also used in IC package 100, but not under IC die 110. In some embodiments, the tapered antipad profile is used for some vias 130 (e.g., of a certain height or taller), but not for others. In some such embodiments, the vertically aligned profile is employed for blind or buried vias 130, but not for through vias 130.
Vias 130 are substantially vertical structures between different layers 120 of IC package 100, e.g., connecting structures in different layers 120. Vias 130 have a circular cross-section (e.g., in an x-y plane) in some embodiments. For example, vias 130 may be substantially vertical, substantially cylindrical solid structures of electrically conductive material (such as copper or another metal) or tubes of such a material, e.g., with the conductive material on an interior sidewall of a hole through layers 120. Vias 130 may be other shapes. (Although the term “diameter” may be used to refer to a lateral dimension of via 130 or antipad void 125, via 130 or antipad void 125 may be shapes with non-circular cross-sections, and “diameter” may refer to a lateral dimension, such as a length or width, of such a feature.) Via 130 may have one or more pads 131, e.g., at upper and lower ends, and connections 133 to via 130 and/or pads 131. Pads 131 may be considered parts of vias 130. Vias 130, pads 131, traces 135, and conductors 121 may all be or include the same or various conductive materials. In some embodiments, one or more of these conductive structures is of copper. In other embodiments, one or more of vias 130, pads 131, traces 135, and conductors 121 are of aluminum or stainless steel. In other embodiments, one or more of these conductive structures is of another conductive material, such as a metal.
Antipad voids 125 (which may also be referred to as antipads 125) are regions in layers 120 around via 130 without any of conductors 121 in the region. While conductors 121 may be absent in antipads 125, in addition to vias 130, antipads 125 may include pads 131 and connections 133 to vias 130 and pads 131. Conductors 121 may be ground planes or other structures capable of carrying electrical current. Antipads 125, while devoid of conductors 121, may otherwise be filled with one or more insulators, such as a dielectric or other material separating conductive layers in a package substrate. In the example of
Package substrate 101 is a planar platform and may include dielectric and metallization structures, such as conductors 121, in multiple layers 120. Substrate 101 mechanically supports and electrically couples one or more IC dies 110. Substrate 101 may be of any suitable structure and material(s), for example, any sufficiently insulating material or materials. In many embodiments, substrate 101 includes organic materials, such as a plastic. Substrate 101 may include ceramic materials, silicon, or glass. In some embodiments, substrate 101 includes fiberglass weave in an epoxy resin. Glass or silicon may have advantages over, e.g., organic substrate materials, such as higher thermal conductivity, higher strength and stiffness, and a lower propensity for absorbing moisture. IC die(s) 110 may couple to substrate 101 on an upper surface of package substrate 101, or substrate 101 may have a well or cavity in which IC die(s) 110 may be located. An upper surface of substrate 101 may be flush with IC die(s) 110, or IC die(s) 110 might extend partially beyond the upper surface of substrate 101. At least one side of substrate 101 includes substrate interconnect interfaces for coupling (e.g., soldering, direct bonding, etc.) to one or more IC dies 110. The opposite side of substrate 101 may include similar interfaces or, e.g., copper pads for socketing or solder bumps for bonding the package to a host component, such as a printed circuit board (PCB). Substrate 101 may be any host component with substrate interconnect interfaces, including an interposer, etc. Substrate 101 may couple to any other host component, such as another substrate.
IC package 100 is coupled to a system substrate 199. IC package 100 is over system substrate 199. Only a portion of substrate 199 is shown under substrate 101 as substrate 199 spans beyond the edges of
Improved antipads 125 in antipad profile 222 have various diameters, such as D2, D4, D6, D9, and D11. Larger diameters near pads 131, connections 133, and upper and/or lower ends 237, 238 (e.g., D2 and D11 at levels L2 and L11) may improve electrical performance of via 130, while smaller diameters (e.g., D4, D6, and D9 at levels L4, L6, and L9) between larger diameters may improve mechanical performance. Profile 222 of antipads 125, with a narrower diameter near midpoint M, may be characterized as a tapered void profile 222. With the improved mechanical performance of the tapered void profile 222, vias 130 may be located under the IC die 110 without the need for a keep-out area in the die shadow. IC package 100 may have increased routing flexibility and I/O interconnect density (e.g., under IC die 110) and decreased package size (for example, laterally).
Larger diameters D2 and D11 may improve electrical performance of via 130, such as signal integrity, by reducing capacitance between via 130, including pads 131, and (e.g., grounded) conductors 121. This reduced capacitance may improve impedance matching and reduce losses from mismatch and corresponding reflections, for example, by minimizing insertion loss and optimizing return losses. Smaller diameters (e.g., D4, D6, and D9) away from pads 131 may improve impedance matching. Profile 222 of antipads 125 surrounding via 130 may be vertically symmetric, e.g., across midpoint M. In
Profile 222 of antipads 125 surrounding via 130 can be characterized as concave with slopes near ends 237, 238, flatter than slopes near midpoint M. For example, profile 222 is concave with slope S1 between levels L2 and La flatter than slope S2 between levels L4 and L6. The slopes of profile 222 are defined by the vertical heights H between antipads 125 (and layers 120) divided by the differences or deltas Δ between the staggered ends of antipads 125. Slope S1 is defined by height H1 between levels L2 and L4, and by delta Δ1 between the edges or boundaries of antipads 125 in levels L2 and L4. Slope S2 is defined by height H2 between levels L4 and L6, and by delta Δ2 between the edges or boundaries of antipads 125 in levels L4 and L6. (With slopes S1, S2 on either side of profile 222, deltas Δ1, Δ2 are equal to half of the differences of diameters D2, D4 and of diameters D4, D6, respectively, or equal to the differences of the radii of antipads 125 in the case of circular antipads 125.) Delta Δ1 is greater than delta Δ2, so slope S1 is less than (or flatter than) slope S2 (assuming heights H1, H2 are equal). Slope S2 being greater than slope S1 may allow for reducing capacitance with pads 131 while providing satisfactory mechanical performance. This tapered and symmetric profile may reduce impedance discontinuities along via 130. In the example of
Although package substrates 101 may often have six or twelve layers 120, substrates 101 may have more or fewer layers 120. Also, however many layers 120 substrate 101 has, a concave or tapered profile of antipads 125 may be employed for any via 130 with enough levels or layers 120, whether or not via 130 spans all of the layers 120 of substrate 101. Via 130 may be between layers 120 in a shorter stack of layers 120 or between only some layers 120 in a stack having many more layers 120.
Pad 131 of one via 130 may be in antipad 125 of another via 130. In some embodiments, keepout exceptions are made for conductors associated with paired adjacent vias 130 (e.g., pads 131 in the antipad of other via 130). In some embodiments, larger antipads are used in layers 120 with ground plane conductors 121 than in other layers 120, e.g., layers 120 with pads 131.
The circuit parameters for paired vias 130 with an improved, tapered antipad profile are plotted with a circle at antipad size of 0.385 mm, which is the weighted average of the various antipads 125 in the structure described at
The circuit parameters for paired vias 130 with a vertically aligned antipad profile are plotted with the other various shapes at their respective antipad sizes. Each (non-circle) shape represents paired vias 130 with stacks of antipads 125 having equal diameters (and radii). Antipads 125 at levels L2, L4, L6, L9, and L11 have radii ranging from 0.225 mm to 0.425 mm. For example, the data represented by squares are for two paired vias 130 with two stacks of antipads 125 having equal radii. In the case of the data represented by squares, half of the antipads 125 are coaxial with a first via 130 and the other half of the antipads 125 are coaxial with a second via 130, and all antipads 125 (e.g., at levels L2, L4, L6, L9, and L11) have radii equal to 0.225 mm. Notably, in the case of the data represented by squares (radii equal to 0.225 mm) and diamonds (radii equal to 0.275 mm), vias 130 are spaced such that their respective antipads 125 do not overlap and conductors 121 (e.g., at each of levels L2, L4, L6, L9, and L11) connect between vias 130.
A formula for differential impedance Zdiff is provided near the bottom of
Plots 601, 602 show self-inductance LAC and mutual inductance Lm, respectively, of the various modeled structures. Self-inductance LAC is greater than mutual inductance Lm, and their difference is the numerator, so increasing self-inductance LAC or decreasing mutual inductance Lm will increase differential impedance Zdiff. However, although both inductances increase with antipad size, self-inductance LAC and mutual inductance Lm increase more or less together, and their difference is relatively constant across the various antipad radii.
Plots 603, 604 show self-capacitance CAC and mutual capacitance Cm, respectively, of the various modeled structures. Increasing either or both of self-capacitance CAC and mutual capacitance Cm will increase differential impedance Zdiff. Plot 604 shows that mutual capacitance Cm is relatively constant across the various antipad radii.
Plot 603 show that, for the via pairs with vertically aligned antipads, self-capacitance CAC decreases significantly as antipad radii increases. This is much as has been described elsewhere herein (e.g., at least at
Plot 704 shows performance generally better than plots 701A, 702A and substantially similar to that of plot 703A, particularly at 10 GHz and below. Plot 704A is for a structure with a tapered void profile having a widest diameter at the upper and lower ends corresponding to the structure of plot 703A and a narrow diameter at the midpoint corresponding to the structure of plot 702A.
Plots 701-704 of
Multiple layers of conductors may be formed in a substrate with antipad voids of varying dimensions formed in the conductors. A narrowest antipad may be formed in a conductor between other conductors with wider antipads. The antipad voids may be formed in already formed conductors. For example, a hole may be etched or bored through a substantially continuous conductor layer, or some conductive material may be etched away in the desired antipad region. The conductors may be initially formed with antipad voids. For example, the antipad voids may be keepout regions automatically kept absent of conductors, and then a conductor layer may be formed with an antipad void in the conductors as-formed. A via may be formed in and through the antipads in multiple layers. Connections to the via may be made, for example, at the top and bottom of the via. The connections may be in one or more of the conductor layers with antipad voids or over and under these conductor layers. An IC die may be coupled to the substrate, including over the via.
Methods 800 begin with forming a first conductor having a first antipad in a first layer of a substrate at operation 810. The layer and conductor may be formed by any suitable means and of any suitable materials. In some embodiments, the layer and conductor are formed over a received substrate. In some embodiments, the first layer will be a substrate for forming subsequent layers over the first layer, e.g., in a single build-up direction or on both sides of, and directions from, the first-layer substrate. In many embodiments, the first layer and at least some subsequent layers are formed separately and assembled into a stack of layers. In many embodiments, the first layer and subsequent layers are formed in pairs of layers and assembled into a stack with an even number of layers. In some embodiments, layers are added to both sides of a first-layer substrate such that the eventual stack of layers has an even number of layers. In some embodiments, one, some, or all of the pairs include one layer that is mostly conductive material (such as copper or another metal), e.g., as a ground plane, and the other layer has some conductive material formed into various structures, such as conductive traces. For example, a substrate of a sufficiently insulating material (such as plastic, glass, fiberglass weave impregnated with resin, etc.) may have conductive material formed (e.g., deposited, plated, printed, etc.) on both sides of the substrate.
The conductive material may be formed using any suitable means. In many embodiments, photolithography is used to pattern various structures of conductive material. In some embodiments, the conductive material is deposited in desired pattern using a photomask or film. In many embodiments, the conductive material is deposited as a foil or film or other complete layer, and photolithographic mask is patterned onto the conductive layer before removing any conductive material not masked. In some embodiments, conductive material is deposited in complete layers on both sides of the substrate, and much of the conductive material is removed from one side (e.g., to form conductive traces, etc.) while moving little or no conductive material from the other side (e.g., for a ground plane).
In this way (or other ways), an antipad (or gap, hole, cavity, etc.) may be formed in a conductor. For example, a circular void or antipad may be formed in a mostly solid layer of copper (or other conductive material) with the center of the antipad (and the antipad's diameter) on a planned axis for a via to be subsequently formed. The axis may also be the planned center for other antipads in other, subsequent layers.
Methods 800 continue at operation 820 with forming a second conductor having a second antipad in a second layer. The second conductor and second layer may be formed before, concurrently with, or after the first conductor and first layer are formed, as described at operation 810, such that the first layer need not be the layer first formed. A second layer may be formed over (or under) the first layer or as one of a pair of layers with the first layer. In many embodiments, the second conductor and second layer are formed in a similar manner as (and either before, concurrently with, or after) the first conductor and first layer, such as in pairs of layers. The first and second layers may then be assembled (e.g., after careful alignment). In some such embodiments, the first and second layers are assembled each from separate pairs of layers, with each pair of layers sharing an insulating substrate between the layers. When assembling pairs of layers, two layers (each on separate substrates) may be contacted together (e.g., and bonded) or the two layers may be brought together with an insulating substrate or layer (without conductive material formed on any surface) between the two layers and substrates.
A second antipad may be formed in the second conductor similar to the first antipad in the first conductor (e.g., with positive or negative photoresist or photolithography). The second antipad may have a second diameter, shorter than the diameter of the first antipad, but centered on (e.g., bisected by) the same axis, such that the second antipad will be smaller than, but coaxial with, the first antipad (and that both antipads will be centered on the eventual via). Again, the layers should be carefully aligned before assembly to ensure the antipads (and eventual via) are coaxial.
Methods 800 continue with forming a third conductor having a third antipad in a third layer at operation 830. The third conductor and third layer may be formed before, concurrently with, or after the first and second conductors and first and second layers are formed, as described at operations 810, 820. In many embodiments, the third conductor and third layer are assembled in a stack of an even number of layers, for example, with three ground planes and three other layers with conductive structures formed on the layers. The third conductor and third layer may be formed over the second conductor and second layer such that the second layer is between the first and third layers. In embodiments with the first layer over the second layer, the second conductor and second layer may be over the third conductor and third layer such that the second layer is between the first and third layers.
A third antipad may be formed in the third conductor similar to the first and second antipads in the first and second conductors. The third antipad may have a third diameter, equal to the diameter of the first antipad and centered on the same axis, such that the third antipad will be coaxial with the first and second antipads (and the eventual via). In this way, the smaller second antipad will be coaxial with and between the first and third antipads, and the three antipads will collectively form a stack of antipads with a tapered antipad profile (around the axis and eventual via).
In some embodiments, one of the layers (or pairs of layers) may be a substrate that other layers are built up from, and that substrate may be the layer at the midpoint of the stack of layers. In some such embodiments, that substrate layer may have a middle and smallest antipad of the stack of antipads, and that substrate layer may be the second layer between the first and third layers and having the second antipad with the second, shorter diameter.
In some embodiments, methods 800 include forming a fourth conductor having a fourth antipad in a fourth layer. The fourth conductor and fourth layer may be formed much as other conductors and layers, but should be included in the stack of layers during assembly such that the fourth layer is between the first and third layers, and the second layer is at a midpoint of the via or at least between the fourth layer and the midpoint of the via.
The fourth antipad may also may be formed much as other antipads (e.g., patterned as a void in the fourth conductor in the fourth layer, and centered on the axis, coaxial with the other antipads). The fourth antipad should also be formed of the proper size to maintain the tapered antipad profile. With the fourth antipad in the fourth layer (between the second antipad and either of the first and third diameters), the fourth antipad diameter is greater than the second diameter and shorter than the first and third diameters. Like the fourth antipad, the fourth antipad diameter is centered on the axis such that the fourth antipad will be coaxial with the via and the other antipads.
In some embodiments, methods 800 include forming a fifth conductor having a fifth antipad in a fifth layer. The fifth conductor and fifth layer may be formed much as other conductors and layers, but should be included in the stack of layers during assembly such that the fifth layer is between the first and third layers, and the second layer is between the fourth and fifth layers.
The fifth antipad may also may be formed much as other antipads (e.g., patterned as a void in the fifth conductor in the fifth layer, and centered on the axis, coaxial with the other antipads). The fifth antipad should also be formed of the proper size to maintain the tapered antipad profile. With the fifth antipad in the fifth layer (between the second antipad and either of the first and third diameters), the fifth antipad diameter is greater than the second diameter and shorter than the first and third diameters. In some embodiments, the fifth antipad diameter is equal to the fourth antipad diameter. Like the fifth antipad, the fifth antipad diameter is centered on (and bisected by) the axis such that the fifth antipad will be coaxial with the via and the other antipads.
Methods 800 continue at operation 840 with forming a via on the axis and in at least the first, second, and third layers. The via may be formed by any suitable means. For example, the via may be formed by forming (e.g., boring or etching) a hole in or through (at least) the first, second, and third layers. In some embodiments, the hole is formed by drilling through the layers. In some embodiments, a laser bores the hole. A metal (such as copper, etc.) or another conductive material may be formed in the hole. The hole may be filled with the conductive material, or the conductive material may be deposited (e.g., plated) on a sidewall of the hole formed through the layers. The hole and subsequent via should be formed on the axis and so through the antipads, the voids in the conductors.
The via may go through additional layers, which may be between the first and third layers. The via may go through first, second, and third layers, as well as layers over and under the first, second, and third layers, e.g., to connect structures (such as traces) in the layers over and under the first, second, and third layers. There may be other layers that the via does not go through. For example, a via may connect structures (such as traces) in a middle and a top layer, a middle and a bottom layer, or two buried layers. In some embodiments, a via may be formed before the entire stack of layers is assembled.
Methods 800 continue with forming first and second connections to the via at operation 850. The connections may be formed by any suitable means and with any suitable materials. The connections may be by conductive traces to conductive pads centered on the via. In many embodiments, the connections are made by forming the via. For example, the layers may be formed and assembled with conductive traces and pads already on some layers when the via hole is formed through the layers between two pads. Conductive material (such as copper) that is plated (or otherwise deposited) in or on the hole may also then form connections (e.g., electrical connections) to the (two or more) pads and traces. In some embodiments, a pad is formed over the via and connecting the via to a conductive trace. Connections may be formed by other means.
The connections may be between the first and third layers or between the first or third layer and a layer under the first layer or over the third layer. For example, the first connection may be in or under the first layer, and the second connection may be in or over the third layer. The via hole may be formed before the layer are fully assembled. In some embodiments, the via hole may be formed as multiple holes in multiple layers before the holes and layers are aligned and assembled.
Methods 800 continue at operation 860 with coupling an IC die to the substrate. The substrate formed (or added to) by forming or assembling the layers may be an IC package substrate for mounting or supporting one or more IC dies. The tapered antipad profile may enable a higher density of I/O interconnects or of routing in the IC package. The IC die and package substrate may be coupled by any suitable means. In some embodiments, the die and substrate are direct bonded. In some embodiments, the die is soldered to the package substrate. In some embodiments, the tapered antipad profile enables the placement of the IC die directly over vias in the package substrate. In some such embodiments, the IC die is coupled over a via with a tapered antipad profile.
Also as shown, server machine 906 includes a battery and/or power supply 915 to provide power to devices 950, and to provide, in some embodiments, power delivery functions such as power regulation. Devices 950 may be deployed as part of a package-level integrated system 910. Integrated system 910 is further illustrated in the expanded view 920. In the exemplary embodiment, devices 950 (labeled “Memory/Processor”) includes at least one memory chip (e.g., random-access memory (RAM)), and/or at least one processor chip (e.g., a microprocessor, a multi-core microprocessor, or graphics processor, or the like) having the characteristics discussed herein. In an embodiment, device 950 is a microprocessor including a static RAM (SRAM) cache memory. As shown, device 950 may be an IC device having a via with a tapered antipad profile, as discussed herein. Device 950 may be further coupled to (e.g., communicatively coupled to) a board, an interposer, or a substrate 199 along with, one or more of a power management IC (PMIC) 930, RF (wireless) IC (RFIC) 925 including a wideband RF (wireless) transmitter and/or receiver (TX/RX) (e.g., including a digital baseband and an analog front end module further includes a power amplifier on a transmit path and a low noise amplifier on a receive path), and a controller 935 thereof. In some embodiments, RFIC 925, PMIC 930, controller 935, and device 950 include a via with a tapered antipad profile.
Computing device 1000 may include a processing device 1001 (e.g., one or more processing devices). As used herein, the term “processing device” or “processor” indicates a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory. Processing device 1001 may include a memory 1021, a communication device 1022, a refrigeration device 1023, a battery/power regulation device 1024, logic 1025, interconnects 1026 (i.e., optionally including redistribution layers (RDL) or metal-insulator-metal (MIM) devices), a heat regulation device 1027, and a hardware security device 1028.
Processing device 1001 may include one or more digital signal processors (DSPs), application-specific ICs (ASICs), central processing units (CPUs), graphics processing units (GPUs), cryptoprocessors (specialized processors that execute cryptographic algorithms within hardware), server processors, or any other suitable processing devices.
Computing device 1000 may include a memory 1002, which may itself include one or more memory devices such as volatile memory (e.g., dynamic random-access memory (DRAM)), nonvolatile memory (e.g., read-only memory (ROM)), flash memory, solid state memory, and/or a hard drive. In some embodiments, memory 1002 includes memory that shares a die with processing device 1001. This memory may be used as cache memory and may include embedded dynamic random-access memory (eDRAM) or spin transfer torque magnetic random-access memory (STT-MRAM).
Computing device 1000 may include a heat regulation/refrigeration device 1006. Heat regulation/refrigeration device 1006 may maintain processing device 1001 (and/or other components of computing device 1000) at a predetermined low temperature during operation.
In some embodiments, computing device 1000 may include a communication chip 1007 (e.g., one or more communication chips). For example, the communication chip 1007 may be configured for managing wireless communications for the transfer of data to and from computing device 1000. The term “wireless” and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a nonsolid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not.
Communication chip 1007 may implement any of a number of wireless standards or protocols, including but not limited to Institute for Electrical and Electronic Engineers (IEEE) standards including Wi-Fi (IEEE 802.11 family), IEEE 802.16 standards (e.g., IEEE 802.16-2005 Amendment), Long-Term Evolution (LTE) project along with any amendments, updates, and/or revisions (e.g., advanced LTE project, ultramobile broadband (UMB) project (also referred to as “3GPP2”), etc.). IEEE 802.16 compatible Broadband Wireless Access (BWA) networks are generally referred to as WiMAX networks, an acronym that stands for Worldwide Interoperability for Microwave Access, which is a certification mark for products that pass conformity and interoperability tests for the IEEE 802.16 standards. Communication chip 1007 may operate in accordance with a Global System for Mobile Communication (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE network. Communication chip 1007 may operate in accordance with Enhanced Data for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). Communication chip 1007 may operate in accordance with Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution-Data Optimized (EV-DO), and derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. Communication chip 1007 may operate in accordance with other wireless protocols in other embodiments. Computing device 1000 may include an antenna 1013 to facilitate wireless communications and/or to receive other wireless communications (such as AM or FM radio transmissions).
In some embodiments, communication chip 1007 may manage wired communications, such as electrical, optical, or any other suitable communication protocols (e.g., the Ethernet). As noted above, communication chip 1007 may include multiple communication chips. For instance, a first communication chip 1007 may be dedicated to shorter-range wireless communications such as Wi-Fi or Bluetooth, and a second communication chip 1007 may be dedicated to longer-range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, or others. In some embodiments, a first communication chip 1007 may be dedicated to wireless communications, and a second communication chip 1007 may be dedicated to wired communications.
Computing device 1000 may include battery/power circuitry 1008. Battery/power circuitry 1008 may include one or more energy storage devices (e.g., batteries or capacitors) and/or circuitry for coupling components of computing device 1000 to an energy source separate from computing device 1000 (e.g., AC line power).
Computing device 1000 may include a display device 1003 (or corresponding interface circuitry, as discussed above). Display device 1003 may include any visual indicators, such as a heads-up display, a computer monitor, a projector, a touchscreen display, a liquid crystal display (LCD), a light-emitting diode display, or a flat panel display, for example.
Computing device 1000 may include an audio output device 1004 (or corresponding interface circuitry, as discussed above). Audio output device 1004 may include any device that generates an audible indicator, such as speakers, headsets, or earbuds, for example.
Computing device 1000 may include an audio input device 1010 (or corresponding interface circuitry, as discussed above). Audio input device 1010 may include any device that generates a signal representative of a sound, such as microphones, microphone arrays, or digital instruments (e.g., instruments having a musical instrument digital interface (MIDI) output).
Computing device 1000 may include a GPS device 1009 (or corresponding interface circuitry, as discussed above). GPS device 1009 may be in communication with a satellite-based system and may receive a location of computing device 1000, as known in the art.
Computing device 1000 may include other output device 1005 (or corresponding interface circuitry, as discussed above). Examples of the other output device 1005 may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or an additional storage device.
Computing device 1000 may include other input device 1011 (or corresponding interface circuitry, as discussed above). Examples of the other input device 1011 may include an accelerometer, a gyroscope, a compass, an image capture device, a keyboard, a cursor control device such as a mouse, a stylus, a touchpad, a bar code reader, a Quick Response (QR) code reader, any sensor, or a radio frequency identification (RFID) reader.
Computing device 1000 may include a security interface device 1012. Security interface device 1012 may include any device that provides security measures for computing device 1000 such as intrusion detection, biometric validation, security encode or decode, access list management, malware detection, or spyware detection.
Computing device 1000, or a subset of its components, may have any appropriate form factor, such as a hand-held or mobile computing device (e.g., a cell phone, a smart phone, a mobile internet device, a music player, a tablet computer, a laptop computer, a netbook computer, a personal digital assistant (PDA), an ultramobile personal computer, etc.), a desktop computing device, a server or other networked computing component, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a vehicle control unit, a digital camera, a digital video recorder, or a wearable computing device.
The subject matter of the present description is not necessarily limited to specific applications illustrated in
The following examples pertain to further embodiments, and specifics in the examples may be used anywhere in one or more embodiments.
In one or more first embodiments, an apparatus includes a package substrate, including a plurality of metal layers and a plurality of voids, and an integrated circuit (IC) die on the package substrate, wherein the package substrate includes a first metal layer having a first void, the first void having a first radius, a second metal layer having a second void, the second metal layer over the first metal layer, the second void having a second radius smaller than the first radius, a third metal layer having a third void, the third metal layer over the second metal layer, the third void having a third radius larger than the second radius, and a metal via within, and extending through at least one of, the first, second, and third voids.
In one or more second embodiments, further to the first embodiments, a first connection to the metal via is in or under the first metal layer, and a second connection to the metal via is in or over the third metal layer.
In one or more third embodiments, further to the first or second embodiments, the metal via includes a first pad at the first connection or a second pad at the second connection.
In one or more fourth embodiments, further to the first through third embodiments, the first radius is substantially equal to the third radius.
In one or more fifth embodiments, further to the first through fourth embodiments, a fourth void at the metal via in a fourth metal layer has a fourth radius, the fourth metal layer is between the first and third metal layers, the first and third radii are greater than the fourth radius, and the fourth radius is greater than the second radius.
In one or more sixth embodiments, further to the first through fifth embodiments, a fifth void at the metal via in a fifth metal layer has a fifth radius, the fifth metal layer is between the first and third metal layers, the second metal layer is between the fourth and fifth metal layers, the first and third radii are greater than the fifth radius, and the fifth radius is greater than the second radius.
In one or more seventh embodiments, further to the first through sixth embodiments, a void profile around the metal via has a first slope adjacent an end of the metal via, the void profile has a second slope adjacent a midpoint of the metal via, and the second slope is greater than the first slope.
In one or more eighth embodiments, further to the first through seventh embodiments, the plurality of metal layers includes at least one pair of the metal layers above or below a midpoint of the metal via, each such pair includes a distal metal layer further from the midpoint and an intervening metal layer nearer to the midpoint, and the distal metal layer includes a distal void having a radius greater than a radius of an intervening void in the intervening metal layer.
In one or more ninth embodiments, further to the first through eighth embodiments, the metal via is a first metal via, the apparatus further including a second metal via, and a void at the second metal via overlaps an individual one of the voids at the first metal via.
In one or more tenth embodiments, further to the first through ninth embodiments, the metal via is a first metal via, and the plurality of voids is a first plurality of voids, the apparatus further including a second metal via through a second plurality of voids, wherein the first metal via is beneath the IC die, and individual ones of the second plurality of voids have substantially equal radii.
In one or more eleventh embodiments, an apparatus includes a first substrate, an IC package, including an IC die and a second substrate, the IC die coupled to a power supply through the first substrate, a stack of antipads in a stack of layers in the second substrate, and a via extending through one or more of the antipads, wherein the via is within or through a first antipad in a first layer, through a second antipad in a second layer over the first layer, and within or through a third antipad in a third layer over the second layer, and wherein a first diameter of the first antipad is greater than a second diameter of the second antipad, and the second diameter is smaller than a third diameter of the third antipad.
In one or more twelfth embodiments, further to the eleventh embodiments, the via includes a first connection in or under the first layer, a second connection in or over the third layer, a first pad at the first connection, and a second pad at the second connection, wherein the second diameter is equal to or greater than a diameter of the first or second pad.
In one or more thirteenth embodiments, further to the eleventh or twelfth embodiments, the first diameter is substantially equal to the third diameter.
In one or more fourteenth embodiments, further to the eleventh through thirteenth embodiments, the apparatus also includes fourth and fifth antipads in fourth and fifth layers, wherein the fourth and fifth antipads have a fourth diameter, the fourth layer is between the first and the second layers, the fifth layer is between the second and the third layers, the first and third diameters are greater than the fourth diameter, and the fourth diameter is greater than the second diameter.
In one or more fifteenth embodiments, a method includes forming a first conductor having a first antipad in a first layer of a substrate, the first antipad having a first diameter on an axis, forming a second conductor having a second antipad in a second layer, the second antipad having a second diameter on the axis, the first diameter greater than the second diameter, forming a third conductor having a third antipad in a third layer, the third antipad having a third diameter on the axis, wherein the second layer is between the first and third layers, and the third diameter is substantially equal to the first diameter, and forming a via on the axis and in at least the first, second, and third layers.
In one or more sixteenth embodiments, further to the fifteenth embodiments, the method also includes coupling an IC die to the substrate.
In one or more seventeenth embodiments, further to the fifteenth or sixteenth embodiments, coupling the IC die includes coupling the IC die over the via.
In one or more eighteenth embodiments, further to the fifteenth through seventeenth embodiments, the method also includes forming first and second connections to the via, wherein the first connection is in or under the first layer, and the second connection is in or over the third layer.
In one or more nineteenth embodiments, further to the fifteenth through eighteenth embodiments, the method also includes forming a fourth conductor having a fourth antipad in a fourth layer, the fourth antipad having a fourth diameter on the axis, wherein the fourth layer is between the first and third layers, the second layer is at a midpoint of the via or between the fourth layer and the midpoint of the via, the first diameter is greater than the fourth diameter, and the fourth diameter is greater than the second diameter.
In one or more twentieth embodiments, further to the fifteenth through nineteenth embodiments, the method also includes forming a fifth conductor having a fifth antipad in a fifth layer, the fifth antipad having a fifth diameter on the axis, wherein the fifth layer is between the first and third layers, the fifth diameter is substantially equal to the fourth diameter, and the second layer is between the fourth layer and the fifth layer.
The disclosure can be practiced with modification and alteration, and the scope of the appended claims is not limited to the embodiments so described. For example, the above embodiments may include specific combinations of features. However, the above embodiments are not limiting in this regard and, in various implementations, the above embodiments may include the undertaking only a subset of such features, undertaking a different order of such features, undertaking a different combination of such features, and/or undertaking additional features than those features explicitly listed. The scope of the patent rights should, therefore, be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled.
