Claims
- 1. A method of manufacturing a semiconductor die package comprising:forming a housing defining a cavity for holding at least one semiconductor die, said housing including a plurality of insulative side walls and an end plate joined to said side walls, wherein the thickness of the end plate is greater than the distance that the side walls extend away from the end plate; inserting a plurality of electrically conductive leads extending through at least one of said side walls, each of said leads including an internal lead section extending within the cavity and an external lead section extending externally of said at least one side wall; and providing a cover plate joined to said side walls opposite said end plate, wherein said cover plate includes an aperture formed therethrough which exposes to the environment a sufficient portion of said at least one semiconductor die such that pressing a human digit into said aperture results in contact between said human digit and said at least one semiconductor die.
- 2. A method of manufacturing a semiconductor die package according to claim 1, wherein the side walls and the end plate are molded together to form a one-piece structure.
- 3. A method of manufacturing a semiconductor die package according to claim 1, wherein said cover plate is made of a conductive material.
- 4. A method of manufacturing a semiconductor die package according to claim 3, wherein said cover plate forms part of an electrostatic discharge path.
- 5. A method of manufacturing a semiconductor die package according to claim 4, wherein said cover plate and the internal lead section of at least one of said leads are electrically connected by a conductive material.
- 6. A method of manufacturing a semiconductor die package according to claim 1, wherein said cover plate has an outer circumference greater than the outer circumference of the at least one semiconductor die.
- 7. A method of manufacturing a semiconductor die package comprising:forming a housing defining a cavity for holding a semiconductor die, the housing including a plurality of insulative side walls and an end plate joined to said side walls, wherein the housing includes an aperture formed therethrough for exposing a majority of a surface of the semiconductor die to ambient and an electrically conductive cover plate that defines the aperture; inserting a plurality of electrically conductive leads extending through at least one of said side walls, each of said leads including an internal lead section extending within the cavity and an external lead section extending externally of said at least one side wall; and providing a cap that fits over said housing to close the aperture from ambient, the cap being removably secured to the housing.
- 8. A method of manufacturing a semiconductor die package according to claim 7, wherein said leads are L-shaped.
- 9. A method of manufacturing a semiconductor die package according to claim 7, wherein said cover plate forms part of an electrostatic discharge path.
- 10. A method of manufacturing a semiconductor die package according to claim 7, wherein the cap includes a plurality of clips for detachably securing the cap to the housing.
- 11. A method of manufacturing a semiconductor die package according to claim 7, wherein the cap is made from stainless steel.
RELATED APPLICATIONS
This is a divisional of application Ser. No. 09/950,702 filed on Sep. 13, 2001, which is a divisional of application Ser. No. 09/218,180, filed on Dec. 22, 1998, now U.S. Pat. No. 6,307,258.
This application is related in subject matter to U.S. application Ser. No. 08/208,586, entitled “Prefabricated Semiconductor Chip Carrier”, filed Mar. 11, 1994, and expressly incorporated by reference herein; U.S. application Ser. No. 08/465,146, entitled “Method of Manufacturing A Semiconductor Chip Carrier”, filed Jun. 5, 1995, and expressly incorporated by reference herein; U.S. application Ser. No. 08/487,103, entitled “Semiconductor Die Carrier Having Double-Sided Die Attach Plate”, filed Jun. 7, 1995, and expressly incorporated by reference herein; U.S. application Ser. No. 08/902,032, entitled “Semiconductor Die Carrier Having A Dielectric Epoxy Between Adjacent Leads”, filed Jul. 29, 1997, which is a continuation of U.S. application Ser. No. 08/487,100, filed Jun. 7, 1995, and expressly incorporated by reference herein; U.S. application Ser. No. 08/482,00, entitled “Low Profile Semiconductor Die Carrier”, filed Jun. 7, 1995, and expressly incorporated by reference herein; U.S. patent application Ser. No. 08/970,379, entitled “Multi-Chip Module Having Interconnect Dies”, filed Nov. 15, 1997 and expressly incorporated by reference herein; and U.S. patent application Ser. No. 09/033,480, entitled “Semiconductor Die Package For Mounting In Horizontal And Upright Configurations”, filed Mar. 3, 1998 and expressly incorporated by reference herein.
US Referenced Citations (22)
Foreign Referenced Citations (7)
Number |
Date |
Country |
0 155 044 |
Sep 1985 |
EP |
0786745 |
Jul 1997 |
EP |
0789334 |
Aug 1997 |
EP |
61082447 |
Apr 1986 |
JP |
1074795 |
Mar 1989 |
JP |
2301182 |
Dec 1990 |
JP |
5226803 |
Sep 1993 |
JP |
Non-Patent Literature Citations (2)
Entry |
Intel Corporation, Packaging. |
Rao R. Tummala, Microelectronics Packaging Handbook, Foreword, Chapters 11 (Package-To-Board Interconnections, and 12 (Printed-Circuit Board Packaging), New York, Van Nostrand Reinhold, ©1989. |