OVERLAY ALIGNMENT MARK AND ALIGNMENT METHOD FOR THE FABRICATION OF TRENCH-CAPACITOR DRAM DEVICES

Abstract

A small-size (w<0.5 micrometers) alignment mark in combination with a “k1 process” is proposed, which is particularly suited for the fabrication of trench-capacitor DRAM devices which requires highly accurate AA-DT and GC-DT overlay alignment. The “k1 process” is utilized to etch away polysilicon studded in the alignment mark trenches and to refresh the trench profile, thereby improving overlay alignment accuracy and precision.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

The invention can be fully understood by reading the following detailed description of the preferred embodiments, with reference made to the accompanying drawings as follows:

FIGS. 1-7 are schematic, cross-sectional diagrams illustrating the alignment method utilized in the fabrication of a deep-trench capacitor dynamic random access memory (DRAM) device in accordance with one preferred exemplary embodiment of this invention;

FIG. 8 depicts a schematic top view of the previous-layer alignment pattern in accordance with one preferred exemplary embodiment of this invention;

FIG. 9 depicts a schematic top view of the overlay mark in accordance with one preferred exemplary embodiment of this invention; and

FIG. 10 is a flow chart demonstrating the front-end process for fabricating a deep trench capacitor DRAM device in accordance with the preferred embodiment of this invention.

Claims

1. A method for fabricating a microelectronic device, comprising: providing a semiconductor substrate comprising thereon a device region and an alignment-mark forming region;forming a trench in the semiconductor substrate within the device region, and simultaneously, forming a previous-layer alignment pattern in the semiconductor substrate within the alignment-mark forming region, wherein the previous-layer alignment pattern comprises a plurality of trench lines;forming a capacitor structure within the trench comprising at least a conductive layer in the trench, wherein the trench lines also comprises the conductive layer;forming a first photo resist layer over the semiconductor substrate and performing an exposure process to form an opening in the first photo resist layer, wherein the opening only exposes the previous-layer alignment pattern in the alignment-mark forming region;using the first photo resist layer as a mask, performing an removing process to remove the conductive layer inside the trench lines;removing the first photo resist layer;forming a second photo resist layer over the semiconductor substrate; andpatterning the second photo resist layer, and simultaneously, forming an existing-layer photo resist pattern within the alignment-mark forming region, wherein the existing-layer photo resist pattern and the previous-layer alignment pattern together form an overlay mark.

2. The method according to claim 1 wherein before forming the second photo resist layer on the semiconductor substrate, the method further comprises the following step: depositing a planarization layer on the semiconductor substrate.

3. The method according to claim 2 wherein the planarization layer comprises boron-doped silicate glass (BSG), BPSG, TEOS oxide or combinations thereof.

4. The method according to claim 1 wherein after the removing process, the depth of the trench lines ranges between 3000 angstroms and 8000 angstroms.

5. The method according to claim 1 wherein the line width of each trench line ranges between 0.2 micrometer and 0.3 micrometer.

6. The method according to claim 1 wherein each of the trench lines has a line width that is less than or equal to 0.5 micrometer.

7. The method according to claim 1 further comprising using the overlay mark to assess AA-DT (active area-deep trench) overlay accuracy.

8. A method for fabricating a microelectronic device, comprising: providing a substrate comprising thereon a device region and an mark forming region;forming a trench in the substrate within the device region, and simultaneously, forming a first pattern structure in the substrate within the mark forming region, wherein the first pattern structure comprises a plurality of trench lines;forming at least a material in the trench and simultaneously forming the material in the trench lines;forming a first patterning layer over the substrate comprising an opening, wherein the opening exposes the first pattern structure in the mark forming region;removing at least a part of the material inside the trench lines; andremoving the first patterning layer

9. The method according to claim 8 wherein before forming the second patterning layer on the semiconductor substrate, the method further comprises the following step: depositing a planarization layer on the semiconductor substrate.

10. The method according to claim 9 wherein the planarization layer comprises boron-doped silicate glass (BSG), BPSG, TEOS oxide or combinations thereof.

11. The method according to claim 8 wherein after the removing process, the depth of the trench lines ranges between 3000 angstroms and 8000 angstroms.

12. The method according to claim 8 wherein the material inside the trench lines is completely removed.

13. The method according to claim 8 wherein the material inside the trench lines is partially removed.