Claims
- 1. A method of preparing a film thickness standard on an integrated circuit substrate, comprising:successively forming oxide film layers upon one another on the integrated circuit substrate until a continuous film thickness standard is formed having a thickness greater than 1 micron, wherein each of the oxide film layers has a same thickness.
- 2. The method according to claim 1, wherein the continuous film thickness standard is substantially free of uniformity variations such that deviation of the thickness of the continuous film thickness standard from a desired value is less than or equal to 0.3% over the entire continuous film standard.
- 3. The method according to claim 2, wherein the continuous film thickness standard is substantially free of uniformity variations such that deviation of the thickness of the continuous film thickness standard from a desired value is less than or equal to 0.2% over the entire continuous film standard.
- 4. The method according to claim 1, wherein the continuous film thickness standard is substantially free of uniformity variations such that deviation of a refraction angle from a theoretical value for the continuous film standard is less than or equal to 0.2%.
- 5. The method according to claim 1, wherein the step of successively forming each of the oxide film layers comprises successively forming each of the oxide film layers by a Plasma Enhanced Oxidation process.
- 6. The method according to claim 5, wherein the step of successively forming each of the oxide film layers comprises successively forming each of the oxide film layers under constant Plasma Enhanced Oxidation process conditions by supplying 95 liter/min. of SiH4 and 1800 liter/min. of N2O gas.
- 7. The method according to claim 6, wherein the constant Plasma Enhanced Oxidation process conditions take place at 400° C.
- 8. The method according to claim 7, wherein the same thickness of each of the oxide film layers is 4000 Å.
- 9. The method according to claim 6, wherein the constant Plasma Enhanced Oxidation process conditions take place at 2.9 Torr.
Priority Claims (1)
Number |
Date |
Country |
Kind |
97-27093 |
Jun 1997 |
KR |
|
Parent Case Info
This application is a divisional of U.S. application Ser. No. 09/064,800, filed Apr. 22, 1998, now U.S. Pat. No. 6,008,503.
US Referenced Citations (7)
Non-Patent Literature Citations (2)
Entry |
Candela et al., SPIE vol. 661, Optical Testing and Metrology, pp 402-407, 1986 (no month).* |
VLSI Standards Incorporated, 1996 Product Guide (No month). |