Patent Application
20060001134
1. Field of the Invention
The invention relates to a package structure, and more particularly, to a package structure capable of achieving greater reliability and production yield.
2. Description of the Prior Art
In the semiconductor industry, the production of integrated circuits is generally divided into two stages: integrated circuit manufacturing and integrated circuit packaging. The manufacturing of integrated circuit includes processes such as wafer manufacturing, circuit design, photomask manufacturing, and wafer dicing. Integrated circuit packaging on the other hand, includes processes such as wire bonding or flip chip assembly for electrically connecting a circuit chip to a substrate or a lead frame.
As the demand of smaller, more functional and complex PDAs, cellular phones, CPUs, and memory modules increases each day, the development of semiconductors also moves toward a direction of higher density packaging. Among many popular package structures, a flip chip (FC) structure with the characteristics of rapid cooling, low inductance, multi-terminal, and small size has been used most commonly in favor of others. In general, a flip chip package involves formation of a plurality of bumps on a chip and the addition of a layer of solder paste on the lead frame. The chip is then attached to the lead frame by melting the paste via a reflow process. Essentially, this type of package structure has already been disclosed in U.S. Pat. No. 6,661,087. Nevertheless, the reflow process often causes the melting-state chip bumps and the solder paste to travel on the lead frame, which eventually causes the chip to move away from its original position and result in problems such as product failure or low production yields.
In the recent history of integrated circuit packaging, passive devices (i.e. electrical resistors, capacitors, or inductors) have often been used for applications requiring high frequency or various other electrical properties. In the past, passive devices have generally been placed on the surface of printed circuit boards (PCBs). However, in order to reduce the space occupied on the PCB, most passive devices today are integrated into the chip. Eventually, a system in a package (SiP) was formed to provide a high efficiency, low cost, and small size package design for the market.
In the SiP design, the solder paste is often used as a linking medium between the passive device and the lead frame. After being processed by a reflow process via high temperature, the melting solder paste readily bonds the passive device and the lead frame together. Nevertheless, the reflow process often causes the solder paste to travel on the lead frame and the passive device to shift from its original position and results in problems such as product failure or low production yield. Consequently, it becomes a critical matter for the package industry to actively look for a package structure design that is able to effectively prevent the solder paste from moving on the lead frame.
It is therefore an objective of the claimed invention to provide a package structure for solving the problems stated previously.
The present invention relates to a package structure. The package structure includes a lead frame having a plurality of leads, each of which includes a first recession, at least a first device, and a plurality of solder joints respectively positioned in the first recessions for connecting the first device to the lead frame.
As the present invention includes a plurality of lead frame recessions for fixing each solder joints in place, the joints are likely to remain in its original position during the melting state of a reflow process, thereby significantly increasing the overall yield and reliability of the package structure.
These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.
Please refer to
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Thereinafter, the device 18 is connected to the lead frame 12 to place each of the bumps 20 within the corresponding recession 16a. Next, a reflow process is performed for melting the solder paste 22b and forming the solder joint 22 as shown in
As noted previously, the metal lead frame 12 of the present invention includes a plurality of recessions 16a for fixing each bump 20 in place, preventing bump 20 and solder paste 22b from shifting positions during the reflow process, maintaining the electrical performance of the semiconductor device 18, and ultimately increasing the overall yield and reliability of the package structure 10.
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In essence, the metal lead frame 32 includes a plurality of recessions 38a for preventing the melting state solder joint 50 from shifting positions during a reflow process, thereby increasing the overall yield and reliability of the package structure 30. The manufacturing technique of the package structure shown in
In contrast to prior art technology, the lead frame 12 and 32 of present invention includes the recessions 16a and 38a, hence the solder joint 22 and 50 can be well maintained in its original position during a reflow process, thereby increasing the overall yield and reliability of the package structure 10 and 30.
Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 093119793 | Jun 2004 | TW | national |
