Patent Application
20160323995
The present invention relates to the field of PCB technologies, and in particular, to a PCB processing method and a PCB.
With the increasing of a user data traffic volume, assembling printed circuit boards (abbreviated as PCB) and connectors is widely used in a communication system to implement the transmission of inter-board signals. The capacity of a typical switching system reaches 10 T, and up to hundreds of connectors are used. Very high requirements for the density of the connectors and the rate of single channels are proposed because very high communication capacity needs to be met and so many single boards and connectors need to be installed in a cabinet having a limited space. Currently, the single channel rate of the connectors has been raised more than 25 Gbps, and the minimum distance between connector wafers is only 1.85 mm. The density of the connectors has to be reduced to further improve the single channel rate of the connectors. The density and rate of the connectors are actually contradictory. Connector manufacturers make great efforts in the design of high-rate and high-density connectors. At present, a through hole is generally designed on a PCB for crimping the connectors. As a result, the wiring space of the PCB is limited by the space between wafers. During the research of the present invention, inventors found that the existing art at least has the following problems. After a connector type is determined, the space for layout between wafers on the PCB is limited. Due to through hole crimping, the deeper the backdrilling is, the larger the depth tolerance of a backdrilled hole is, and the poorer the control of a stub is.
In view of the aforementioned problems, the present invention is proposed to provide a PCB processing method and a PCB for overcoming the aforementioned problems or at least in part solving the aforementioned problems.
The present invention provides a PCB processing method, including: respectively carrying out lamination processing on a plurality of PCB daughter boards constituting a PCB according to PCB design requirements, and drilling and electroplating a top-most PCB daughter board of the PCB to form a via hole; laminating the plurality of PCB daughter boards together to form the PCB, and drilling and electroplating the formed PCB to form a through hole for mounting a connector, wherein a depth of the blind hole is greater than or equal to a length of a signal pin of the connector.
Preferably, after drilling and electroplating the top-most PCB daughter board of the PCB to form a via hole, the method further includes: backdrilling the via hole that needs to be backdrilled.
Preferably, the blind hole has a metallized part after backdrilling, and a length of the metallized part is greater than or equal to that of the signal pin of the connector.
Preferably, drilling and electroplating the formed PCB to form a through hole for mounting the connector includes: drilling and electroplating the formed PCB at preset intervals to form multiple through holes for mounting connectors.
Preferably, after drilling and electroplating the formed PCB to form a through hole for mounting the connector, the method further includes: backdrilling the through hole that needs to be backdrilled.
Preferably, the method further includes: determining a position of the through hole and of the blind hole according to wiring pattern of the PCB.
Preferably, the top-most PCB daughter board is formed by laminating a core board and a dielectric.
Preferably, the bottom-most PCB daughter board of the plurality of PCB daughter boards constituting the PCB is formed by directly processing a core board or is formed by the core board and a dielectric.
The present invention further provides a PCB fabricated by the foregoing printed circuit board PCB processing method, the PCB is formed by laminating multilayer PCB daughter boards, and the PCB is provided with a blind hole and a through hole for mounting a connector.
Preferably, the blind hole and the through hole are backdrilled.
Beneficial effects of the present invention are as below:
In the case where the density of the connector is constant, the blind hole is formed by twice or more laminations, a space between wafers of the lower layer of PCBs may be doubled, and the space for layout between wafers may be doubled.
The foregoing description is merely a summarization of the technical schemes of the present invention, and may be implemented in accordance with the contents of the specification to more clearly understand the technological means of the present invention. The embodiments of the present invention are given to make the foregoing and other objectives, features and advantages of the present invention more apparent.
Various other advantages and benefits will become apparent to those of ordinary skill in the art by reading the detailed description of the following preferred embodiments. The drawings are merely intended for showing preferred embodiments, but are not deemed to limit the present invention. Furthermore, in the whole drawings, the same reference marks denote the same parts. In the figures:
The following will describe in more detail the exemplary embodiments of the present disclosure with reference to the drawings. Although the drawings display the exemplary embodiments of the present disclosure, it should be understood that the present disclosure may be implemented in various forms but not limited by the embodiments set forth herein. Instead, these embodiments are provided to more thoroughly understand the present disclosure, and completely convey the scope of the present disclosure to those skilled in the art.
As mentioned above, in the existing art, connectors are mounted by crimping, and all crimping holes are designed as through holes. This manner has a disadvantage that the distance between two wafers of the connector is quite small so that the space of connector for layout is very small. The density of the connectors has to be reduced if the space for layout is increased. In order to solve the aforementioned problem, the embodiments of the present invention provide a printed circuit board PCB processing method and a PCB, which may enable the space for layout between wafers to be doubled without reducing the density of the connector. Furthermore, the stub in the crimping of the blind hole may be effectively reduced by adopting multiple backdrilling before crimping. The following further describes in detail the present invention with reference to the drawings and the embodiments. It should be understood that the embodiments described herein are merely used to explain the present invention, and are not intended to limit the present invention.
Method Embodiments
According to the embodiments of the present invention, a PCB processing method is provided.
Step 101: lamination processing is respectively carried out on a plurality of PCB daughter boards constituting a PCB according to PCB design requirements, and a top-most PCB daughter board of the PCB is drilled and electroplated to form a via hole, where the top-most PCB daughter board is formed by laminating a core board and a dielectric. A bottom-most PCB daughter board of the plurality of PCB daughter boards constituting the PCB is formed by directly processing a core board or is formed by laminating the core board and a dielectric.
After the via hole is formed by drilling and electroplating the top-most PCB daughter board of the PCB, the via hole that needs to be backdrilled may be backdrilled. The blind hole has a metallized part after backdrilling, and a length of the metallized part is greater than or equal to that of the signal pin of the connector.
Step 102: the plurality of PCB daughter boards are laminated together to form the PCB, and the formed PCB is drilled and electroplated to form a through hole for mounting the connector, wherein a blind hole for mounting a connector is formed by the via hole, and a depth of the blind hole is greater than or equal to a length of the signal pin of the connector.
In Step 102, the formed PCB may be drilled and electroplated at preset intervals to form multiple through holes for mounting connectors. And the through hole that needs to be backdrilled may be backdrilled.
In this embodiment of the present invention, a position of the through hole and of the blind hole may be determined according to the wiring pattern of the PCB. For example, preferably, in this embodiment of the present invention, the connector may be crimped by using the blind hole every other wafer.
As mentioned above, the embodiments of the present invention propose a PCB processing method for connector crimping. The blind hole is formed by twice or more laminations. And where in terms of design and processing, it is needed to guarantee that the depth of the blind hole is greater than the length of the signal pin of the connector, so as to guarantee that the connector may be inserted from the blind hole by crimping. A crimping effect after processing is as shown in
The following makes a detailed description of the specific processing method of the embodiments of the present invention with reference to drawings and by taking two PCB daughter boards, i.e. a PCB daughter board of a upper layer and a PCB daughter board of a lower layer, as an example:
Step 201: the PCB daughter board of upper layer is processed first according to requirements, the PCB daughter board of lower layer part is processed by directly using a core board, or is processed by multilayer core boards and prepreg PP, where core boards are formed by laminating copper foils the dielectric (PP), as shown in
Step 202: the PCB daughter board of upper layer is drilled and electroplated, as shown in
Step 203: the via hole needed in the PCB daughter board of upper layer is backdrilled, as shown in
Step 204: the PCB daughter board of upper layer and PCB daughter board of lower layer are laminated together, as shown in
Step 205: the position of the crimping hole of the connector is drilled and electroplated, as shown in
Step 206: the through hole that needs backdrilling is backdrilled, as shown in
After the foregoing processing, the connector may be assembled, and the schematic diagram after assembly is as shown in
In conclusion, through the technical schemes of the embodiments of the present invention, in the case where the density of the connector is constant, wafers between lower layer of PCB may be doubled via reasonably designing the crimping of PCB and connectors, namely by means of twice or more laminations, so that the wiring space between wafers may be doubled. In addition, according to the technical schemes of the embodiments of the present invention, the blind hole is backdrilled before multiple laminating, which may effectively reduce the length of the stub.
Device Embodiments
According to the embodiments of the present invention, there is provided a PCB fabricated by the foregoing PCB processing method, as shown in
In conclusion, through the technical schemes of the embodiments of the present invention, in the case where the density of the connector is constant, wafers between lower layer of PCB may be doubled via considerable designing the crimping of PCB and connectors, namely by means of twice or more laminations, so that the wiring space between wafers may be doubled. In addition, according to the technical schemes of the embodiments of the present invention, the blind hole is backdrilled before multiple laminating, which may effectively reduce the length of the stub.
Apparently, a person skilled in the art may make various modifications and variations on the present invention without departing from the spirit and scope of the present invention. In this way, if the modifications and variations of the present invention fall within the scope of the claims of the present invention and equivalent technologies thereof, the present invention also intends to include the modifications and variations.
In the embodiments of the present invention, in the case where the density of the connector is constant, wafers between lower layer of PCB may be doubled via forming the blind hole by twice or more laminations, so that the wring space between wafers may be doubled. Furthermore, the stub in the crimping of the blind hole may be effectively reduced by backdrilling before multiple laminating. Therefore, the present invention has industrial applicability
| Number | Date | Country | Kind |
|---|---|---|---|
| 201310739302.6 | Dec 2013 | CN | national |
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/CN2014/078052 | 5/21/2014 | WO | 00 |
