Patent Application
20240315056
This application claims priority to and the benefit of Chinese Patent Application 202310270309.1, filed on Mar. 15, 2023, which is hereby incorporated by reference in its entirety.
Implementations of the present application relate to the technical field of semiconductors, and in particular to a peripheral circuit assembly, a memory system and a fabrication method of the memory system.
As feature sizes of semiconductor manufacturing processes are increasingly getting smaller, the storage density of memory devices is increasingly getting higher, and a three-dimensional memory emerges as the times require. In order to increase the storage capacity of the three-dimensional memory, the number of stacked layers of a memory array chip of the three-dimensional memory is continuously increasing. In the case that the storage capacity is fixed, as the number of stacked layers of the memory array chip increases, the size of the memory array chip decreases, and a complementary metal oxide semiconductor (CMOS) in bonding connection with the memory array chip is also reduced in size simultaneously, but this affects the formation of peripheral devices.
Other features, purposes and advantages of the present application will become more apparent by reading the detailed description of non-limitative examples made by reference to the following figures. The figures are used for a better understanding of the scheme, but do not constitute limitations on the present application. In the figures:
Optimization of the formation of the CMOS of different peripheral devices is one of the urgent technical problems to be solved.
In order to better understand the present application, various aspects of the present application will be described in more detail with reference to the figures. It is understood that these detailed descriptions are only descriptions of example implementations of the present application, and are not limitations on the scope of the present application in any manner. Like reference numbers denote like elements throughout the specification. The expression “and/or” includes any or all combinations of one or more of associated listed items.
It is noted that, in the specification, the expressions, such as first, second, third and the like, are only used to distinguish one feature from another feature, instead of representing any limitation on the features, particularly instead of representing any sequential order.
For ease of description, the thicknesses, dimensions and shapes of components have been slightly adjusted in the figures. The figures are merely examples and are not drawn to scale strictly. As used herein, terms “approximately”, “about”, and similar terms, are used to represent approximation, instead of representing a degree, and are intended to describe an inherent deviation in a measured value or a calculated value as recognized by those of ordinary skill in the art.
It is also understood that expressions, such as “comprise”, “comprising”, “have”, “include”, and/or “including”, etc., are open-ended expressions, rather than close-ended expressions in the specification. They indicate the existence of the stated features, elements and/or components, but do not exclude the existence of one or more other features, elements, components and/or combinations thereof. Moreover, the expression, such as “at least one of . . . ”, appearing before a list of listed features, modifies the whole list of features, rather than an individual element therein. Furthermore, “may” is used to represent “one or more implementations of the present application” when the implementations of the present application are described. Moreover, the term “example” is intended to refer to an example or an example illustration.
Unless otherwise defined, all phrases (including engineering terms and technical terms) as used herein have the same meanings as those generally understood by those of ordinary skill in the art to which the present application pertains. It is further understood that terms as defined in common dictionaries should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art, and should not be interpreted in an idealized or overly formal sense unless otherwise stated expressly in the present application.
It should be noted that, examples and features in the examples in the present application may be combined with one another in the case of no conflicts. In addition, unless otherwise defined expressly or conflicting with the context, specific operations included in a method as set forth in the present application are not necessarily limited to an order as set forth but may be carried out in any order or in parallel. The present application will be described in detail below by reference to the figures and in conjunction with the examples.
Furthermore, in the present application, the term “layer” refers to a material portion including a region with a thickness. A layer may extend over the entirety of an underlying or overlying structure, or may have an extent less than the extent of the underlying or overlying structure. Furthermore, a layer may be a region of a homogeneous or inhomogeneous continuous structure that has a thickness less than the thickness of a continuous structure. A layer may extend horizontally, vertically, and/or along an inclined surface. A layer may include multiple sub-layers. In addition, “connection” or “joining”, when used in the present application, may represent direct contact or indirect contact between respective components, unless otherwise expressly defined or derived from the context.
In the relevant art, as the number of stacked layers of the three-dimensional memory continues to increase, the number of peripheral devices such as high voltage (HV) devices and low low voltage (LLV) devices on the CMOS also increases, and there may be a situation that the area is not enough on the CMOS. In addition, the manufacturing processes and thermal budgets of the high voltage device and the low low voltage device are different. The low low voltage device is suitable for small-scale manufacturing processes, while the high voltage device can employ lower-cost large-scale manufacturing processes, and the corresponding thermal budget of the low low voltage device is smaller than that of the high voltage device. However, since the high voltage device and the low low voltage device are formed on the same CMOS at the same time in the relevant art, the high voltage device needs to employ the same small-scale manufacturing process as the low low voltage device, and meanwhile an additional thermal budget is required to be introduced due to the presence of the high voltage device, which increases the process cost, easily results in inconsistent polysilicon heights of different devices, and is unfavorable to the performance of the low low voltage device that is sensitive to the thermal budget. In addition, in the relevant art, the controller is usually formed on a separate wafer, and is connected with the memory array chip through a circuit wiring, which not only increases the cost, but also reduces the integration and speed of the three-dimensional memory.
Based on this, in order to solve at least part of the above-mentioned problems, the implementations of the present application provide a peripheral circuit assembly.
Since the low low voltage device and the high voltage device are located on different peripheral circuit chips in the implementation of the present application, even if the number of low low voltage devices and high voltage devices increases as the number of stacked layers of the memory array chip 100 of the three-dimensional memory increases, on the premise of matching the size of the memory array chip 100, the areas of the first peripheral circuit chip 200 and the second peripheral circuit chip 300 can also meet the demands for forming the low low voltage device and the high voltage device respectively, and the high voltage device and the low low voltage device no longer affect each other. In other words, the manufacturing process of the high voltage device is no longer affected by that of the low low voltage device. The high voltage device can employ a large-scale manufacturing process, which not only reduces the process cost, but also enables the polysilicon heights of the high voltage device and the low low voltage device to be unified, and the ion implantation of NP (N plus, N-type heavily doped)/PP (P plus, P-type heavily doped) of the high voltage device and the low voltage device can also be compatible. At the same time, the thermal budget of the low voltage device is no longer affected by high voltage device, and there is no need to introduce an additional thermal budget during the fabrication of the low voltage device. In addition, since the first peripheral circuit chip 200 or the second peripheral circuit chip 300 further includes a controller in the implementation of the present application, in other words, the controller and the high voltage device or the low low voltage device are integrated on the same peripheral circuit chip in the implementation of the present application, not only can the cost of forming the controller on a separate wafer be saved, but also the circuit wiring between chips can be reduced, that is, the circuit wiring between the chip where the controller is located and other chips can be saved, thereby improving the speed and integration.
It is to be noted that, the high voltage device may include, but is not limited to, at least one of a row decoder, a column decoder, a word line driver, and a bit line driver; and the low low voltage device may include, but is not limited to, an I/O circuit. The operating voltage of the high voltage device is generally greater than 3.3 V, such as 5 V-30 V. As an example, the operating voltage of the high voltage device may be 5 V, 10 V. 15 V. 20 V, 25 V or 30 V. Of course, it may also be any value between any two of the above-mentioned voltage values. The operating voltage of the low low voltage device is generally lower than 1.3 V, such as 0.9 V-1.2 V. As an example, the operating voltage of the low low voltage device may be 0.9 V. 0.95 V. 1 V. 1.05 V. 1.1 V. 1.15 V or 1.2 V. Of course, it may also be any value between any two of the above-mentioned voltage values. Those skilled in the art should understand that the above description of the operating voltage ranges of the high voltage device and the low low voltage device is for better understanding of the present solution, and does not constitute a limitation on the present application.
In some examples, the high voltage device, the low low voltage device and the controller may include, but are not limited to, at least one of a transistor, a diode, a resistor, an inductor and a capacitor.
As an example, the low low voltage device includes a transistor. In order to distinguish it from transistors of other peripheral devices, the transistor of the low low voltage device is referred to as a first transistor 290 hereinafter. As shown in
In some examples, the first transistor 290 may include a first source 291, a first drain 292 and a first gate structure 293, wherein the first drain 292 and the first source 291 are formed in the first substrate 210; the first gate structure 293 is located on a side of the first substrate 210 and is between the first drain 292 and the first source 291; the first gate structure 293 includes a gate insulation layer and a gate conductive layer; and the gate conductive layer is located on a side of the gate insulation layer far away from the first substrate 210. If the first transistor 290 is an N-type transistor, the first drain 292 and the first source 291 are formed in the first substrate 210 using an N-type dopant such as phosphorus (P), arsenic (As), and antimony (Sb), etc.; and if the first transistor 290 is a P-type transistor, the first drain 292 and the first source 291 are formed in the first substrate 210 using a P-type dopant such as boron (B), etc. The material of the gate insulation layer includes an insulating material such as silicon oxide, silicon nitride, silicon oxynitride, hafnium oxide, zirconium oxide, aluminum oxide, magnesium oxide, and tantalum oxide, etc., and the material of the gate conductive layer includes polysilicon, a conductive metal or a conductive alloy. As an example, the material of the gate conductive layer includes at least one of tungsten (W), titanium nitride (TiN), copper (Cu) and silver (Ag). The gate insulation layer and the gate conductive layer may be formed on a side of the first substrate 210 through a thin film deposition process.
In some examples, a low low voltage well region 294 formed by doping with a lower concentration of an N-type or P-type dopant is further formed in a partial region of the first substrate 210, and the first drain 292 and the first source 291 are formed in the low low voltage well region 294. If the first transistor 290 is an N-type transistor, a P-type doped well, i.e., a low low voltage P well, may be formed in the first substrate 210 using a P-type dopant such as boron (B), etc.; and if the first transistor 290 is a P-type transistor, an N-type doped well, i.e., a low low voltage N well, may be formed in the first substrate 210 using an N-type dopant such as phosphorus (P), arsenic (As) and antimony (Sb), etc. Each of the above-mentioned well regions may be formed in the first substrate 210 by an ion implantation or diffusion process. It is to be noted that the controller may also include a transistor, and a first trench isolation structure 230 corresponding to the transistor of the controller is formed on the first substrate 210. For case of description, the transistor of the controller is referred to as a fourth transistor 295 hereinafter, and the formation method of the fourth transistor 295 is similar to that of the first transistor 290 and is not repeated here.
Similarly, the high voltage device may also include a transistor. In order to distinguish it from the transistors of other peripheral devices such as the low low voltage device, the transistor of the high voltage device is referred to as a second transistor 350 hereinafter. As shown in
In some examples, the first peripheral circuit chip 200 and/or the second peripheral circuit chip 300 further includes a low voltage device. In other words, the first peripheral circuit chip 200 or the second peripheral circuit chip 300 includes a low voltage device. Alternatively, the first peripheral circuit chip 200 and the second peripheral circuit chip 300 include low voltage devices at the same time.
As an example, the first peripheral circuit chip 200 includes a low low voltage device, a controller and at least one low voltage device, and the second peripheral circuit chip 300 includes a high voltage device and at least one other low voltage device. The controller is located on a side of the low low voltage device and the low voltage device along a second direction (x direction) perpendicular to the first direction. Of course, the first peripheral circuit chip 200 may also include a low low voltage device and at least one low voltage device, and the second peripheral circuit chip 300 includes a controller, a high voltage device and at least one other low voltage device. Alternatively, the first peripheral circuit chip 200 includes a low low voltage device and a controller, and the second peripheral circuit chip 300 includes a high voltage device and a low voltage device. Alternatively, the first peripheral circuit chip 200 includes a low low voltage device and a low voltage device, and the second peripheral circuit chip 300 includes a high voltage device and a controller. The above-mentioned low voltage device may include, but is not limited to, a page buffer or a logic device, and the operating voltage of the low voltage device is generally between 1.3 V and 3.3 V. As an example, the operating voltage of the low voltage device may be 1.3 V, 1.8 V, 2.3 V. 2.8 V or 3.3 V. Of course, it may be any value between any two of the above-mentioned voltage values. Those skilled in the art should understand that the above description of the operating voltage ranges of the low voltage device is for better understanding of the present solution and does not constitute a limitation on the present application.
In some examples, the low voltage device may include, but is not limited to, at least one of a transistor, a diode, a resistor, an inductor, and a capacitor. As an example, each of the first peripheral circuit chip 200 and the second peripheral circuit chip 300 includes a low voltage device and a third trench isolation structure 420, and each of the low voltage device of the first peripheral circuit chip 200 and the low voltage device of the second peripheral circuit chip 300 may include a transistor. In order to distinguish it from transistors of other peripheral devices such as a low low voltage device and a high voltage device, the transistor of the low voltage device is referred to as a third transistor 410 hereinafter. The third transistor 410 and the third trench isolation structure 420 of the first peripheral circuit chip 200 are at least partially located in the first substrate 210, and the third trench isolation structure 420 surrounds an active region of the corresponding third transistor 410. The third transistor 410 and the third trench isolation structure 420 of the second peripheral circuit chip 300 are at least partially located in the second substrate 310, and the above-mentioned third trench isolation structure 420 surrounds the active region of the corresponding third transistor 410. The process operations of the third transistor 410 and the third trench isolation structure 420 are similar to those above, which are not repeated here.
In some examples, as shown in
In some examples, as shown in
In some examples, as shown in
In some examples, as shown in
In some examples, as shown in
In addition, considering that the number of high voltage devices, low voltage devices and low low voltage devices will increase as the number of stacked layers of the memory array chip 100 of the three-dimensional memory increases continuously, in order to be able to meet the demands, the peripheral circuit assembly may further include the third peripheral circuit chip that includes a low voltage device. The third peripheral circuit chip may include all of the low voltage devices, of course, it may also include part of the low voltage devices, and the rest of the low voltage devices may be disposed on the first peripheral circuit chip 200 and/or the second peripheral circuit chip 300. It is to be noted that the structure of the third peripheral circuit chip is similar to the structures of the first peripheral circuit chip 200 and the second peripheral circuit chip 300 and is not repeated here. The number of the third peripheral circuit chips may be one or a plurality. In the case that the peripheral circuit assembly includes a plurality of third peripheral circuit chips, the plurality of third peripheral circuit chips are sequentially disposed along the first direction (z direction).
By disposing the low low voltage device and the high voltage device on the first peripheral circuit chip 200 and the second peripheral circuit chip 300 respectively, and bonding the first peripheral circuit chip 200 and/or the second peripheral circuit chip 300 to at least one memory array chip 100, the implementation of the present application can not only dispose the low low voltage device, the high voltage device and the controller on the first peripheral circuit chip 200 or the second peripheral circuit chip 300 located on a side of the memory array chip 100, which increases the number of stacked layers, i.e., the storage density, of the memory array chip 100 without affecting the size of the memory system along a direction vertical to stacking of the memory array chip 100, thereby achieving the compatibility between the high storage density and the small size of the memory system, but also can locate the low low voltage device and the high voltage device on different peripheral circuit chips respectively, such that the high voltage device and the low low voltage device no longer affect each other. In other words, the manufacturing process of the high voltage device is no longer affected by that of the low low voltage device, the polysilicon heights of the high voltage device and the low low voltage device can also be unified, and the NP/PP ion implantation of the high voltage device and the low voltage device can also be compatible. The high voltage device can employ the large-scale manufacturing process to reduce the process cost; meanwhile, a thermal budget of the low voltage device is no longer affected by the high voltage device, and there is no need to introduce an additional thermal budget during the fabrication of the low voltage device. In addition, since the controller and the high voltage device or the low low voltage device are integrated on the same peripheral circuit chip in the implementations of the present application, not only can the cost of forming the controller on a separate wafer be saved, but also the circuit wiring between chips can be reduced, that is, the circuit wiring between the chip where the controller is located and other chips can be saved, thereby improving the speed and integration.
In some examples, the first peripheral circuit chip 200 is in bonding connection with a side of the memory array chip 100, and the second peripheral circuit chip 300 is in bonding connection with a side of the first peripheral circuit chip 200 far away from the memory array chip 100. Of course, the first peripheral circuit chip 200 and the second peripheral circuit chip 300 may also exchange positions. In other words, the second peripheral circuit chip 300 is in bonding connection with a side of the memory array chip 100, and the first peripheral circuit chip 200 is in bonding connection with a side of the second peripheral circuit chip 300 far away from the memory array chip 100. Alternatively, the memory array chip 100 is located between the first peripheral circuit chip 200 and the second peripheral circuit chip 300. In other words, the first peripheral circuit chip 200 is in bonding connection with a side of the memory array chip 100, and the second peripheral circuit chip 300 is in bonding connection with a side of the memory array chip 100 far away from the first peripheral circuit chip 200.
In some examples, the first peripheral circuit chip 200 and/or the second peripheral circuit chip 300 further includes a low voltage device. In other words, the first peripheral circuit chip 200 or the second peripheral circuit chip 300 includes a low voltage device. Alternatively, the first peripheral circuit chip 200 and the second peripheral circuit chip 300 include low voltage devices at the same time.
In some examples, considering that the number of high voltage devices, low voltage devices and low low voltage devices will increase as the number of stacked layers of the memory array chip 100 of the three-dimensional memory increases continuously, in order to meet the demands, the peripheral circuit assembly may further include a third peripheral circuit chip that may be in bonding connection with a side of the memory array chip 100, the first peripheral circuit chip 200 or the second peripheral circuit chip 300. The number of the third peripheral circuit chips may be one or a plurality. In the case that the peripheral circuit assembly includes a plurality of third peripheral circuit chips, the plurality of third peripheral circuit chips are sequentially disposed along the first direction (z direction). The third peripheral circuit chip may include all of the low voltage devices, of course, it may also include part of the low voltage devices, and the rest of the low voltage devices may be disposed on the first peripheral circuit chip 200 and/or the second peripheral circuit chip 300.
In some examples, as shown in
The channel structure includes a function layer and a channel layer, each of which may be formed through a thin film deposition process, which may be, but is not limited to, a physical vapor deposition (PVD) process, a chemical vapor deposition (CVD) process, an atomic layer deposition (ALD) process or any combination of the above-mentioned processes. Further, the function layer may include a blocking layer, a charge trapping layer and a tunneling layer sequentially disposed along a second direction (x direction), and the second direction is perpendicular to the first direction, that is, perpendicular to the stacking direction of the stack structure 130. The materials of the blocking layer and the tunneling layer may be, but are not limited to, silicon oxide, and the material of the charge trapping layer may be, but is not limited to, silicon nitride. In other words, the function layer may have an ONO structure. The material of the channel layer may be, but is not limited to, a semiconductor material such as amorphous silicon, polysilicon, or monocrystalline silicon, etc.
It is to be noted that part of the function layer and the channel layer corresponding to the gate layer and a part of the gate layer together constitute a memory cell. A plurality of memory cells are connected in series along the stacking direction of the stack structure 130, i.e., the first direction (z direction) to form a memory string. The memory cells located in the same row, that is, distributed along the second direction (x direction), may be connected to the same word line, and the rest of the gate layer may be used as a word line for a plurality of memory cells in the corresponding memory string. Each memory string, that is, the memory cells in the same column, may be connected to the same bit line (not shown). Under the control of a voltage of the corresponding word line, carriers in the channel layer of the memory cell enter the charge trapping layer of the function layer, or the carriers in the charge trapping layer of the function layer return back to the channel layer, thereby achieving programing or erasing of the memory cell.
In some examples, as shown in
In order to shorten the wiring to reduce the cost and increase the transmission speed, in the case that the first peripheral circuit chip 200 and/or the second peripheral circuit chip 300 includes the low voltage device, the low voltage device is disposed corresponding to the core region 131, and the high voltage device is disposed corresponding to the connection region 132. As an example, the low voltage device includes a page buffer that is connected with a bit line to apply a bit line voltage to the bit line, wherein the bit line voltage corresponds to data DATA to be programmed, and the data DATA may include multi-bit data. In a read operation, the page buffer may sense data DATA stored in the selected memory cells through the bit line and output the sensed data DATA to an I/O circuit. The high voltage device may include a word line driver that is connected with a word line through a word line contact to apply a word line voltage to the word line, thereby performing an erase operation on the memory cells corresponding to the word line. As can be seen from the above, the page buffer is connected with the bit line, and the bit line contacts with the channel structure; that is, the bit line is located within the core region 131, the word line driver is connected to the word line through the word line contact, and the word line contact is located in the connection region 132. As such, the wiring is the shortest in an implementation of the present application by disposing the low voltage device and the high voltage device corresponding to the core region 131 and the connection region 132 respectively; in other words, by substantially aligning the low voltage device with the core region 131 and the high voltage device with the connection region 132 along the first direction, so that not only the wiring cost can be reduced, but also the transmission rate can be increased.
In some examples, the first peripheral circuit chip 200 is in bonding connection with a side of the memory array chip 100, and the second peripheral circuit chip 300 is in bonding connection with a side of the first peripheral circuit chip 200 far away from the memory array chip 100. The first peripheral circuit chip 200 includes a first substrate 210, a low low voltage device, a controller, a first interconnection structure 250 and a first connection structure 240. As shown in
In some examples, as shown in
In some examples, as shown in
Various operations in the method of fabricating the semiconductor device in the examples of the present application are introduced below in details.
In S100, a first peripheral circuit chip 200 including a first device is formed, wherein the first device may include a controller or a low voltage device in addition to a low low voltage device or a high voltage device. The high voltage device may include, but is not limited to, at least one of a row decoder, a column decoder, a word line driver and a bit line driver. The low low voltage device may include, but is not limited to, an I/O circuit. The low voltage device may include, but is not limited to, a page buffer or a logic device.
In some examples, the first device includes a low low voltage device including a first transistor 290 and a controller including a fourth transistor 295. Further, as shown in
In some examples, the first transistor 290 may be formed on the first substrate 210 by the following operations: forming a low low voltage well region 294 in the first substrate 210, for example, if the transistor is an N-type transistor, then an ion implantation or diffusion process may be used to form a P-type doped well, i.e., a low low voltage P well, in the first substrate 210, and a dopant may be a low concentration of P-type dopant such as boron (B), etc.; and if the transistor is a P-type transistor, then an ion implantation or diffusion process may be used to form an N-type doped well, i.e., a low low voltage N well, in the first substrate 210, and a dopant may be a low concentration of N-type dopant such as phosphorus (P), arsenic (As) and antimony (Sb), etc. A first drain 292 and a first source 291 are formed in the low low voltage well region 294; if the transistor is an N-type transistor, then the first drain 292 and the first source 291 are formed in the first substrate 210 using an N-type dopant such as phosphorus (P), arsenic (As) and antimony (Sb), etc.; and if the transistor is a P-type transistor, the first drain 292 and the first source 291 is formed in the first substrate 210 using a P-type dopant such as boron (B), etc. A first gate structure 293 including a gate insulation layer and a gate conductive layer is formed on a side of the first substrate 210. For example, the gate insulation layer may be formed on a side of the first substrate 210 through a thin film deposition process, and part of the gate insulation layer is removed through an etching process, such that the rest of the gate insulation layer is located between the first source 291 and the first drain 292. The gate conductive layer is formed on a side of the gate insulation layer facing away from the first substrate 210 through a thin film deposition process, and part of the gate conductive layer is removed through an etching process, such that the rest of the gate conductive layer is located between the first source 291 and the first drain 292 and covers the gate insulation layer. The material of the gate insulation layer includes a dielectric material such as silicon oxide, silicon nitride, silicon oxynitride, hafnium oxide, zirconium oxide, aluminum oxide, magnesium oxide, and tantalum oxide, etc., and the material of the gate conductive layer includes polysilicon, a conductive metal or a conductive alloy. As an example, the material of the gate conductive layer includes at least one of tungsten (W), titanium nitride (TiN), copper (Cu) and silver (Ag). It is to be noted that the first source 291 and the first drain 292 of the first transistor 290 may also be directly formed in the first substrate 210; in other words, the above-mentioned operations may not include the operation of forming the low low voltage well region 294. The method of forming the fourth transistor 295 on the first substrate 210 is similar to the method of forming the first transistor 290 above, and is not repeated here.
In some examples, the first device may further include a low voltage device that includes a third transistor 410. The first interconnection layer 220 includes a first insulation layer 260 covering the first substrate 210, the first transistor 290, the third transistor 410 and the fourth transistor 295 and a first interconnection structure 250 located in the first insulation layer 260, and the first interconnection structure 250 is connected with the first transistor 290, the third transistor 410 and/or the fourth transistor 295. The first insulation layer 260 may include a plurality of interlayer insulation layers stacked sequentially along a first direction. The first interconnection structure 250 contacts with a gate structure, a source or a drain of the above-mentioned transistor at one end, and contacts with the first connection structure 240 or penetrates through the first insulation layer 260 at the other end.
In S200, a second peripheral circuit chip 300 including a second device is formed, wherein one of the first device and the second device includes a high voltage device, and the other one includes a low low voltage device. In addition, the second device may further include a controller or a low voltage device.
In some examples, the second device includes a high voltage device. As shown in
In some examples, the second device may further include a low voltage device that includes a third transistor 410. The second interconnection layer 320 may include a second insulation layer 321 covering the second substrate 310 and the second and third transistors 350 and 410, and a third interconnection structure 322 located in the second insulation layer 321. The third interconnection structure 322 contacts with a gate structure, a source or a drain of the above-mentioned transistor of the second peripheral circuit chip 300 at one end, and penetrates through the second insulation layer 321 at the other end.
In S300, a memory array chip 100 is formed, wherein the number of the memory array chips 100 may be one or a plurality.
In some examples, S300 may include: forming a laminated structure on a side of a third substrate (not shown), wherein the laminated structure includes insulation layers and sacrificial layers stacked alternately along a first direction; forming, in the laminated structure, a channel structure at least penetrating through the laminated structure; replacing the sacrificial layers with gate layers to form a stack structure 130; and removing the third substrate to form a semiconductor layer 110 on a side of the stack structure. The insulation layers and the sacrificial layers may be disposed in pairs or may not be disposed in pairs. For example, the laminated structure may include, but is not limited to, 64, 128 or more than 128 pairs of insulation layers and sacrificial layers. As an example, the insulation layer is a silicon oxide layer, and the sacrificial layer is a silicon nitride layer.
In some examples, the channel structure may be formed by the following operations: along a stacking direction of the laminated structure, i.e., the first direction, forming a plurality of channel holes on a side of the laminated structure facing away from the third substrate, the channel holes penetrating through the laminated structure and extending at least to the third substrate, wherein the channel holes may be formed by a dry etching process, a combination of dry and wet etching processes, or a patterning process, and wherein the patterning process includes photolithography, cleaning and chemical mechanical polishing processes; forming blocking layers on inner walls of the channel holes to block the outflow of charges; forming charge trapping layers on sides of the blocking layers facing away from the inner walls of the channel holes to store charges; forming tunneling layers on sides of the charge trapping layers facing away from the blocking layers; forming channel layers on sides of the tunneling layers facing away from the charge trapping layers to transport the required carriers, i.e., electrons or holes; filling dielectric layers within hole spaces surrounded by the channel layers; and forming channel plugs contacting with the channel layers on sides of the filled dielectric layers facing away from the third substrate.
It is to be noted that those ordinarially skilled in the art should understand that, the formation positions of the function layers on the inner walls of the channel holes may be controlled according to different architectures of the memory system, without departing from the teaching of the present application. In other words, the function layers may be formed on sidewalls of the channel holes extending along the first direction (z direction) and may also be formed on the sidewalls and bottom surfaces of the channel holes extending along the second direction (x direction), on which the present application imposes no limitation. In addition, in order to reduce structure stress, air gaps may be formed in the filled dielectric layers by controlling corresponding parameters in the channel filling process.
In some examples, as shown in
In S400, at least one memory array chip 100 is bonded to at least one of the first peripheral circuit chip 200 and the second peripheral circuit chip 300 along the first direction. The above-mentioned bonding may refer to any one of hybrid bonding, anodic bonding, fusion bonding, transfer bonding, adhesive bonding and eutectic bonding. It is to be noted that, the first peripheral circuit chip 200 and the second peripheral circuit chip 300 may be bonded to each other, and one of them is bonded to the memory array chip 100. Alternatively, two sides of the memory array chip 100 are bonded to the first peripheral circuit chip 200 and the second peripheral circuit chip 300 respectively.
In some examples, S400 may include: bonding the first peripheral circuit chip 200 to a side of the memory array chip 100 (see
Further, as shown in
In some examples, as shown in
It is to be noted that the materials of the first bonding layer 270 to the fourth bonding layer 170 may include, but are not limited to, insulating materials such as silicon oxide, silicon nitride and/or silicon oxynitride, etc. The materials of the first bonding contacts 271 to the fourth bonding contacts 171 may include, but are not limited to, at least one of tungsten, cobalt, copper, aluminum, and silicide.
In some examples, in order to shorten the depth of the pad structure 160 along the first direction, reduce the process difficulty of forming the pad structure 160, and increase the transmission speed, after performing the operation of bonding the third interconnection layer 140 to the first interconnection layer 220, and before performing the operation of forming the first interconnection via structure 242 penetrating through the first substrate 210, the fabrication method further includes thinning the first substrate 210.
It should be understood that various forms of flows as shown above may be used, and operations thereof may be reordered, added or deleted. As an example, as long as expected results of the technical solutions of the present application can be achieved, various operations set forth in the disclosure may be performed in parallel, in sequence, or in a different order, on which no limitation is imposed herein in this regard.
A peripheral circuit assembly, a memory system and a fabrication method of the memory system provided in implementations of the present application can solve or partially solve deficiencies or needs in prior approaches.
A peripheral circuit assembly provided according to a first aspect of the present application comprises: a first peripheral circuit chip; and a second peripheral circuit chip located on a side of the first peripheral circuit chip along a first direction, wherein one of the first peripheral circuit chip and the second peripheral circuit chip comprises a low low voltage device, and the other one comprises a high voltage device, and the first peripheral circuit chip or the second peripheral circuit chip further includes a controller.
A memory system provided according to a second aspect of the present application comprises: a peripheral circuit assembly that comprises a first peripheral circuit chip and a second peripheral circuit chip located on a side of the first peripheral circuit chip along a first direction, wherein one of the first peripheral circuit chip and the second peripheral circuit chip comprises a low low voltage device, and the other one comprises a high voltage device, and the first peripheral circuit chip or the second peripheral circuit chip further comprises a controller; and at least one memory array chip in bonding connection with at least one of the first peripheral circuit chip and the second peripheral circuit chip along the first direction.
A fabrication method of the memory system provided according to a third aspect of the present application comprises: forming a first peripheral circuit chip comprising a first device; forming a second peripheral circuit chip comprising a second device, wherein one of the first device and the second device comprises a low low voltage device, and the other one comprises a high voltage device, and the first device or the second device further comprises a controller; forming at least one memory array chip; and bonding the at least one memory array chip to at least one of the first peripheral circuit chip and the second peripheral circuit chip along a first direction, wherein the second peripheral circuit chip is located on a side of the first peripheral circuit chip along the first direction.
The peripheral circuit assembly provided by the implementations of the present application may allow the high voltage device and the low low voltage device to no longer affect each other by locating the low low voltage device and the high voltage device on different peripheral circuit chips respectively. In other words, the manufacturing process of the high voltage device is no longer affected by that of the low low voltage device. The high voltage device may employ a large-scale manufacturing process, which not only reduces the process cost, but also enables the polysilicon heights of the high voltage device and the low low voltage device to be unified, and the NP/PP ion implantation of the high voltage device and the low voltage device can also be compatible. At the same time, a thermal budget of the low voltage device is no longer affected by the high voltage device, and there is no need to introduce an additional thermal budget during the fabrication of the low voltage device. In addition, since the first peripheral circuit chip or the second peripheral circuit chip further includes a controller in the implementations of the present application, in other words, the controller and the high voltage device or the low low voltage device are integrated on the same peripheral circuit chip in the implementations of the present application, not only can the cost for forming the controller on a separate wafer be saved, but also the circuit wiring between chips can be reduced, that is, the circuit wiring between the chip where the controller is located and other chips is saved, thereby improving the speed and integration.
According to the memory system provided by the implementations of the present application, the low low voltage device and the high voltage device are disposed on the first peripheral circuit chip and the second peripheral circuit chip respectively, and the first peripheral circuit chip and/or the second peripheral circuit chip are bonded to at least one memory array chip, so that not only the low low voltage device, the high voltage device and the controller may be disposed on the first peripheral circuit chip or the second peripheral circuit chip located on a side of the memory array chip, which increases the number of stacked layers, i.e., the storage density, of the memory array chip without affecting the size of the memory system along a direction vertical to stacking of the memory array chip, thereby achieving the compatibility between the high storage density and the small size of the memory system, but also the low low voltage device and the high voltage device can be located on different peripheral circuit chips respectively, such that the high voltage device and the low low voltage device no longer affect each other. In other words, the manufacturing process of the high voltage device is no longer affected by that of the low low voltage device, the polysilicon heights of the high voltage device and the low low voltage device can also be unified, and the NP/PP ion implantation of the high voltage device and the low voltage device can also be compatible. The high voltage device can employ the large-scale manufacturing process to reduce the process cost; meanwhile, a thermal budget of the low voltage device is no longer affected by the high voltage device, and there is no need to introduce an additional thermal budget during the fabrication of the low voltage device. In addition, since the controller and the high voltage device or the low low voltage device are integrated on the same peripheral circuit chip in the implementations of the present application, not only can the cost of forming the controller on a separate wafer be saved, but also the circuit wiring between chips can be reduced, that is, the circuit wiring between the chip where the controller is located and other chips can be saved, thereby improving the speed and integration.
It is to be understood that the contents as described in this part is neither intended to identify critical or important features of examples of the present application, nor used to limit the scope of the present application.
The above Detailed Description does not constitute a limitation on the protection scope of the present application. Those skilled in the art should understand that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements by equalizing other factors. Any amendments, equivalent substitutions and improvements and the like made within the spirit and principles of the present application shall be included in the protection scope of the present application.
| Number | Date | Country | Kind |
|---|---|---|---|
| 202310270309.1 | Mar 2023 | CN | national |
