International Business Machines Corporation, a New York corporation; Macronix International Corporation, a Taiwan corporation, and Infineon Technologies A.G., a German corporation, are parties to a Joint Research Agreement.
1. Field of the Invention
The present invention relates to high density memory devices based on phase change based memory materials, including chalcogenide based materials and on other programmable resistive materials, and to methods for manufacturing such devices.
2. Description of Related Art
Phase change based memory materials are widely used in read-write optical disks. These materials have at least two solid phases, including for example a generally amorphous solid phase and a generally crystalline solid phase. Laser pulses are used in read-write optical disks to switch between phases and to read the optical properties of the material after the phase change.
Phase change based memory materials, like chalcogenide based materials and similar materials, also can be caused to change phase by application of electrical current at levels suitable for implementation in integrated circuits. The generally amorphous state is characterized by higher resistivity than the generally crystalline state, which can be readily sensed to indicate data. These properties have generated interest in using programmable resistive material to form nonvolatile memory circuits, which can be read and written with random access.
The change from the amorphous to the crystalline state is generally a lower current operation. The change from crystalline to amorphous, referred to as reset herein, is generally a higher current operation, which includes a short high current density pulse to melt or break down the crystalline structure, after which the phase change material cools quickly, quenching the phase change process, allowing at least a portion of the phase change structure to stabilize in the amorphous state. It is desirable to minimize the magnitude of the reset current used to cause transition of phase change material from the crystalline state to the amorphous state. The magnitude of the reset current needed for reset can be reduced by reducing the size of the phase change material element in the cell and of the contact area between electrodes and the phase change material, so that higher current densities are achieved with small absolute current values through the phase change material element.
A technology developed by the assignee of the present application is referred to as a phase change bridge cell, in which a very small patch of memory material is formed as a bridge across a thin film insulating member between electrodes. The phase change bridge is easily integrated with logic and other types of circuitry on integrated circuits. See, U.S. application Ser. No. 11/155,067, filed 17 Jun. 2005, entitled “Thin Film Fuse Phase Change RAM and Manufacturing Method,” by Lung et al., which application was owned at the time of invention and is currently owned by the same assignee.
Problems have arisen in manufacturing such devices with very small dimensions, and with variations in process that meet tight specifications needed for large-scale memory devices. It is desirable therefore to provide a memory cell structure with an array architecture supporting high-density devices, and a method for manufacturing such structure that meets tight process variation specifications needed for large-scale memory devices. Furthermore, it is desirable to produce memory devices having a small active phase change region.
An array of memory cells described herein includes a plurality of word lines comprising doped semiconductor material having a first conductivity type, the word lines having word line widths and extending in parallel in a first direction. A plurality of second doped semiconductor regions having a second conductivity type opposite the first conductivity type, second doped semiconductor regions in the plurality of second doped semiconductor regions on corresponding word lines and defining respective pn junctions therebetween. A plurality of electrode pairs, wherein pairs include respective first and second electrodes and an insulating member between the first and second electrodes, the insulating member having a thickness between the first and second electrodes, the first electrodes on corresponding second doped semiconductor regions. An array of bridges of memory material across the insulating members of respective electrode pairs, the bridges having respective bottom surfaces and contacting the first and second electrodes in the respective electrode pairs on the bottom surface, and defining an inter-electrode path between the corresponding first and second electrodes defined by the thickness of the insulating member, wherein the memory material has at least two solid phases.
In preferred embodiments the memory cells have an area equal to 4F2, where F is about one half the sum of the word line width and the separation distance between adjacent word lines, typically about the minimum feature size for a lithographic process used in manufacturing the memory cells.
A method for manufacturing an array of memory cells as described herein comprises forming a plurality of word lines comprising doped semiconductor material having a first conductivity type, the word lines having word line widths and extending in parallel in a first direction. Forming a plurality of second doped semiconductor regions, having a second conductivity type opposite the first conductivity type, on corresponding word lines and defining respective pn junctions therebetween. Forming a plurality of electrode pairs, wherein pairs include respective first and second electrodes and an insulating member between the first and second electrodes, the insulating member having a thickness between the first and second electrodes, the first electrodes on corresponding second doped semiconductor regions. Forming an array of bridges of memory material across the insulating members of respective electrode pairs, the bridges having respective bottom surfaces and contacting the first and second electrodes in the respective electrode pairs on the bottom surface, and defining an inter-electrode path between the corresponding first and second electrodes defined by the thickness of the insulating member, wherein the memory material has at least two solid phases.
Other aspects and advantages of the invention are described below with reference to the figures.
The following description of the invention will typically be with reference to specific structural embodiments and methods. It is to understood that there is no intention to limit the invention to the specifically disclosed embodiments and methods but that the invention may be practiced using other features, elements, methods, and embodiments. Preferred embodiments are described to illustrate the present invention, not to limit its scope, which is defined by the claims. Those of ordinary skill in the art will recognize a variety of equivalent variations on the description that follows. Like elements in various embodiments are commonly referred to with like reference numerals.
A detailed description is provided with reference to
A first electrode 150 comprising conductive material is on the second doped semiconductor region 140. An insulating member 155 has a thickness 165 between the first electrode 150 and a conductive second electrode 160. The bridge of memory material 110 is across the insulating member 155 and contacts the first and second electrodes 150,160 on a bottom surface of the bridge 110. In operation, voltages on the first doped semiconductor region 120 and the second electrode 160 can induce current to flow from the first doped semiconductor region 120 to the second electrode 160, or vice-versa, via the second doped semiconductor region 130, the first electrode 150, and the bridge 110 of memory material.
The active region 170 is the region of the bridge 110 in which the memory material is induced to change between at least two solid phases. As can be appreciated the active region 170 can be made extremely small in the illustrated structure, reducing the magnitude of current needed to induce the phase changes. The inter-electrode path length between the first and second electrodes 150, 160 is defined by the thickness 165 of the insulating member. In representative embodiments, the thickness 165 of the insulating member 155 can be established using a thin film deposition technique to form a thin sidewall dielectric on the sidewall of first electrode 150. Likewise, the thickness 115 of the bridge 110 of memory material can be very small. The thickness 115 can be established using a thin film deposition technique of memory material on the top surfaces of the first electrode 150, the insulating member 110, and the second electrode 160.
In the illustrated embodiment a dielectric layer 180 is between the first doped semiconductor region 120 and the insulating member 155. Alternatively, the dielectric layer 180 can be omitted such that the insulating member 155 is on the first doped semiconductor region 120.
Embodiments of the memory cell 100 include phase change based memory materials, including chalcogenide based materials and other materials, for the bridge 110. Chalcogens include any of the four elements oxygen (O), sulfur (S), selenium (Se), and tellurium (Te), forming part of group VI of the periodic table. Chalcogenides comprise compounds of a chalcogen with a more electropositive element or radical. Chalcogenide alloys comprise combinations of chalcogenides with other materials such as transition metals. A chalcogenide alloy usually contains one or more elements from group IV of the periodic table of elements, such as germanium (Ge) and tin (Sn). Often, chalcogenide alloys include combinations including one or more of antimony (Sb), gallium (Ga), indium (In), and silver (Ag). Many phase change based memory materials have been described in technical literature, including alloys of: Ga/Sb, In/Sb, In/Se, Sb/Te, Ge/Te, Ge/Sb/Te, In/Sb/Te, Ga/Se/Te, Sn/Sb/Te, In/Sb/Ge, Ag/In/Sb/Te, Ge/Sn/Sb/Te, Ge/Sb/Se/Te and Te/Ge/Sb/S. In the family of Ge/Sb/Te alloys, a wide range of alloy compositions may be workable. The compositions can be characterized as TeaGebSb100−(a+b).
One researcher has described the most useful alloys as having an average concentration of Te in the deposited materials well below 70%, typically below about 60% and ranged in general from as low as about 23% up to about 58% Te and most preferably about 48% to 58% Te. Concentrations of Ge were above about 5% and ranged from a low of about 8% to about 30% average in the material, remaining generally below 50%. Most preferably, concentrations of Ge ranged from about 8% to about 40%. The remainder of the principal constituent elements in this composition was Sb. These percentages are atomic percentages that total 100% of the atoms of the constituent elements. (Ovshinsky '112 patent, cols 10-11.) Particular alloys evaluated by another researcher include Ge2Sb2Te5, GeSb2Te4 and GeSb4Te7, (Noboru Yamada, “Potential of Ge—Sb—Te Phase-Change Optical Disks for High-Data-Rate Recording”, SPIE v.3109, pp. 28-37 (1997).) More generally, a transition metal such as chromium (Cr), iron (Fe), nickel (Ni), niobium (Nb), palladium (Pd), platinum (Pt) and mixtures or alloys thereof may be combined with Ge/Sb/Te to form a phase change alloy that has programmable resistive properties. Specific examples of memory materials that may be useful are given in Ovshinsky '112 at columns 11-13, which examples are hereby incorporated by reference.
Phase change alloys are capable of being switched between a first structural state in which the material is in a generally amorphous solid phase, and a second structural state in which the material is in a generally crystalline solid phase in its local order in the active channel region of the cell. These alloys are at least bistable. The term amorphous is used to refer to a relatively less ordered structure, more disordered than a single crystal, which has the detectable characteristics such as higher electrical resistivity than the crystalline phase. The term crystalline is used to refer to a relatively more ordered structure, more ordered than in an amorphous structure, which has detectable characteristics such as lower electrical resistivity than the amorphous phase. Typically, phase change materials may be electrically switched between different detectable states of local order across the spectrum between completely amorphous and completely crystalline states. Other material characteristics affected by the change between amorphous and crystalline phases include atomic order, free electron density and activation energy. The material may be switched either into different solid phases or into mixtures of two or more solid phases, providing a gray scale between completely amorphous and completely crystalline states. The electrical properties in the material may vary accordingly.
Phase change alloys can be changed from one phase state to another by application of electrical pulses. It has been observed that a shorter, higher amplitude pulse tends to change the phase change material to a generally amorphous state. A longer, lower amplitude pulse tends to change the phase change material to a generally crystalline state. The energy in a shorter, higher amplitude pulse is high enough to allow for bonds of the crystalline structure to be broken and short enough to prevent the atoms from realigning into a crystalline state. Appropriate profiles for pulses can be determined empirically or by modeling, and specifically adapted to a particular phase change alloy. In following sections of the disclosure, the phase change material is referred to as GST, and it will be understood that other types of phase change materials can be used. A material useful for implementation of a PCRAM described herein is Ge2Sb2Te5.
The following are short summaries describing four types of resistive memory materials.
1. Chalcogenide Material
An exemplary method for forming chalcogenide material uses the PVD-sputtering or magnetron-sputtering method with source gas(es) of Ar, N2, and/or He, etc. at the pressure of 1 mTorr ˜100 mTorr. The deposition is usually done at room temperature. A collimator with an aspect ratio of 1˜5 can be used to improve the fill-in performance. To improve the fill-in performance, a DC bias of several tens of volts to several hundreds of volts is also used. On the other hand, the combination of DC bias and the collimator can be used simultaneously.
A post-deposition annealing treatment in vacuum or in an N2 ambient is optionally performed to improve the crystallize state of chalcogenide material. The annealing temperature typically ranges from 100° C. to 400° C. with an anneal time of less than 30 minutes.
The thickness of chalcogenide material depends on the design of cell structure. In general, a chalcogenide material with thickness of higher than 8 nm can have a phase change characterization so that the material exhibits at least two stable resistance states. It is expected that some materials are suitable with even lower thicknesses.
Word lines 220 extend in parallel in a first direction, the word lines 220 having word line widths 201 and adjacent word lines 220 separated by a word line separation distance 202. The word lines 220 comprise doped semiconductor material having a first conductivity type. Conductive bit lines 260 extend in parallel in a second direction perpendicular to the first direction, the bit lines 260 having bit line widths 261 and adjacent bit lines being separated by a bit line separation distance 262. In the illustrated embodiment the bit lines 260 form the second electrodes of the memory cells 200. Dielectric material 290 is between adjacent word lines 220.
The memory cells 200 include second doped semiconductor regions 230 on the corresponding word line 220 and define respective pn junctions 240 therebetween. The second doped semiconductor regions 230 have a second doped conductivity type opposite the first conductivity type. The memory cells 200 include electrode pairs, the pairs including respective first electrodes 250 and second electrodes (bit lines 260) and an insulating member 255 between the first electrode 250 and the second electrodes (bit lines 260), the first electrodes 250 on the corresponding second doped semiconductor regions 230. The insulating member 255 has a thickness 256 between the first electrodes 250 and the second electrodes (bit lines 260). In the illustrated embodiment dielectric 280 is between the insulating members 255 and the word lines 220. Alternatively, the dielectric 280 can be omitted such that the insulating members 255 are on the corresponding word lines 220.
The memory cells 200 include a bridge 210 of memory material across the insulating member 255. The bridge 210 has a bottom surface and contacts the first electrodes 250 and the second electrodes (bit lines 260) on the bottom surface. An inter-electrode path between the first electrodes 250 and the second electrodes (bit lines 260) has a path length defined by the thickness 256 of the insulating member 255.
The bridges 210 in the illustrated embodiment comprise memory material having at least two solid phases that are reversible, such as chalcogenide material or other related material, by applying a current through the bridge 210 or applying a voltage across the first electrodes 250 and the second electrodes (bit lines 260).
It will be understood that a wide variety of materials can be utilized in implementation of the conductive bit lines 260 and first electrodes 250, including metals such as aluminum, titanium nitride, and tungsten based materials as well as non-metal conductive material such as doped polysilicon. The first electrodes 250 and bit lines 260 in the illustrated embodiment are preferably TiN or TaN. Alternatively, the first electrodes 250 and bit lines 260 are TiAlN or TaAlN, or comprise, for further examples, one or more elements selected from the group consisting of Ti, W, Mo, Al, Ta, Cu, Pt, Ir, La, Ni, and Ru and alloys thereof.
Next, the multi-layer structure 300 illustrated in
Next, a first dielectric material 500 is formed in the first trenches 410 of the structure illustrated in
Next, a plurality of second trenches 600 are formed by etching the structure illustrated in
Next, a second dielectric material 700 is formed in the trenches 600 of
Next, a conformal layer of a third dielectric material is formed on the structure illustrated in
Next, a layer of conductive material is formed on the structure illustrated in
An embodiment of an array of memory cells as described herein include a plurality of word lines comprising doped semiconductor material having a first conductivity type, the word lines having word line widths and extending in parallel in a first direction. A plurality of second doped semiconductor regions having a second conductivity type opposite the first conductivity type, second doped semiconductor regions in the plurality of second doped semiconductor regions on corresponding word lines and defining respective pn junctions therebetween. A plurality of electrode pairs, wherein pairs include respective first and second electrodes and an insulating member between the first and second electrodes, the insulating member having a thickness between the first and second electrodes, the first electrodes on corresponding second doped semiconductor regions. An array of bridges of memory material across the insulating members of respective electrode pairs, the bridges having respective bottom surfaces and contacting the first and second electrodes in the respective electrode pairs on the bottom surface, and defining an inter-electrode path between the corresponding first and second electrodes defined by the thickness of the insulating member, wherein the memory material has at least two solid phases.
Advantages of an embodiment described herein include memory cells having reduced cell sizes, providing an array architecture supporting high-density devices, and a method for manufacturing such structure that meets tight process variation specifications needed for large-scale memory devices.
While the present invention is disclosed by reference to the preferred embodiments and examples detailed above, it is to be understood that these examples are intended in an illustrative rather than in a limiting sense. It is contemplated that modifications and combinations will occur to those skilled in the art, which modifications and combinations will be within the spirit of the invention and the scope of the following claims.
Any and all patents, patent applications and printed publications referred to above are incorporated by reference.
Number | Name | Date | Kind |
---|---|---|---|
3271591 | Ovshinsky | Sep 1966 | A |
3530441 | Ovshinsky | Sep 1970 | A |
4599705 | Holmberg et al. | Jul 1986 | A |
4719594 | Young et al. | Jan 1988 | A |
4876220 | Mohsen et al. | Oct 1989 | A |
4959812 | Momodomi et al. | Sep 1990 | A |
5017508 | Dodt et al. | May 1991 | A |
5166096 | Cote et al. | Nov 1992 | A |
5166758 | Ovshinsky et al. | Nov 1992 | A |
5177567 | Klersy et al. | Jan 1993 | A |
5332923 | Takeuchi et al. | Jul 1994 | A |
5391901 | Tanabe et al. | Feb 1995 | A |
5515488 | Stephens, Jr. | May 1996 | A |
5534712 | Ovshinsky et al. | Jul 1996 | A |
5687112 | Ovshinsky | Nov 1997 | A |
5789277 | Zahorik et al. | Aug 1998 | A |
5789758 | Reinberg | Aug 1998 | A |
5814527 | Wolstenholme et al. | Sep 1998 | A |
5831276 | Gonzalez et al. | Nov 1998 | A |
5837564 | Sandhu et al. | Nov 1998 | A |
5869843 | Harshfield | Feb 1999 | A |
5879955 | Gonzalez et al. | Mar 1999 | A |
5902704 | Schoenborn et al. | May 1999 | A |
5920788 | Reinberg | Jul 1999 | A |
5952671 | Reinberg et al. | Sep 1999 | A |
5958358 | Tenne et al. | Sep 1999 | A |
5970336 | Wolstenholme et al. | Oct 1999 | A |
5985698 | Gonzalez et al. | Nov 1999 | A |
5998244 | Wolstenholme et al. | Dec 1999 | A |
6011725 | Eitan et al. | Jan 2000 | A |
6025220 | Sandhu | Feb 2000 | A |
6031287 | Harshfield | Feb 2000 | A |
6034882 | Johnson et al. | Mar 2000 | A |
6066870 | Siek | May 2000 | A |
6077729 | Harshfield | Jun 2000 | A |
6087269 | Williams | Jul 2000 | A |
6087674 | Ovshinsky et al. | Jul 2000 | A |
6104038 | Gonzalez et al. | Aug 2000 | A |
6111264 | Wolstenholme et al. | Aug 2000 | A |
6114713 | Zahorik | Sep 2000 | A |
6117720 | Harshfield | Sep 2000 | A |
6147395 | Gilgen | Nov 2000 | A |
6150253 | Doan et al. | Nov 2000 | A |
6153890 | Wolstenholme et al. | Nov 2000 | A |
6177317 | Huang et al. | Jan 2001 | B1 |
6185122 | Johnson et al. | Feb 2001 | B1 |
6189582 | Reinberg et al. | Feb 2001 | B1 |
6236059 | Wolstenholme et al. | May 2001 | B1 |
RE37259 | Ovshinsky | Jul 2001 | E |
6271090 | Huang et al. | Aug 2001 | B1 |
6280684 | Yamada et al. | Aug 2001 | B1 |
6287887 | Gilgen | Sep 2001 | B1 |
6314014 | Lowrey et al. | Nov 2001 | B1 |
6320786 | Chang et al. | Nov 2001 | B1 |
6339544 | Chiang et al. | Jan 2002 | B1 |
6351406 | Johnson et al. | Feb 2002 | B1 |
6372651 | Yang et al. | Apr 2002 | B1 |
6420215 | Knall et al. | Jul 2002 | B1 |
6420216 | Clevenger et al. | Jul 2002 | B1 |
6420725 | Harshfield | Jul 2002 | B1 |
6423621 | Doan et al. | Jul 2002 | B2 |
6429064 | Wicker | Aug 2002 | B1 |
6462353 | Gilgen | Oct 2002 | B1 |
6483736 | Johnson et al. | Nov 2002 | B2 |
6487114 | Jong et al. | Nov 2002 | B2 |
6501111 | Lowrey | Dec 2002 | B1 |
6511867 | Lowrey et al. | Jan 2003 | B2 |
6512241 | Lai | Jan 2003 | B1 |
6514788 | Quinn | Feb 2003 | B2 |
6534781 | Dennison | Mar 2003 | B2 |
6545903 | Wu | Apr 2003 | B1 |
6555860 | Lowrey et al. | Apr 2003 | B2 |
6563156 | Harshfield | May 2003 | B2 |
6566700 | Xu | May 2003 | B2 |
6567293 | Lowrey et al. | May 2003 | B1 |
6579760 | Lung et al. | Jun 2003 | B1 |
6586761 | Lowrey | Jul 2003 | B2 |
6589714 | Maimon et al. | Jul 2003 | B2 |
6593176 | Dennison | Jul 2003 | B2 |
6597009 | Wicker | Jul 2003 | B2 |
6605527 | Dennison et al. | Aug 2003 | B2 |
6605821 | Lee et al. | Aug 2003 | B1 |
6607974 | Harshfield | Aug 2003 | B2 |
6613604 | Maimon et al. | Sep 2003 | B2 |
6617192 | Lowrey et al. | Sep 2003 | B1 |
6620715 | Blosse et al. | Sep 2003 | B1 |
6621095 | Chiang et al. | Sep 2003 | B2 |
6627530 | Li et al. | Sep 2003 | B2 |
6639849 | Takahashi et al. | Oct 2003 | B2 |
6673700 | Dennison et al. | Jan 2004 | B2 |
6744088 | Dennison | Jun 2004 | B1 |
6791102 | Johnson et al. | Sep 2004 | B2 |
6797979 | Chiang et al. | Sep 2004 | B2 |
6800504 | Li et al. | Oct 2004 | B2 |
6800563 | Xu | Oct 2004 | B2 |
6805563 | Ohashi et al. | Oct 2004 | B2 |
6808991 | Tung et al. | Oct 2004 | B1 |
6815704 | Chen | Nov 2004 | B1 |
6830952 | Lung et al. | Dec 2004 | B2 |
6850432 | Lu et al. | Feb 2005 | B2 |
6859389 | Idehara et al. | Feb 2005 | B2 |
6861267 | Xu et al. | Mar 2005 | B2 |
6864500 | Gilton | Mar 2005 | B2 |
6864503 | Lung et al. | Mar 2005 | B2 |
6867638 | Saiki et al. | Mar 2005 | B2 |
6888750 | Walker et al. | May 2005 | B2 |
6894305 | Yi et al. | May 2005 | B2 |
6903362 | Wyeth et al. | Jun 2005 | B2 |
6909107 | Rodgers et al. | Jun 2005 | B2 |
6927410 | Chen | Aug 2005 | B2 |
6933516 | Xu | Aug 2005 | B2 |
6936840 | Sun et al. | Aug 2005 | B2 |
6937507 | Chen | Aug 2005 | B2 |
6972430 | Casagrande et al. | Dec 2005 | B2 |
6992932 | Cohen et al. | Jan 2006 | B2 |
7023009 | Kostylev et al. | Apr 2006 | B2 |
7033856 | Lung et al. | Apr 2006 | B2 |
7042001 | Kim et al. | May 2006 | B2 |
7053431 | Ogiwara | May 2006 | B2 |
7067864 | Nishida et al. | Jun 2006 | B2 |
7067865 | Lung et al. | Jun 2006 | B2 |
7122281 | Pierrat | Oct 2006 | B2 |
7122824 | Khouri et al. | Oct 2006 | B2 |
7126149 | Iwasaki et al. | Oct 2006 | B2 |
7132675 | Gilton | Nov 2006 | B2 |
7166533 | Happ | Jan 2007 | B2 |
7214958 | Happ | May 2007 | B2 |
7220983 | Lung | May 2007 | B2 |
7277317 | Le Phan et al. | Oct 2007 | B2 |
20010055838 | Walker et al. | Dec 2001 | A1 |
20020081833 | Li et al. | Jun 2002 | A1 |
20020182835 | Quinn | Dec 2002 | A1 |
20030073262 | Xu et al. | Apr 2003 | A1 |
20040051094 | Ooishi | Mar 2004 | A1 |
20040166604 | Ha et al. | Aug 2004 | A1 |
20050029502 | Hudgens | Feb 2005 | A1 |
20050093022 | Lung | May 2005 | A1 |
20050124157 | Lowrey et al. | Jun 2005 | A1 |
20050167656 | Sun et al. | Aug 2005 | A1 |
20050201182 | Osada et al. | Sep 2005 | A1 |
20050212024 | Happ | Sep 2005 | A1 |
20050215009 | Cho | Sep 2005 | A1 |
20050270832 | Chu et al. | Dec 2005 | A1 |
20060043617 | Abbott | Mar 2006 | A1 |
20060108667 | Lung | May 2006 | A1 |
20060110878 | Lung et al. | May 2006 | A1 |
20060118913 | Yi et al. | Jun 2006 | A1 |
20060154185 | Ho et al. | Jul 2006 | A1 |
20060175599 | Happ | Aug 2006 | A1 |
20060226409 | Burr et al. | Oct 2006 | A1 |
20060234138 | Fehlhaber et al. | Oct 2006 | A1 |
20060284157 | Chen et al. | Dec 2006 | A1 |
20060284158 | Lung et al. | Dec 2006 | A1 |
20060284214 | Chen | Dec 2006 | A1 |
20060284279 | Lung et al. | Dec 2006 | A1 |
20060286709 | Lung et al. | Dec 2006 | A1 |
20060286743 | Lung et al. | Dec 2006 | A1 |
20070030721 | Segal et al. | Feb 2007 | A1 |
20070037101 | Morioka | Feb 2007 | A1 |
20070108077 | Lung et al. | May 2007 | A1 |
20070108429 | Lung | May 2007 | A1 |
20070108430 | Lung | May 2007 | A1 |
20070108431 | Chen et al. | May 2007 | A1 |
20070109836 | Lung | May 2007 | A1 |
20070109843 | Lung et al. | May 2007 | A1 |
20070111429 | Lung | May 2007 | A1 |
20070115794 | Lung | May 2007 | A1 |
20070117315 | Lai et al. | May 2007 | A1 |
20070121363 | Lung | May 2007 | A1 |
20070121374 | Lung et al. | May 2007 | A1 |
20070126040 | Lung | Jun 2007 | A1 |
20070131922 | Lung | Jun 2007 | A1 |
20070131980 | Lung | Jun 2007 | A1 |
20070138458 | Lung | Jun 2007 | A1 |
20070147105 | Lung et al. | Jun 2007 | A1 |
20070154847 | Chen et al. | Jul 2007 | A1 |
20070155172 | Lai et al. | Jul 2007 | A1 |
20070158632 | Ho | Jul 2007 | A1 |
20070158633 | Lai et al. | Jul 2007 | A1 |
20070158645 | Lung | Jul 2007 | A1 |
20070158690 | Ho et al. | Jul 2007 | A1 |
20070158862 | Lung | Jul 2007 | A1 |
20070161186 | Ho | Jul 2007 | A1 |
20070173019 | Ho et al. | Jul 2007 | A1 |
20070173063 | Lung | Jul 2007 | A1 |
20070176261 | Lung | Aug 2007 | A1 |
20070224726 | Chen et al. | Sep 2007 | A1 |
20070246699 | Lung | Oct 2007 | A1 |
20070257300 | Ho et al. | Nov 2007 | A1 |
20070262388 | Ho et al. | Nov 2007 | A1 |
Number | Date | Country |
---|---|---|
0079539 | Dec 2000 | WO |
0145108 | Jun 2001 | WO |
Entry |
---|
Adler, David, “Amorphous-Semiconductor Devices,” Sci. Amer., vol. 236, pp. 36-48, May 1977. |
Adler, D. et al., “Threshold Switching in Chalcogenide-Glass Thin Films,” J. Appl/ Phys 51(6), Jun. 1980, pp. 3289-3309. |
Ahn, S.J. et al., “A Highly Manufacturable High Density Phase Change Memory of 64 Mb and Beyond,” IEEE IEDM 2004, pp. 907-910. |
Ahn, S. J. et al., “Highly Reliable 5nm Contact Cell Technology for 256Mb PRAM,” VLSI Technology, Digest of Technical Papers, Jun. 14-16, 2005, pp. 98-99. |
Axon Technologies Corporation paper: Technology Description, pp. 1-6. |
Bedeschi, F. et al., “4-MB MOSFET-Selected Phase-Change Memory Experimental Chip,” IEEE, 2004, 4 pp. |
Blake thesis, “Investigation of GeTeSb5 Chalcogenide Films for Use as an Analog Memory,” AFIT/GE/ENG/00M-04, Mar. 2000, 121 pages. |
Chen, An et al., “Non-Volatile Resistive Switching for Advanced Memory Applications,” IEEE IEDM , Dec. 5-7, 2005, 4 pp. |
Cho, S. L. et al., “Highly Scalable On-axis Confined Cell Structure for High Density PRAM beyond 256Mb,” 2005 Symposium on VLSI Technology Digest of Technical Papers, pp. 96-97. |
Gibson, G. A. et al, “Phase-change Recording Medium that Enables Ultrahigh-density Electron-beam Data Storage,” Applied Physics Letter, 2005, 3 pp., vol. 86. |
Gill, Manzur et al., “A High-Performance Nonvolatile Memory Technology for Stand-Alone Memory and Embedded Applications,” 2002 IEEE-ISSCC Technical Digest (TD 12.4), 7 pp. |
Ha, Y. H. et al., “An Edge Contact Type Cell fro Phase Change RAM Featuring Very Low Power Consumption,” 2003 Symposium on VLSI Technology Digest of Technical Papers, pp. 175-176. |
Happ, T. D. et al., “Novel None-Mask Self-Heating Pillar Phase Change Memory,” 2006 Symposium on VLSI Technology, 2 pp. |
Haring Bolivar, P. et al., “Lateral Design for Phase Change Random Access Memory Cells with Low-Current Consumption,” presented at 3rd E*PCOS 04 Symposium in Balzers, Principality of Liechtenstein, Sep. 4-7, 2004, 4 pp. |
Horii, H. et al., “A Novel Cell Technology Using N-doped GeSbTe Films for Phase Change RAM,” 2003 Symposium on VLSI Technology Digest of Technical Papers, pp. 177-178. |
Hudgens, S. et al., “Overview of Phase-Change Chalcogenide Nonvolatile Memory Technology,” MRS Bulletin, Nov. 2004, pp. 829-832. |
Hwang, Y. N. et al., “Full Integration and Reliability Evaluation of Phase-change RAM Based on 0.24?m-CMOS Technologies,” 2003 Symposium on VLSI Technology Digest of Technical Papers, pp. 173-174. |
Iwasaki, Hiroko et al., “Completely Erasable Phase Change Optical Disk,” Jpn. J. Appl. Phys., Feb. 1992, pp. 461-465, vol. 31. |
Jeong, C. W. et al., “Switching Current Scaling and Reliability Evaluation in PRAM,” IEEE Non-Volatile Semiconductor Memory Workshop, Monterey, CA, 2004, pp. 28-29 and workshop cover sheet. |
Kim, Kinam et al., “Reliability Investigations for Manufacturable High Density PRAM,” IEEE 43rd Annual International Reliability Physics Symposium, San Jose, 2005, pp. 157-162. |
Kojima, Rie et al., “Ge-Sn-Sb-Te Phase-change Recording Material Having High Crystallization Speed,” Proceedings of PCOS 2000, pp. 36-41. |
Lacita, A. L.; “Electrothermal and Phase-change Dynamics in Chalcogenide-based Memories,” IEEE IEDM 2004, 4 pp. |
Lai, Stefan, “Current Status of the Phase Change Memory and Its Future,” IEEE IEDM 2003, pp. 255-258. |
Lai, Stephan et al., OUM-A 180 nm Nonvolatile Memory Cell Element Technology for Stand Alone and Embedded Applications, IEEE IEDM 2001, pp. 803-806. |
Lankhorst, Martin H. R., et al; Low-Cost and Nanoscale Non-Volatile Memory Concept for Future Silicon Chips, Mar. 13, 2005, 6 pp., Nature Materials Advance Online Publication, www.nature.com/naturematerials. |
“Magnetic Bit Boost,” www.sciencenews.org <http://www.sciencenews.org>, Dec. 18 & 25, 2004, p. 389, vol. 166. |
Mott, Nevill, “Electrons in Glass,” Nobel Lecture, Dec. 8, 1977, Physics, 1977, pp. 403-413. |
“New Memories Tap Spin, Gird for Battle,” Science News, Apr. 3, 1999, p. 223, vol. 155. |
“Optimized Thermal Capacitance in a Phase Change Memory Cell Design”, IPCOM000141986D, IP.com Prior Art Database, Oct. 18, 2006, 4 pp. |
Ovonyx Non-Confidential paper entitled “Ovonic Unified Memory,” Dec. 1999, pp. 1-80. |
Ovshinsky, Sandford R., “Reversible Electrical Switching Phenomena in Disordered Structures,” Physical Review Letters, vol. 21, No. 20, Nov. 11, 1968, pp. 1450-1453. |
Owen, Alan E. et al., “Electronic Conduction and Switching in Chalcogenide Glasses,” IEEE Transactions on Electron Devices, vol. Ed. 20, No. 2, Feb. 1973, pp. 105-122. |
Pellizer, F. et al., “Novel ?Trench Phase-Change Memory Cell for Embedded and Stand-Alone Non-Volatile Memory Applications,” 2004 Symposium on VLSI Technology Digest of Technical Papers, pp. 18-19. |
Pirovano, Agostino et al., “Reliability Study of Phase-Change Nonvolatile Memories,” IEEE Transactions on Device and Materials Reliability, Sep. 2004, pp. 422-427, vol. 4, No. 3. |
Prakash, S. et al., “A Guideline for Designing Chalcogenide-Based Glasses for Threshold Switching Characteristics,” IEEE Electron Device Letters, vol. 18, No. 2, Feb. 1997, pp. 45-47. |
Radaelli, A. et al., “Electronic Switching Effect and Phase-Change Transition in Chalcogenide Materials,” IEEE Electron Device Letters, Oct. 2004, pp. 684-686, vol. 25, No. 10. |
“Remembering on the Cheap,” www.sciencenews.org <http://www.sciencenews.org>, Mar. 19, 2005, p. 189, vol. 167. |
Rochefort, C. et al., “Manufacturing of High Aspect-Ration p-n Junctions Using Vapor Phase Doping for Application in Multi-Resurf Devices,” IEEE 2002. |
Strauss, Karl F. et al., “Overview of Radiation Tolerant Unlimited Write Cycle Non-Volatile Memory,” IEEE 2000. |
Subramanian, Vivek et al., “Low Leakage Germanium-Seeded Laterally-Crystallized Single-Grain 100-nm TFT's for Vertical Intergration Applications,” IEEE Electron Device Letters, vol. 20, No. 7, Jul. 1999. |
Wicker, Guy et al., Nonvolatile, High Density, High Performance Phase Change Memory, 1999, ‘http://klabs.org/richcontent/MAPLDCon99/Papers/P21—Tyson—P.PDF#search=nonvolatile%20high%20density%20high%20performance%20phase%20change%20memory <http://klabs.org/richcontent/MAPLDCon99/Papers/P21—Tyson—P.PDF#search='nonvolatile%20high%20density%20high%20performance%20phase%20change%20memory>’, 8 pages. |
Wicker, Guy, “A Comprehensive Model of Submicron Chalcogenide Switching Devices,” Doctoral Dissertation, Wayne State University, Detroit, MI, 1996. |
Wolf, Stanley, Excerpt from: Silicon Processing for the VLSI Era—vol. 4, pp. 674-679, 2004. |
Wuttig, Matthias, “Towards a Universal Memory?” Nature Materials, Apr. 2005, pp. 265-266, vol. 4. |
Yi, J. H. et al., “Novel Cell Structure of PRAM with Thin Metal Layer Inserted GeSbTe,” IEEE IEDM 2003, 4 pages. |
Yonehara, T. et al., “Control of Grain Boundary Location by Selective Nucleation Over Amorphous Substrates,” Mat. Res. Soc. Symp. Proc., vol. 106, 1998, pp. 21-26. |
“Thermal Conductivity of Crystalline Dielectrics” in CRC Handbook of Chemistry and Physics, Internet Version 2007, (87th edition), David R. Lide, ed. Taylor and Francis, Boca Raton, FL. |
Schafft, Harry A. et al., “Thermal Conductivity Measurements of Thin Films Silicon Dioxide”, Proceedings of the IEEE 1989 International Conference on Microelectronic Test Structures, vol. 2, No. 1, Mar. 1989, pp. 121-124. |
Number | Date | Country | |
---|---|---|---|
20080247224 A1 | Oct 2008 | US |