Patent Application
20240194677
The present disclosure generally relates semiconductor devices, and more particularly, to SRAM constructed with nanosheet Field Effect Transistors (FET).
In SRAM cells, there are gate stacks of nanosheets with neighboring devices having a source/drain (S/D) epitaxial (referred to as “epi”) grown on the cell that is typically diamond-shaped. Particularly in a case where FET pull-up and pull-down device are arranged, the epi S/D diamonds may contact each other causing a short of the neighboring devices.
According to one embodiment, a semiconductor device includes a first nanosheet field effect transistor (FET) arranged on a substrate, wherein the first FET includes a first gate stack. A second nanosheet FET is arranged on the substrate adjacent to the first nanosheet FET. The second FET includes a second gate stack. A top of the first gate stack and a top of the second gate stack have different heights.
In one embodiment, a first channel of the first gate stack extends from the bottom of the first gate stack and has a first height. A second channel of the second gate stack extends from the bottom of the second gate stack and has a second height. The first height of the first channel is different than the second height of the second channel based on a difference in channel heights of the substrate.
In one embodiment, the first height of the first channel is different than the second height of the second channel additionally based on a metal gate height having a distance between two adjacent channels in the first gate stack and the second gate.
In one embodiment, the first FET is a pull-up (PU) PFET, and the second FET is a pull-down (PD) NFET.
In one embodiment, an S/D epitaxial growth on the PU PFET and on the PD NFET are offset by a difference in channel height of the first height of the first channel and the second height of the second channel.
In one embodiment, the substrate includes a stepped upper surface. The PU PFET is arranged on higher portion of the stepped upper surface. The PD NFET is arranged on a lower portion of the stepped upper surface.
In one embodiment, a shallow trench isolation (STI) SiO2 recess is connected to the PU PFET and the PD NFET to fill different depths on an upper surface of the substrate.
In one embodiment, the substrate includes Si having a pattern with different recess depths, wherein the substrate is arranged below a Bottom Dielectric Isolation (BDI) layer.
In one embodiment, there are a same number of nanosheets for each nanosheet FET on the Si pattern.
In one embodiment, a same number of nanosheets have a same total nanosheet height. The total nanosheet height includes a channel height, a dummy SiGe layer, and the BDI layer.
According to one embodiment, a method of preventing a source/drain (S/D) epi merge includes providing a first nanosheet fin including a first field effect transistor (FET) on a substrate. The first FET includes a first gate stack. A second nanosheet fin including a second FET is provided on the substrate adjacent to the first nanosheet FET. The second FET includes a second gate stack. A top of the first gate stack is a different height than a top of the second gate stack.
In one embodiment, the method includes forming a step on the surface of the substrate so that the first gate stack is offset in height from the second gate stack.
In one embodiment, the method includes forming the first nanosheet fin and the second nanosheet fin on the substrate to have equal lengths.
In one embodiment, the method includes providing the first nanosheet fin on a higher portion of the stepped substrate surface and the second nanosheet fin on a lower portion of the stepped substrate surface.
In one embodiment, the first FET provided on the first nanosheet fin comprises a pull-up (PU) PFET, and the second FET provided on the second nano fin comprises a pull-down (PD) NFET.
In one embodiment, the method includes providing a first channel that extends from the bottom of the first gate stack and has a first height, and providing a second channel that extends from the bottom of the second gate stack and has a second height. The first height of the first channel is different than the second height of the second channel by at least a difference in channel heights of the substrate.
In one embodiment, the method includes providing a first metal gate on the first nanosheet FET and a second metal gate on the second nanosheet FET. The first height of the first channel is different than the second height of the second channel by the difference in channel heights and by a metal gate height distance between the first channel and the second channel in the first gate stack and the second gate.
According to one embodiment, a method of forming a semiconductor device includes forming a stepped portion on a substrate surface. A first gate nanosheet stack with alternating layers of different semiconductor materials is formed on the stepped portion of the substrate surface. A second nanosheet gate stack with alternating layers of different semiconductor materials is formed on a non-stepped portion of the substrate surface. The first nanosheet gate stack and the second nanosheet gate stack are patterned to create respective nanosheet fins. An upper surface of the first nanosheet fin is higher than an upper surface of the second nanosheet fin. An epitaxial source/drain (S/D) is grown on each of the first nanosheet fin and the second nanosheet fin.
In one embodiment, the epitaxial S/D is grown on a side of each nanosheet fin and has different respective height on the stepped portion than the non-stepped portion of the substrate.
In one embodiment, the alternating layers of different semiconductor materials include Si and SiGe, and the method further includes providing an STI of SiO2 on surface of the substrate.
The drawings are of illustrative embodiments. They do not illustrate all embodiments. Other embodiments may be used in addition to or instead. Details that may be apparent or unnecessary may be omitted to save space or for more effective illustration. Some embodiments may be practiced with additional components or steps and/or without all the components or steps that are illustrated. When the same numeral appears in different drawings, it refers to the same or like components or steps.
In the following detailed description, numerous specific details are set forth by way of examples to provide a thorough understanding of the relevant teachings. However, it should be understood that the present teachings may be practiced without such details. In other instances, well-known methods, procedures, components, and/or circuitry have been described at a relatively high level, without detail, to avoid unnecessarily obscuring aspects of the present teachings. It is to be understood that the present disclosure is not limited to the depictions in the drawings, as there may be fewer elements or more elements than shown and described.
In discussing the present technology, it may be helpful to describe various salient terms. In one aspect, spatially related terminology such as “front,” “back,” “top,” “bottom,” “beneath,” “below,” “lower,” above,” “upper,” “side,” “left,” “right,” and the like, is used with reference to the direction of the Figures being described. Since components of embodiments of the disclosure can be positioned in a number of different directions, the directional terminology is used for purposes of illustration and is in no way limiting. Thus, it will be understood that the spatially relative terminology is intended to encompass different directions of the device in use or operation in addition to the direction depicted in the figures. For example, if the device in the figures is turned over, elements described as “below” or “beneath” other elements or features would then be oriented “above” the other elements or features. Thus, for example, the term “below” can encompass both an orientation that is above, as well as, below. The device may be otherwise oriented (rotated 90 degrees or viewed or referenced at other directions) and the spatially relative descriptors used herein should be interpreted accordingly.
Although the terms first, second, third, etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of example embodiments. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.
Example embodiments are described herein with reference to schematic illustrations of idealized or simplified embodiments (and intermediate structures). As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, may be expected. Thus, the regions illustrated in the figures are schematic in nature and their shapes do not necessarily illustrate the actual shape of a region of a device and do not limit the scope.
It is to be understood that other embodiments may be used and structural or logical changes may be made without departing from the spirit and scope defined by the claims. The description of the embodiments is not limiting. In particular, elements of the embodiments described hereinafter may be combined with elements of different embodiments.
There is a step 107 of Si to increase a distance between the active sheets and space the epi S/D further apart to prevent shorting. A shallow trench isolation (STI) 110 of SiO2 is arranged on top of the substrate 105 and surrounding the gate stacks. A gate spacer material 115 is arranged around the gate stacks. The spacer material can be made of any suitable dielectric material, such as, for example, a low-k dielectric, nitrides, silicon nitride, silicon oxide, SiON, SiC, SiOCN, and SiBCN. In some embodiments of the discloser, the spacer material 115 is a conformal layer deposited over the semiconductor structure followed by an anisotropic etch. An epi S/D 120 for the pull-up PU FET and an epi S/D 125 for the pull-down PD FET are shown as having a difference in heights at least because of the step 107 of Si. The difference in heights reduces the possibility of the epi S/Ds contacting each other and causing device failure without increasing the cell size to space the epi S/Ds apart from each other. In addition, a metal gate height distance (
Fabrication of device depicted in
A step (e.g., recess) is formed on the substrate 105. One non-limiting example is to form an Optical Planarizing Layer (OPL) coating 210. An etching is then performed to create the step.
With the foregoing overview of the example architecture, it may be helpful now to consider a high-level discussion of an example process. To that end,
At operation 1602, a step (e.g., recess) is formed on the substrate. One non-limiting example is to form an Optical Planarizing Layer (OPL) coating such as shown in
At operation 1604, a first gate nanosheet stack is formed on the step of the substrate that includes alternating layers of different semiconductor materials on the semiconductor surface. For example,
At operation 1606, a second gate nanosheet stack is formed on the non-stepped surface of the substrate that includes alternating layers of different semiconductor materials on the semiconductor surface. The alternating layers are the same as described above with regard to operation 1604.
At operation 1608, the first and second nanosheet gate stacks are patterned into fins.
At operation 1610, an epitaxial source/drain (epi S/D) is grown on each of the first nanosheet fin and the second nanosheet fin.
With regard to the method described above in the flowchart of
The descriptions of the various embodiments of the present teachings have been presented for purposes of illustration, but are not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.
While the foregoing has described what are considered to be the best state and/or other examples, it is understood that various modifications may be made therein and that the subject matter disclosed herein may be implemented in various forms and examples, and that the teachings may be applied in numerous applications, only some of which have been described herein. It is intended by the following claims to claim any and all applications, modifications, and variations that fall within the true scope of the present teachings. For example, while the substrate is disclosed as being Si, it may be made of other materials.
The components, operations, steps, features, objects, benefits, and advantages that have been discussed herein are merely illustrative. None of them, nor the discussions relating to them, are intended to limit the scope of protection. While various advantages have been discussed herein, it will be understood that not all embodiments necessarily include all advantages. Unless otherwise stated, all measurements, values, ratings, positions, magnitudes, sizes, and other specifications that are set forth in this specification, including in the claims that follow, are approximate, not exact. They are intended to have a reasonable range that is consistent with the functions to which they relate and with what is customary in the art to which they pertain.
Numerous other embodiments are also contemplated. These include embodiments that have fewer, additional, and/or different components, steps, features, objects, benefits and advantages. These also include embodiments in which the components and/or steps are arranged and/or ordered differently.
The flowcharts, and diagrams in the figures herein illustrate the architecture, functionality, and operation of possible implementations according to various embodiments of the present disclosure.
While the foregoing has been described in conjunction with exemplary embodiments, it is understood that the term “exemplary” is merely meant as an example, rather than the best or optimal. Except as stated immediately above, nothing that has been stated or illustrated is intended or should be interpreted to cause a dedication of any component, step, feature, object, benefit, advantage, or equivalent to the public, regardless of whether it is or is not recited in the claims.
It will be understood that the terms and expressions used herein have the ordinary meaning as is accorded to such terms and expressions with respect to their corresponding respective areas of inquiry and study except where specific meanings have otherwise been set forth herein. Relational terms such as first and second and the like may be used solely to distinguish one entity or action from another without necessarily requiring or implying any such actual relationship or order between such entities or actions. The terms “comprises,” “comprising,” or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. An element proceeded by “a” or “an” does not, without further constraints, preclude the existence of additional identical elements in the process, method, article, or apparatus that comprises the element.
The Abstract of the Disclosure is provided to allow the reader to quickly ascertain the nature of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. In addition, in the foregoing Detailed Description, it can be seen that various features are grouped together in various embodiments for the purpose of streamlining the disclosure. This method of disclosure is not to be interpreted as reflecting an intention that the claimed embodiments have more features than are expressly recited in each claim. Rather, as the following claims reflect, the inventive subject matter lies in less than all features of a single disclosed embodiment. Thus, the following claims are hereby incorporated into the Detailed Description, with each claim standing on its own as a separately claimed subject matter.
