The following will describe a printed wiring board according to preferred embodiments of the present invention and embodiments of a method of manufacturing the same with reference to the accompanying drawings.
The drawings used in the following explanation show the main part of the printed wiring board, that is, a mounting area for mounting a semiconductor device.
A printed wiring board and a method of manufacturing the same will be described below according to First Embodiment of the present invention (corresponding to claim 1 and claim 15).
First, referring to
In a mounting area 10 of a printed wiring board 1 according to First Embodiment, conductor wiring layers (inner layers) 12 are provided on both sides of a core substrate 11, and the surfaces of the conductor wiring layers 12 are covered with interlayer insulating resin layers 13. Further, a conductor wiring layer (outer layer) 14b and a plurality of conductor lands (conductor land portions) 14a for mounting (solder and the like) a semiconductor device are provided on the surfaces of the interlayer insulating resin layer 13, and surface insulating resin layers 16 are provided on the outermost surfaces (outside surfaces). Therefore, one side of the printed wiring board 1 has a four-layer structure (four-layer board). The conductor lands 14a are disposed on the periphery (edge) of the mounting area 10.
The thickness of the overall printed wiring board 1 is mainly set at 0.4 mm to 1.6 mm and the number of layers is at least 1 to 10 (the number of layers is not limited and
As the core substrate 11 and the interlayer insulating resin layer 13, a reinforcing base such as a paper base, a glass base, a glass nonwoven fabric base, and an aramid nonwoven fabric base is frequently impregnated with phenol resin, epoxy resin, polyimide resin, bismaleimide-triazine resin, and so on.
The conductor wiring layers (inner layers) 12, the conductor wiring layer (outer layer) 14b, and the conductor lands 14a are generally made of Cu. These layers and lands are formed by a method of forming wiring by copper foil etching and a method of forming wiring by Cu plating. Further, each layer is about 10 μm to 40 μm in thickness and the inner layer is generally thinner than the outer layer.
Surface treatment on the conductor lands 14a is one of the application of heat resistant pre-flux and the plating of Ni, Pd, Au and the like, so that the solderability improves. Moreover, as the surface insulating resin layer 16, a photosensitive resin called solder resist is frequently used with a thickness of about 10 μm to 40 μm.
The conductor wiring layers (inner layers) 12, the conductor wiring layer (outer layer) 14b, and the conductor lands 14a are connected to one another via through holes, via holes, and so on (not shown) to form a predetermined (desired) circuit.
Moreover, in the mounting area 10 of the printed wiring board 1, the surface insulating resin layer 16 is removed like a quadrilateral (e.g., a square), that is, a quadrilateral removed portion 17 is formed and the interlayer insulating resin layer 13 under the removed portion 17 is exposed in an area (central portion) other than the conductor lands 14a and immediately below the semiconductor device, the conductor lands 14a being disposed on the edge of the mounting area 10.
The method of manufacturing the printed wiring board 1 will be schematically described below.
To be specific, this manufacturing method is a method of manufacturing a printed wiring board having one of a single-layer structure and a multilayer structure, the method including the steps of: obtaining the conductor wiring layer by forming a wiring pattern on the conductor layer provided on at least one side of the core substrate; and forming the surface insulating resin layer on the conductor wiring layer on the outermost surface after repeatedly performing a predetermined number of times the steps of forming the interlayer insulating resin layer so as to cover the conductor wiring layer and forming the conductor wiring layer on the interlayer insulating resin layer, wherein the method further includes the step of forming, in the area for mounting the semiconductor device, the surface insulating resin layer and selectively removing a part of the surface insulating resin layer in the area other than the conductor land portions and immediately below the semiconductor device, the conductor land portions being bonded to the external electrodes of the semiconductor device.
Further, a single-layer structure is also included in the description of this manufacturing method and thus this manufacturing method is also applicable to a printed wiring board having a single-layer structure (in this case, the predetermined number of repetitions is one and the application of a single-layer structure similarly holds for embodiments described below).
According to the printed wiring board and the method of manufacturing the same, the central portion of the surface insulating resin layer 16 is removed like a quadrilateral, and thus an area on which the surface insulating resin layer 16 expands becomes quite small, thereby preventing a surface of the wiring board from coming into contact with the backside of the semiconductor device during reflow heating when a semiconductor device is mounted.
Although the removed portion 17 is shaped like a square in
Referring to
In First Embodiment, the surface insulating resin layer 16 on the interlayer insulating resin layer 13 is removed like a quadrilateral, whereas in Second Embodiment, a surface insulating resin layer 16 is removed like slits and the other configurations are identical to those of First Embodiment. Thus the different part will be mainly described below. The same constituent elements as those of First Embodiment are indicated by the same reference numerals and the explanation thereof is omitted.
As shown in
With this configuration, an area on which the surface insulating resin layer 16 expands is divided to reduce an amount of expansion of the surface insulating resin layer 16, so that during reflow heating when a semiconductor device is mounted, it is possible to prevent a surface of the wiring board, that is, the surface insulating resin layer 16 from coming into contact with the backside of the semiconductor device.
The method of manufacturing the printed wiring board 1 according to Second Embodiment is the same as that of First Embodiment and thus the explanation thereof is omitted.
Referring to
In First Embodiment, the surface insulating resin layer 16 on the interlayer insulating resin layer 13 is removed like a quadrilateral, whereas in Third Embodiment, a surface insulating resin layer 16 is removed in a gridlike fashion and the other configurations are identical to those of First Embodiment. Thus the different part will be mainly described below. The same constituent elements as those of First Embodiment are indicated by the same reference numerals and the explanation thereof is omitted.
As shown in
With this configuration, as in Second Embodiment, an area on which the surface insulating resin layer 16 expands is divided to reduce an amount of expansion of the surface insulating resin layer 16, so that during reflow heating when a semiconductor device is mounted, it is possible to prevent a surface of the wiring board, that is, the surface insulating resin layer 16 from coming into contact with the backside of the semiconductor device.
The method of manufacturing the printed wiring board 1 according to Third Embodiment is also the same as that of First Embodiment and thus the explanation thereof is omitted.
In one of Second and Third Embodiments, the removed portion is shaped like vertical slits or formed in a grid-like fashion. The shape of the removed portion may be horizontal or diagonal slits and a diagonal mesh. Further, it is not necessary to unify the dimensions and angles of these slits, grid, and mesh.
The configuration of one of Second and Third Embodiments is effective when the hygroscopicity and reliability of the printed wiring board are adversely affected and the configuration of First Embodiment is not applicable.
Referring to
In First Embodiment, the surface insulating resin layer 16 on the interlayer insulating resin layer 13 is removed like a quadrilateral, whereas in Fourth Embodiment, a conductor wiring layer 14b formed under a surface insulating resin layer 16 is partially removed and the other configurations are identical to those of First Embodiment. Thus the different part will be mainly described below. The same constituent elements as those of First Embodiment are indicated by the same reference numerals and the explanation thereof is omitted.
As shown in
With this configuration, the surface insulating resin layer 16 on the conductor wiring layer (outer layer) 14b is neither even nor flat. The surface insulating resin layer 16 is recessed (recessed portions are formed) by the removed portion 15 and is seemingly divided like the conductor wiring layers (outer layer) 14b.
Therefore, an area on which the surface insulating resin layer 16 expands is divided to reduce an amount of expansion of the surface insulating resin layer 16, so that during reflow heating when a semiconductor device is mounted, it is possible to prevent a surface of the wiring board, that is, the surface insulating resin layer 16 from coming into contact with the backside of the semiconductor device.
The configuration and manufacturing method of the printed wiring board 1 will be schematically described below.
To be specific, the printed wiring board is one of a single-layer printed wiring board and a multilayer printed wiring board in which the conductor wiring layer and the interlayer insulating resin layer are stacked or alternately stacked on at least one side of a core substrate and the conductor wiring layer on the outermost surface is covered with the surface insulating resin layer, wherein in an area for mounting a semiconductor device, a part of the conductor wiring layer on the outermost surface is selectively removed and the surface insulating resin layer formed on the removed area (removed portion) is recessed in an area other than the conductor land portions and immediately below the semiconductor device, the conductor land portions being bonded to the external electrodes of the semiconductor device.
Moreover, the manufacturing method is a method of manufacturing a printed wiring board having one of a single-layer structure and a multilayer structure, the method including the steps of: obtaining the conductor wiring layer by forming a wiring pattern on the conductor layer provided on at least one side of the core substrate; and forming the surface insulating resin layer on the conductor wiring layer on the outermost surface after repeatedly performing a predetermined number of times the steps of forming the interlayer insulating resin layer so as to cover the conductor wiring layer and forming the conductor wiring layer on the interlayer insulating resin layer, wherein the method further includes the step of forming, in the area for mounting the semiconductor device, the conductor wiring layer on the outermost surface and selectively removing a part of the conductor wiring layer on the outermost surface in the area other than the conductor land portions and immediately below the semiconductor device, the conductor land portions being bonded to the external electrodes of the semiconductor device.
Referring to
In Fourth Embodiment, the conductor wiring layer 14b on the interlayer insulating resin layer 13 is removed in a grid-like fashion like grooves having a predetermined width. Conversely, in Fifth Embodiment, a conductor wiring layer 14b formed under a surface insulating resin layer 16 is formed in a grid-like fashion. Since the other configurations are identical to those of Fourth Embodiment, the different part will be mainly described below. The same constituent elements as those of Fourth Embodiment (that is, First Embodiment) are indicated by the same reference numerals and the explanation thereof is omitted.
As shown in
With this configuration, the same effect as Fourth Embodiment can be obtained.
In Fourth Embodiment, the conductor wiring layer (outer layer) 14b is shaped like a square. The conductor wiring layer 14b may be rectangular, polygonal, and circular.
Although the conductor wiring layer (outer layer) 14b is formed in a grid-like fashion in Fifth Embodiment, the conductor wiring layer 14b may be shaped like slits and a diagonal mesh. It is not necessary to unify the dimensions and angles of the slits, grid, and mesh. Further, the conductor wiring layer (outer layer) 14b may be dummy wiring not electrically connected to the semiconductor device, that is, conductor lands 14a (corresponding to claims 4 and 7).
Fourth and Fifth Embodiments are effective, for example, when it is necessary to improve heat dissipation and electrical characteristics more than First to Third Embodiments.
Referring to
In Fourth Embodiment, the conductor wiring layer 14b formed on the interlayer insulating resin layer 13 and under the surface insulating resin layer 16 is removed in a grid-like fashion, whereas in Sixth Embodiment, a part of a surface insulating resin layer 16 is further removed on a plurality of conductor wiring layers 14b formed inside a grid-like pattern and the other configurations are identical to those of Fourth Embodiment. Thus the different part will be mainly described below. The same constituent elements as those of Fourth Embodiment are indicated by the same reference numerals and the explanation thereof is omitted.
As shown in
With this configuration, the area of the surface insulating resin layer 16 on the conductor wiring layers 14b is minimized. Thus an amount of expansion can be reduced more than Fourth Embodiment, and during reflow heating when a semiconductor device is mounted, it is possible to prevent a surface of the wiring board from coming into contact with the backside of the semiconductor device. Further, the conductor wiring layer (outer layer) 14b may be dummy wiring not electrically connected to the semiconductor device, that is, conductor lands 14a (corresponding to claims 4 and 7).
The configuration and manufacturing method of a printed wiring board 1 will be schematically described below.
To be specific, the printed wiring board is one of a single-layer printed wiring board and a multilayer printed wiring board in which the conductor wiring layer and the interlayer insulating resin layer are stacked or alternately stacked on at least one side of a core substrate and the outermost conductor wiring layer is covered with the surface insulating resin layer, wherein in an area for mounting a semiconductor device, a part of the surface insulating resin layer formed on one of the interlayer insulating resin layer and the conductor wiring layer and a part of the outermost conductor wiring layer are selectively removed in an area other than the conductor land portions and immediately below the semiconductor device, the conductor land portions being bonded to the external electrodes of the semiconductor device.
Further, the manufacturing method is a method of manufacturing a printed wiring board having one of a single-layer structure and a multilayer structure, the method including the steps of: obtaining the conductor wiring layer by forming a wiring pattern on the conductor layer provided on at least one side of the core substrate; and forming the surface insulating resin layer on the outermost conductor wiring layer after repeatedly performing a predetermined number of times the steps of forming the interlayer insulating resin layer so as to cover the conductor wiring layer and forming the conductor wiring layer on the interlayer insulating resin layer, wherein the method further includes the steps of forming, in an area for mounting the semiconductor device, the surface insulating resin layer and selectively removing a part of the surface insulating resin layer in an area other than the conductor land portions and immediately below the semiconductor device, the conductor land portions being bonded to the external electrodes of the semiconductor device; and forming the outermost conductor wiring layer and selectively removing a part of the outermost conductor wiring layer.
A method of manufacturing the printed wiring board according to Sixth Embodiment will be specifically described later.
Referring to
In First Embodiment, the surface insulating resin layer 16 on the interlayer insulating resin layer 13 is removed like a quadrilateral, whereas in Seventh Embodiment, through holes or via holes are formed inside conductor lands. The other configurations are identical to those of First Embodiment and thus the different part will be mainly described below. The same constituent elements as those of First Embodiment are indicated by the same reference numerals and the explanation thereof is omitted.
As shown in
Since a surface insulating resin layer 16 is not formed on the through holes 18 in this configuration, an area on which the surface insulating resin layer 16 expands is divided and an amount of expansion can be reduced.
The through holes 18 may be dummy wiring not electrically connected to a semiconductor device and via holes may be formed instead of the through holes (corresponding to claim 10).
The configuration and manufacturing method of the printed wiring board 1 will be schematically described below.
To be specific, the printed wiring board is one of a single-layer printed wiring board and a multilayer printed wiring board in which the conductor wiring layer and the interlayer insulating resin layer are stacked or alternately stacked on at least one side of a core substrate and the outermost conductor wiring layer is covered with the surface insulating resin layer, wherein in an area for mounting a semiconductor device, ones of a plurality of through holes and a plurality of via holes are formed in an area other than the conductor land portions and immediately below the semiconductor device, the conductor land portions being bonded to the external electrodes of the semiconductor device.
Further, the manufacturing method is a method of manufacturing a printed wiring board having one of a single-layer structure and a multilayer structure, the method including the steps of: obtaining the conductor wiring layer by forming a wiring pattern on the conductor layer provided on at least one side of the core substrate; and forming the surface insulating resin layer on the outermost conductor wiring layer after repeatedly performing a predetermined number of times the steps of forming the interlayer insulating resin layer so as to cover the conductor wiring layer and forming the conductor wiring layer on the interlayer insulating resin layer, wherein the method further includes the step of forming, in an area for mounting the semiconductor device, one of a through hole and a via hole in an area other than the conductor land portions and immediately below the semiconductor device before the step of forming the surface insulating resin layer, the conductor land portions being bonded to the external electrodes of the semiconductor device.
Referring to
In First Embodiment, the surface insulating resin layer 16 on the interlayer insulating resin layer 13 is removed like a quadrilateral, whereas in Eighth Embodiment, another surface insulating resin layer is formed on a surface insulating resin layer and the other configurations are identical to those of First Embodiment. Thus the different part will be mainly described below. The same constituent elements as those of First Embodiment are indicated by the same reference numerals and the explanation thereof is omitted.
As shown in
The second surface insulating resin layer 19 has a lower coefficient of thermal expansion than the first surface insulating resin layer 16 formed under the second surface insulating resin layer 19. As the first surface insulating resin layer 16, a photoresist called a solder resist is frequently used. As the second surface insulating resin layer 19, a solder resist (having a low coefficient of thermal expansion) is used as in the first surface insulating resin layer 16. Alternatively, a thermosetting resin containing a filler, a metal thin film, and so on are used as the second surface insulating resin layer 19.
As described above, since the second surface insulating resin layer 19 having a low coefficient of thermal expansion is formed on the first surface insulating resin layer 16, it is possible to reduce the amount of expansion of the surface insulating resin layer 16 formed under the second surface insulating resin layer 19. Therefore, during reflow heating when a semiconductor device is mounted, it is possible to prevent a surface of the wiring board from coming into contact with the backside of the semiconductor device.
The configuration and manufacturing method of the printed wiring board 1 will be schematically described below.
The printed wiring board is one of a single-layer printed wiring board and a multilayer printed wiring board in which the conductor wiring layer and the interlayer insulating resin layer are stacked or alternately stacked on at least one side of a core substrate and the outermost conductor wiring layer is covered with the surface insulating resin layer, wherein in an area for mounting a semiconductor device, the second surface insulating resin layer is formed on the first surface insulating resin layer in an area other than the conductor land portions and immediately below the semiconductor device, the conductor land portions being bonded to the external electrodes of the semiconductor device, and the second surface insulating resin layer has a lower coefficient of thermal expansion than the first surface insulating resin layer.
Further, the manufacturing method is a method of manufacturing a printed wiring board having one of a single-layer structure and a multilayer structure, the method including the steps of: obtaining the conductor wiring layer by forming a wiring pattern on the conductor layer provided on at least one side of the core substrate; and forming the first surface insulating resin layer on the outermost conductor wiring layer after repeatedly performing a predetermined number of times the steps of forming the interlayer insulating resin layer so as to cover the conductor wiring layer and forming the conductor wiring layer on the interlayer insulating resin layer, wherein the method further includes the step of forming, in an area for mounting the semiconductor device, the second surface insulating resin layer on the first surface insulating resin layer in an area other than the conductor land portions and immediately below the semiconductor device, the conductor land portions being bonded to the external electrodes of the semiconductor device, and the second surface insulating resin layer has a lower coefficient of thermal expansion than the first surface insulating resin layer.
Although the second surface insulating resin layer 19 is formed on the first surface insulating resin layer 16 in Eighth Embodiment, the second surface insulating resin layer 19 may be formed on the removed portions 17 and 15 described in First to Third Embodiments (corresponding to claim 12, claim 14, and claim 20).
Finally, referring to
First, as shown in
Next, as shown in
After that, as shown in
Next, as shown in
Next, as shown in
After that, as shown in
According to this manufacturing method, in the mounting area 10 for a semiconductor device, the conductor wiring layer (outer layer) 14b is divided by removing the conductor wiring layer 14b in a grid-like fashion (removed portions 15) in the area other than the conductor lands 14a and immediately below the semiconductor device, so that the surface insulating resin layer 16 on the conductor wiring layer (outer layer) 14b is neither even nor flat. Since recessed portions 16a are formed by the removed portions 15, the surface insulating resin layer 16 is also seemingly divided like the conductor wiring layer (outer layer) 14b. Further, since the area of the surface insulating resin layer 16 on the conductor wiring layer 14b is also minimized, the amount of expansion of the surface insulating resin layer 16 is reduced, and during reflow heating when a semiconductor device is mounted, it is possible to prevent a surface of the wiring board from coming into contact with the backside of the semiconductor device, thereby improving yields and the quality and reliability of a mounting operation. The above manufacturing method was described by taking a laminated substrate as an example and is also applicable to a variety of printed substrates such as a built-up substrate.
A printed wiring board and a method of manufacturing the same according to the present invention can improve the quality and reliability of a mounting operation in high-density packaging. Thus the present invention is suitable for the miniaturization, thickness reduction, and improvement in functionality of information communications equipment, office electronic equipment, and so on.
Number | Date | Country | Kind |
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2006-186152 | Jul 2006 | JP | national |