Processing tools are used in the semiconductor industry to perform various processes to fabricate devices. A plasma tool generates an ion beam that may be used to deposit material on a substrate or to remove material from the substrate. Semiconductor fabrication has progressed into nanometer technology process nodes in pursuit of higher device density, higher performance, and lower costs, challenges from both fabrication and design issues have resulted in the development of three dimensional designs, such as gate all around (GAA) transistors. A GAA transistor comprises one or more nano-sheet or nano-wire channel regions having a gate wrapped around the nano-sheet or nano-wire. GAA transistors can reduce short channel effect.
Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.
An ion beam processing tool and one or more techniques for fabricating a semiconductor structure using the ion beam processing tool are provided herein. In some embodiments, the ion beam processing tool includes a plasma source and a grid arrangement positioned proximate the plasma source to generate an ion beam. A beam deflector is positioned adjacent the grid arrangement to deflect the ion beam to facilitate a tilted material removal process. A semiconductor structure includes a first nanostructure, such as a nanosheet transistor or nanowire transistor, and a second nanostructure. A spacer is between the first nanostructure and the second nanostructure. During a gate replacement process, the tilted material removal process is used to remove sidewall portions of the spacer to widen the gate cavity and provides a more flexible process window for forming the metal replacement gate.
For ease of illustration, the grid arrangement 104 is illustrated in expanded form in
According to some embodiments, a beam deflector 118 is positioned within the grid arrangement 104. The beam deflector 118 comprises a plurality of plates 120 positioned along the columnar paths defined by the apertures 106A, 108A, 110A, 112A of the grids 106, 108, 110, 112. A bias voltage applied across the plates 120 of the beam deflector 118 by the controller 105 causes deflection of the ion beam to generate a tilted ion beam. In some embodiments, the tilted ion beam is used for directional etching of features defined on the target 116. As illustrated in
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In some embodiments, the semiconductor structure 300 comprises nanostructure based transistors. Nanostructure is used herein to refer to substantially flat, nearly two-dimensional structures, such as sometimes referred to as nanosheets, as well as structures having two-dimensions that are similar in magnitude, such as sometimes referred to as nanowires.
In some embodiments, nanostructures 310A, 310B, 310C are formed by forming a stack of semiconductor material layers and performing an etch process to remove some of the stack of semiconductor material layers, thereby defining the nanostructures 310A, 310B, 310C. In some embodiments, the nanostructures 310A, 310B, 310C comprise semiconductor material layers 315 and sacrificial semiconductor layers 320. In some embodiments, the materials of the semiconductor material layers 315 are different than the materials of the sacrificial semiconductor layers 320 to provide etch selectivity and allow for removal of the sacrificial semiconductor layers 320.
In some embodiments, the semiconductor material layers 315 comprise the same material composition, and the sacrificial semiconductor layers 320 comprise the same material composition. In some embodiments, the semiconductor material layers 315 comprise substantially pure silicon, and the sacrificial semiconductor layers 320 comprise silicon-germanium (SixGe(1−x) where x ranges from 0.25 to 0.85).
In some embodiments, the number of semiconductor material layers 315 and sacrificial semiconductor layers 320 varies. In some embodiments, the order of the semiconductor material layers 315 and sacrificial semiconductor layers 320 varies. In some embodiments, thicknesses of the semiconductor material layers 315 and sacrificial semiconductor layers 320 vary, and the thicknesses need not be the same.
In some embodiments, an etch process is performed to remove some of the stack of semiconductor material layers 315 and sacrificial semiconductor layers 320 to define recesses between the nanostructures 310A, 310B, 310C and fins 325A, 325B are formed in the recesses. In some embodiments, the fins 325A, 325B have different widths. For example, the fin 325A may be wider than the fin 325B, thereby affecting the spacings between the nanostructures 310A, 310B, 310C. In some embodiments, the fin 325A comprises a cladding layer 326, a bottom liner 327, a sidewall liner 328, a center portion 329, and an inner layer 330. The fin 325B comprises the cladding layer 326, the bottom liner 327, the sidewall liner 328, and the inner layer 330. In some embodiments, the cladding layer 326 comprises the same material as the sacrificial semiconductor layers 320, for example, silicon germanium. In some embodiments, the sidewall liner 328 comprises a high-k dielectric material. As used herein, the term “high-k dielectric” refers to the material having a dielectric constant, k, greater than or equal to about 3.9, which is the k value of SiO2. The high-k dielectric material may be any suitable material. Examples of the high-k dielectric material include but are not limited to Al2O3, HfO2, ZrO2, La2O3, TiO2, SrTiO3, LaAlO3, Y2O3, Al2OxNy, HfOxNy, ZrOxNy, La2OxNy, TiOxNy, SrTiOxNy, LaAlOxNy, Y2OxNy, SiON, SiNx, a silicate thereof, and an alloy thereof. Each value of x is independently from 0.5 to 3, and each value of y is independently from 0 to 2. In some embodiments, the bottom liner 327 comprises a dielectric material that is not a high-k material, such as silicon nitride, or some other suitable dielectric material.
The center portion 329 may comprise one or more layers of a low-k material. A low-k dielectric material may comprise at least one of Si, O, C, H, or N, such as SiCOH, SiOC, SiOCN, or other suitable materials. Organic material such as polymers may be used for the low-k material. In some embodiments, the low-k dielectric material comprises one or more layers of a carbon-containing material, organo-silicate glass, a porogen-containing material, or combinations thereof. The low-k material may be formed by using, for example, at least one of chemical vapor deposition (CVD), low pressure CVD (LPCVD), atomic layer CVD (ALCVD), or a spin-on technology. In some embodiments, the center portion 329 of the fin 325A comprises multiple layers due to the width of the fin 325A. The inner layer 330 may comprise the same material as the center portion 329.
In some embodiments, the cladding layer 326 is formed by depositing a layer in a trench formed to separate the nanostructures 310A, 310B, 310C. In some embodiments, the bottom liner 327 is formed by forming a layer of material of the bottom liner 327 over the cladding layer 326, and the center portion 329 is formed by filling a remaining portion of the trench with the material of the center portion 329. The cladding layer 326300 is then planarized to remove portions of the material of the center portion 329 outside the trench. An etch process is performed to recess the material of the bottom liner 327, and the resulting recesses are filled with material of the sidewall liner 328 and the inner layer 330. The sidewall liner 328 may be a conformal layer, and the inner layer 330 may fill the remaining portions of the recess. Other structures and configurations of the fins 325A, 325B are within the scope of the present disclosure.
In some embodiments, sacrificial gate structures 331 are formed over the nanostructures 310A, 310B, 310C. In some embodiments, the sacrificial gate structures 331 comprise a first gate dielectric layer 332 and sacrificial gate electrodes 333. In some embodiments, the first gate dielectric layer 332 comprises a high-k dielectric material or other suitable dielectric material.
In some embodiments, the first gate dielectric layer 332 comprises a native oxide layer formed by exposure of the semiconductor structure 300 to oxygen at various points in the process flow, causing the formation of silicon dioxide on exposed surfaces of the nanostructures 310A, 310B, 310C. In some embodiments, an additional layer of dielectric material, such as a high-k dielectric material or other suitable material, is formed over the native oxide to form the first gate dielectric layer 332. According to some embodiments, the sacrificial gate structures 331 are formed by forming a layer of sacrificial material and a hard mask layer over the nanostructures 310A, 310B, 310C. In some embodiments, a patterning process is performed to pattern the hard mask layer corresponding to the pattern of gate structures to be formed, and an etch process is performed using the patterned hard mask layer to etch the layer of sacrificial material to define the sacrificial gate electrodes 333. In some embodiments, remaining portions of the hard mask layer form cap layers 335 over the sacrificial gate electrodes 333.
In some embodiments, a sidewall spacer 340 is formed adjacent the sacrificial gate structure 331. In some embodiments, the sidewall spacer 340 is formed by depositing a conformal spacer layer over the sacrificial gate structure 331 and performing an anisotropic etch process to remove portions of the spacer layer positioned on horizontal surfaces of the cap layers 335, and the nanostructures 310A, 310B, 310C. In some embodiments, the sidewall spacer 340 comprises the same material composition as the cap layer 335. In some embodiments, the sidewall spacer 340 comprises nitrogen and silicon or other suitable materials.
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In some embodiments, the source/drain regions 345 are formed in the nanostructures 310A, 310B, 310C after forming the sacrificial gate structures 331 and after forming the end spacers 342. In some embodiments, an epitaxial growth process is performed to form the source/drain regions 345.
In some embodiments, the dielectric layer 350 is formed over the nanostructures 310A, 310B, 310C and adjacent the sacrificial gate structures 331 after forming the source/drain regions 345. In some embodiments, a portion of the dielectric layer 350 is removed to expose the cap layers 335. In some embodiments, the dielectric layer 350 is planarized to expose the cap layers 335. In some embodiments, the dielectric layer 350 comprises silicon dioxide or a low-k material. Referring to
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In some embodiments, the phases described in
In some embodiments, the target 116 may be rotated during at least one of the deposition phase or the tilted material removal phases, or the target 116 may be maintained in a horizontal position during the deposition phase and the tilted material removal phases. Using the beam deflector 118 to provide a tilted material removal phase reduces pitch walking and etch asymmetry issues associated with a vertical etch using a tilted target. In some embodiments, the target may be tilted and rotated in combination with the beam tilting using the beam deflector 118 to provide a more flexible process window.
In some embodiments, the entire vertical portions of the sidewall liner 328 are removed from one or both of the fins 325A, 325B. For example, in
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In some embodiments, removing a portion of or all of the sidewall liner 328 increases the size of the gate cavities 355A, 355B, 355C, thereby increasing the process window for forming the gate structures 365A, 365B, 365C. Removing portions of the sidewall liner 328 also reduces capacitance. Using the beam deflector 318 to perform the tilted etch process reduces the likelihood of damage to the nanostructures 310A, 310B, 310C and serves to reduce issues with pitch walking and etch asymmetry.
Although not required, embodiments are described in the general context of “computer readable instructions” being executed by one or more computing devices. Computer readable instructions may be distributed via computer readable media (discussed below). Computer readable instructions may be implemented as program modules, such as functions, objects, Application Programming Interfaces (APIs), data structures, and the like, that perform particular tasks or implement particular abstract data types. Typically, the functionality of the computer readable instructions may be combined or distributed as desired in various environments.
In some embodiments, computing device 602 may include additional features and/or functionality. For example, computing device 602 may also include additional storage (e.g., removable and/or non-removable) including, but not limited to, magnetic storage, optical storage, and the like. Such additional storage is illustrated in
The term “computer readable media” as used herein includes computer storage media. Computer storage media includes volatile and nonvolatile, removable and non-removable media implemented in any method or technology for storage of information such as computer readable instructions or other data. Memory 608 and storage 610 are examples of computer storage media. Computer storage media includes, but is not limited to, RAM, ROM, electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, CD-ROM, Digital Versatile Disks (DVDs) or other optical storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium which can be used to store the desired information and which can be accessed by computing device 602. Any such computer storage media may be part of computing device 602.
Computing device 602 may also include communication connection(s) 616 that allows computing device 602 to communicate with other devices. Communication connection(s) 1516 may include, but is not limited to, a modem, a Network Interface Card (NIC), an integrated network interface, a radio frequency transmitter/receiver, an infrared port, a universal serial bus (USB) connection, or other interfaces for connecting computing device 602 to other computing devices. Communication connection(s) 616 may include a wired connection or a wireless connection. Communication connection(s) 616 may transmit and/or receive communication media.
The term “computer readable media” may include communication media. Communication media typically embodies computer readable instructions or other data in a “modulated data signal” such as a carrier wave or other transport mechanism and includes any information delivery media. The term “modulated data signal” may include a signal that has one or more of its characteristics set or changed in such a manner as to encode information in the signal.
Computing device 602 may include input device(s) 614 such as keyboard, mouse, pen, voice input device, touch input device, infrared cameras, video input devices, and/or any other input device. Output device(s) 612 such as one or more displays, speakers, printers, and/or any other output device may also be included in computing device 602. Input device(s) 614 and output device(s) 612 may be connected to computing device 602 via a wired connection, wireless connection, or any combination thereof. In some embodiments, an input device or an output device from another computing device may be used as input device(s) 614 or output device(s) 612 for computing device 602.
Components of computing device 602 may be connected by various interconnects, such as a bus. Such interconnects may include a Peripheral Component Interconnect (PCI), such as PCI Express, a Universal Serial Bus (USB), firewire (IEEE 1394), an optical bus structure, and the like. In some embodiments, components of computing device 602 may be interconnected by a network. For example, memory 608 may be comprised of multiple physical memory units located in different physical locations interconnected by a network.
Those skilled in the art will realize that storage devices utilized to store computer readable instructions may be distributed across a network. For example, a computing device 620 accessible via a network 618 may store computer readable instructions to implement one or more embodiments provided herein. Computing device 602 may access computing device 620 and download a part or all of the computer readable instructions for execution. Alternatively, computing device 602 may download pieces of the computer readable instructions, as needed, or some instructions may be executed at computing device 602 and some at computing device 620.
In some embodiments, an ion beam processing tool includes a plasma source, a grid arrangement positioned proximate the plasma source to generate an ion beam, a beam deflector positioned adjacent the grid arrangement, and a controller configured to control the beam deflector to deflect the ion beam to generate a tilted ion beam.
In some embodiments, a method includes generating an ion beam, directing the ion beam at a target, deflecting the ion beam in a first direction to remove a first portion of material from the target, and deflecting the ion beam in a second direction different than the first direction to remove a second portion of material from the target.
In some embodiments, a method for forming a semiconductor structure includes forming a first nanostructure and forming a second nanostructure. A first fin is formed between the first nanostructure and the second nanostructure. A sacrificial gate structure is formed over the first nanostructure, the second nanostructure, and the first fin. A portion of the sacrificial gate structure is removed to form a first gate cavity over a portion of the first nanostructure and expose a first sidewall of the first fin and to form a second gate cavity over a portion of the second nanostructure and expose a second sidewall of the first fin. An ion beam processing tool is employed. The ion beam processing tool includes a beam deflector configured to perform a tilted etch process to remove a first portion of the first fin along the first sidewall and to remove a second portion of the first fin along the second sidewall. A first gate structure is formed in the first gate cavity and a second gate structure in the second gate cavity after the tilted etch process.
The foregoing outlines features of several embodiments so that those of ordinary skill in the art may better understand various aspects of the present disclosure. Those of ordinary skill in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of various embodiments introduced herein. Those of ordinary skill in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.
Although the subject matter has been described in language specific to structural features or methodological acts, it is to be understood that the subject matter of the appended claims is not necessarily limited to the specific features or acts described above. Rather, the specific features and acts described above are disclosed as example forms of implementing at least some of the claims.
Various operations of embodiments are provided herein. The order in which some or all of the operations are described should not be construed to imply that these operations are necessarily order dependent. Alternative ordering will be appreciated having the benefit of this description. Further, it will be understood that not all operations are necessarily present in each embodiment provided herein. Also, it will be understood that not all operations are necessary in some embodiments.
It will be appreciated that layers, features, elements, etc. depicted herein are illustrated with particular dimensions relative to one another, such as structural dimensions or orientations, for example, for purposes of simplicity and ease of understanding and that actual dimensions of the same differ substantially from that illustrated herein, in some embodiments. Additionally, a variety of techniques exist for forming the layers, regions, features, elements, etc. mentioned herein, such as at least one of etching techniques, planarization techniques, implanting techniques, doping techniques, spin-on techniques, sputtering techniques, growth techniques, or deposition techniques such as chemical vapor deposition (CVD), for example.
Moreover, “exemplary” is used herein to mean serving as an example, instance, illustration, etc., and not necessarily as advantageous. As used in this application, “or” is intended to mean an inclusive “or” rather than an exclusive “or”. In addition, “a” and “an” as used in this application and the appended claims are generally be construed to mean “one or more” unless specified otherwise or clear from context to be directed to a singular form. Also, at least one of A and B and/or the like generally means A or B or both A and B. Furthermore, to the extent that “includes”, “having”, “has”, “with”, or variants thereof are used, such terms are intended to be inclusive in a manner similar to the term “comprising”. Also, unless specified otherwise, “first,” “second,” or the like are not intended to imply a temporal aspect, a spatial aspect, an ordering, etc. Rather, such terms are merely used as identifiers, names, etc. for features, elements, items, etc. For example, a first element and a second element generally correspond to element A and element B or two different or two identical elements or the same element.
Also, although the disclosure has been shown and described with respect to one or more implementations, equivalent alterations and modifications will occur to others of ordinary skill in the art based upon a reading and understanding of this specification and the annexed drawings. The disclosure comprises all such modifications and alterations and is limited only by the scope of the following claims. In particular regard to the various functions performed by the above described components (e.g., elements, resources, etc.), the terms used to describe such components are intended to correspond, unless otherwise indicated, to any component which performs the specified function of the described component (e.g., that is functionally equivalent), even though not structurally equivalent to the disclosed structure. In addition, while a particular feature of the disclosure may have been disclosed with respect to only one of several implementations, such feature may be combined with one or more other features of the other implementations as may be desired and advantageous for any given or particular application.