Claims
- 1. A programmable resistance memory element, comprising:a first dielectric material having a sidewall surface; a conductive layer formed over said sidewall surface; a second dielectric material formed over said conductive layer, wherein an edge of said conductive layer is exposed; a third dielectric material formed over said edge, said third dielectric material having an opening formed therethrough uncovering a portion of said edge; and a programmable resistance material disposed in said opening and in communication with said edge.
- 2. The memory element of claim 1, wherein said opening has a lateral dimension less than a photolithographic limit.
- 3. The memory element of claim 1, wherein said opening is a trench.
- 4. The memory element of claim 1, wherein said edge is annular.
- 5. The memory element of claim 1, wherein said edge is linear.
- 6. The memory element of claim 1, wherein said conductive layer is a sidewall layer.
- 7. The memory element of claim 1, wherein said conductive layer is a sidewall spacer or liner.
- 8. The memory element of claim 1, wherein said memory material is a phase-change material.
- 9. The memory element of claim 1, wherein said memory material comprises a chalcogen element.
RELATED APPLICATION INFORMATION
This application is a continuation-in-part of U.S. patent application Ser. No. 09/891,157, filed on Jun. 26, 2001.
US Referenced Citations (2)
Number |
Name |
Date |
Kind |
5952671 |
Reinberg et al. |
Sep 1999 |
A |
6031287 |
Harshfield |
Feb 2000 |
A |
Continuations (1)
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Number |
Date |
Country |
Parent |
09/891157 |
Jun 2001 |
US |
Child |
10/072369 |
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US |