Push-pull programmable logic device cell

Abstract

A memory cell includes a non-volatile p-channel transistor having a source coupled to a first potential, a drain, and a gate. A non-volatile n-channel transistor has a source coupled to a second potential, a drain, and a gate. A switch transistor has a gate coupled to a switch node, a source, and a drain. A stress transistor has a source and drain coupled between the drain of the non-volatile p-channel transistor and the drain of the non-volatile n-channel transistor, the stress transistor having a gate coupled to a gate bias circuit. Where one of the first or second potentials is a bit line, an isolation transistor is coupled between the other of the second potentials and one of the non-volatile transistors.

Description

BACKGROUND

1. Field of the Invention

The present invention relates to non-volatile memory cells in push-pull configuration. More particularly, the present invention relates to non-volatile memory cells in push-pull configuration that may be employed in FPGA devices.

2. The Prior Art

Push-pull non-volatile memory cells for FPGAs have been previously proposed, as shown by illustrative examples in FIGS. 1 and 2. As shown in both FIGS. 1 and 2, a basic push-pull non-volatile memory cell for use in an FPGA device includes a non-volatile p-channel memory transistor 10 connected in series with a non-volatile n-channel memory transistor 12. The common drain connections of the non-volatile p-channel memory transistor 10 and the non-volatile n-channel memory transistor 12 are connected to the gate of a volatile n-channel switch transistor 14 that is used to selectively make connections between circuit nets in the FPGA depending on the state of the memory cell. The push-pull non-volatile memory cell shown in FIG. 1 employs separate floating gates for the non-volatile p-channel memory transistor 10 and the non-volatile n-channel memory transistor 12, as well a separate control gate lines for both devices. The push-pull non-volatile memory cell shown in FIG. 2 employs a common floating gate for both the non-volatile p-channel memory transistor 10 and the non-volatile n-channel memory transistor 12, and a common control gate line for both devices.

When non-volatile p-channel memory transistor 10 is turned off and non-volatile n-channel memory transistor 12 is turned on, there is a low voltage at the gate of volatile n-channel switch transistor 14, which remains turned off. Conversely, when non-volatile p-channel memory transistor 10 is turned on and non-volatile n-channel memory transistor 12 is turned off, there is a high voltage at the gate of volatile n-channel switch transistor 14, which is then turned on.

In order for volatile n-channel switch transistor 14 to pass a high logic signal of around 1.5V, the voltage on its gate must be in excess of 2.5 volts. When n-channel memory transistor 12 is turned off, its drain is at a voltage of between about 2.5V and 3.3V and its source is at 0V. When p-channel memory transistor 12 is turned off, its drain is at a voltage of between about 0V and about 0.5V and its source is at voltage such as 2.5V or 3.3V. Persons of ordinary skill in the art will observe that the one of non-volatile p-channel memory transistor 10 and non-volatile n-channel memory transistor 12 that is turned off in the push-pull memory cell must be designed to tolerate a V_ds of more than 2.5V for a period greater than 20 years for the device to have an acceptable lifetime. For many non-volatile memory devices this can cause the off device to degrade over time.

Prior art patents disclose full push-pull non-volatile memory cells, however it is not believed that there is an actual product employing such a cell has not been reported.

There remains a need for a push-pull non-volatile memory cell in which the volatile n-channel switch transistor is able to pass a high logic signal of around 1.5V and in which the memory transistor that is turned off in the push-pull memory cell can tolerate a V_ds of more than 2.5V over the lifetime of the device.

BRIEF DESCRIPTION

According to one aspect of the present invention, stress may be reduced in one or both of the non-volatile transistors in a push-pull memory cell by providing at least one stress transistor in the memory cell. In the illustrative embodiments disclosed herein, a stress transistor may be provided between either the non-volatile n-channel transistor and the switch transistor, the non-volatile p-channel transistor and the switch transistor, or between both the non-volatile n-channel transistor and the switch transistor and the non-volatile p-channel transistor and the switch transistor. In other illustrative embodiments, a stress transistor may be provided between either the non-volatile n-channel transistor and ground, or the non-volatile p-channel transistor and V_DD.

According to another aspect of the present invention, a memory cell includes complementary pair of non-volatile transistors. A switch transistor has a source, a drain, and a gate coupled to the switch node and to the drain of the non-volatile p-channel transistor. An isolation transistor has a source and drain coupled between one of the power supply potentials and the source of one of the non-volatile transistors. The power supply potential may function as a global line.

BRIEF DESCRIPTION OF THE DRAWING FIGURES

FIG. 1 is a schematic diagram of a first exemplary prior art push-pull non-volatile memory cell.

FIG. 2 is a schematic diagram of another exemplary prior art push-pull non-volatile memory cell.

FIGS. 3A through 3C are schematic diagrams of illustrative push-pull non-volatile memory cells that show various aspects of the present invention.

FIGS. 4A and 4B are cross sectional diagrams illustrating programming of push-pull memory cells.

FIG. 5A is a schematic diagram of an exemplary prior art push-pull non-volatile memory cell. FIGS. 5B and 5C are schematic diagrams of illustrative push-pull non-volatile memory cells that show various aspects of the present invention as compared with the prior art.

FIGS. 6A and 6B are schematic diagrams of illustrative push-pull non-volatile memory cells that show other various aspects of the present invention.

FIG. 7 is a set of a set of four tables that provides illustrative voltages for the various nodes of the circuits shown in FIGS. 3A, 3B, 3C, 5B, 5C, 6A, and 6B.

DETAILED DESCRIPTION

Persons of ordinary skill in the art will realize that the following description of the present invention is illustrative only and not in any way limiting. Other embodiments of the invention will readily suggest themselves to such skilled persons.

The problem encountered in prior-art non-volatile push-pull memory cells can be alleviated by placing at least one additional transistor in the cell order to limit the V_ds of the non-volatile p-channel transistor, the non-volatile n-channel transistor, or both to around 0.5V and still allow the output to the gate of the switch transistor to be either at least a full 2.5V or even higher to fully turn on the switch transistor or at ground to fully turn off the switch transistor. In some embodiments, stress is relieved to the non-volatile p-channel transistor, the non-volatile n-channel transistor, or both.

Referring now to FIG. 3A, a schematic diagram shows an illustrative push-pull non-volatile memory cell 20 in order to show various aspects of the present invention. Memory cell 20 includes non-volatile n-channel transistor 22, non-volatile p-channel transistor 24, and volatile n-channel switch transistor 26. Non-volatile n-channel transistor 22 has its source coupled to ground and its drain coupled to the gate of volatile n-channel switch transistor 26. Non-volatile p-channel transistor 24 has its source coupled to the V_DD supply (in this example assumed to be 3.3V) and its drain coupled to the source of a p-channel isolation transistor 28. The drain of p-channel isolation transistor 28 is coupled to the drain of non-volatile n-channel transistor 22 and the gate of volatile n-channel switch transistor 26.

The gate of non-volatile n-channel transistor 22 is coupled to a gate line 30. The gate of non-volatile p-channel transistor 24 is coupled to a gate line 32. The gate of p-channel isolation transistor 28 is coupled to a gate line 34.

Referring now to FIG. 3B, a schematic diagram shows another illustrative push-pull non-volatile memory cell 40 in order to show various aspects of the present invention. Memory cell 40 includes non-volatile n-channel transistor 42, non-volatile p-channel transistor 44, and volatile n-channel switch transistor 46. Non-volatile p-channel transistor 44 has its source coupled to V_DD and its drain coupled to the gate of volatile n-channel switch transistor 46. Non-volatile n-channel transistor 42 has its source coupled to ground and its drain coupled to the source of an n-channel isolation transistor 48. The drain of n-channel isolation transistor 48 is coupled to the drain of non-volatile p-channel transistor 44 and the gate of volatile n-channel switch transistor 46.

The gate of non-volatile n-channel transistor 42 is coupled to a gate line 50. The gate of non-volatile p-channel transistor 44 is coupled to a gate line 52. The gate of n-channel isolation transistor 48 is coupled to a gate line 54.

In the memory cell 20 of FIG. 3A, stress may be reduced on non-volatile p-channel transistor 24 when the memory cell is in the state where non-volatile p-channel memory transistor 24 is turned off, non-volatile n-channel memory transistor 22 is turned on, and volatile n-channel switch transistor 26 is turned off because its gate is at or near ground. By biasing gate line 34 of p-channel isolation transistor 28 at, for example, 2.3V, the drain of p-channel memory transistor 24 will be at a voltage of at least about 2.8V, and the V_ds of p-channel memory transistor 24 will be at a voltage no higher than about 0.5V. In this case, because n-channel memory transistor 22 is turned on, its V_ds will also be at a voltage no higher than about 0.5V.

In the memory cell 40 of FIG. 3B, stress may be reduced on non-volatile n-channel transistor 42 when the memory cell is in the state where non-volatile p-channel memory transistor 44 is turned on, non-volatile n-channel memory transistor 42 is turned off, and volatile n-channel switch transistor 46 is turned on because its gate is at or near V_DD. By biasing gate line 54 of n-channel isolation transistor 48 at, for example, 1V, the drain of n-channel memory transistor 42 will be at a voltage no greater than about 0.5V, and the V_ds of n-channel memory transistor 42 will be at a voltage no higher than about 0.5V. In this case, because p-channel memory transistor 44 is turned on, its V_ds will also be at a voltage no higher than about 0.5V.

Referring now to FIG. 3C, a schematic diagram shows another illustrative push-pull non-volatile memory cell 60 in order to show other aspects of the present invention. Memory cell 60 includes non-volatile n-channel transistor 62, non-volatile p-channel transistor 64, and volatile n-channel switch transistor 66. Non-volatile p-channel transistor 64 has its source coupled to V_DD. Non-volatile n-channel transistor 62 has its source coupled to ground. The drain of non-volatile n-channel transistor 62 is coupled to the gate of volatile n-channel switch transistor 66 through n-channel isolation transistor 68. The drain of non-volatile p-channel transistor 64 is coupled to the gate of volatile n-channel switch transistor 66 through p-channel isolation transistor 70.

The gate of non-volatile n-channel transistor 62 is coupled to a gate line 72. The gate of non-volatile p-channel transistor 64 is coupled to a gate line 74. The gate of n-channel isolation transistor 68 is coupled to a gate line 76, and the gate of p-channel isolation transistor 70 is coupled to a gate line 78.

In the memory cell 60 of FIG. 3C, stress may be reduced on both non-volatile n-channel transistor 62 and non-volatile p-channel transistor 64. Stress may be reduced on non-volatile n-channel transistor 62 when the memory cell is in the state where non-volatile p-channel memory transistor 64 is turned on, non-volatile n-channel memory transistor 62 is turned off, and volatile n-channel switch transistor 66 is turned on because its gate is at or near V_DD. By biasing gate line 76 of n-channel isolation transistor 68 at, for example, 1V, and gate line 78 of p-channel isolation transistor 70 at, for example, 2.3V, the drain of n-channel memory transistor 62 will be at a voltage no greater than about 0.5V, and the V_ds of n-channel memory transistor 62 will be at a voltage no higher than about 0.5V. In this case, because p-channel memory transistor 64 is turned on, its V_ds will also be at a voltage no higher than about 0.5V.

Likewise, stress may be reduced on non-volatile p-channel transistor 64 when the memory cell is in the state where non-volatile p-channel memory transistor 64 is turned off, non-volatile n-channel memory transistor 62 is turned on, and volatile n-channel switch transistor 66 is turned off because its gate is at or near ground. In the above example where gate line 76 of n-channel isolation transistor 68 is biased at, for example, 1V, and gate line 78 of p-channel isolation transistor 70 is biased at, for example, 2.3V, the drain of p-channel memory transistor 64 will be at a voltage of at least about 2.8V, and the V_ds of p-channel memory transistor 64 will be at a voltage no higher than about 0.5V. In this case, n-channel memory transistor 62 is turned on, and its V_ds will also be at a voltage no higher than about 0.5V.

Referring now to FIGS. 4A and 4B, cross sectional diagrams illustrate typical potentials employed when programming non-volatile push-pull memory cells to turn off either the non-volatile p-channel transistor or the non-volatile n-channel transistor. Persons of ordinary skill in the art will observe that in either case, the sources of both the non-volatile p-channel transistor and the non-volatile n-channel transistor are at the same potential.

In FIG. 4A, the sources, 80 and 82, respectively, of both the non-volatile n-channel transistor 84 in the p-well 86 and the non-volatile p-channel transistor 88 in the n-well 90 are at −3.8V and in FIG. 4B, the sources 80 and 82, respectively, of both the non-volatile n-channel transistor and the non-volatile p-channel transistor are at +3.8V. In both FIGS. 4A and 4B it may also be seen that the non-volatile n-channel transistor 84 and the non-volatile p-channel transistor 88 each have a gate potential (−6.2V and 0V, respectively) that fully inverts both channels. Therefore both the non-volatile n-channel transistor 84 and the non-volatile p-channel transistor 88 are in the “on” state and therefore represent a DC path between the sources of both devices because both devices have previously been erased.

Under these conditions, it is clear that both the source bit line 92 of the non-volatile n-channel transistor 84 and the source bit line 94 of the non-volatile p-channel transistor 88 must be distinct from all other bit lines therefore requiring two bit lines for each column (as shown in prior-art FIG. 5A). Even though the one of the non-volatile p-channel transistor and the non-volatile n-channel transistor that is not being programmed can in fact be turned off, eliminating the connection between the two bit lines, this provides no advantage because the source 92 of the non-volatile n-channel transistor 84 needs to be decoded when it is being programmed and the source 94 of the non-volatile p-channel transistor 88 needs to be decoded when it is being programmed. Thus, two bit lines per cell are still required.

Since both the non-volatile n-channel transistor 84 and the non-volatile p-channel transistor 88 are turned on, only one bit line is required to program the memory cell. If the source of one of the non-volatile n-channel transistor 84 and the non-volatile p-channel transistor 88 could be isolated from the voltage supplying its source terminal, only one bit line would be needed. This can be accomplished by adding an isolation transistor as provided by another aspect of the present invention.

Referring now to FIGS. 5B and 5C, it may be seen that an isolation transistor may be added to isolate one of the non-volatile p-channel transistor and the non-volatile n-channel transistor from the bit line, allowing a global line to be used.

Referring now to FIG. 5B, memory cell 100 is shown to include non-volatile n-channel transistor 102, non-volatile p-channel transistor 104, and volatile n-channel switch transistor 106. Non-volatile p-channel transistor 104 has its source coupled to an array V_DD line through a p-channel isolation transistor 108 and its drain coupled to the gate of volatile n-channel switch transistor 106. Non-volatile n-channel transistor 102 has its source coupled to bit line 116 and its drain coupled to the gate of volatile n-channel switch transistor 106.

The gate of non-volatile n-channel transistor 102 is coupled to a gate line 110. The gate of non-volatile p-channel transistor 104 is coupled to a gate line 112. The gate of p-channel isolation transistor 108 is coupled to a gate line 114.

In the memory cell 100, non-volatile p-channel transistor 104 is coupled through p-channel isolation transistor 108 so its source can be coupled to a common line V_DD. The addition of a single p-channel isolation transistor 108 allows making a trade off between metal complexity and the extra layout area required by the presence of a simple volatile p-channel transistor added to the cell.

Referring now to FIG. 5C, memory cell 120 is shown to include non-volatile n-channel transistor 122, non-volatile p-channel transistor 124, and volatile n-channel switch transistor 126. Non-volatile n-channel transistor 122 has its source coupled to ground through an n-channel isolation transistor 128 and its drain coupled to the gate of volatile n-channel switch transistor 126. Non-volatile p-channel transistor 124 has its source coupled to bit line 136 and its drain coupled to the gate of volatile n-channel switch transistor 126.

The gate of non-volatile n-channel transistor 122 is coupled to a gate line 130. The gate of non-volatile p-channel transistor 124 is coupled to a gate line 132. The gate of n-channel isolation transistor 128 is coupled to a gate line 134.

In the memory cell 120, non-volatile n-channel transistor 122 is coupled through n-channel isolation transistor 128 so its source can be a common line ground. The addition of a single n-channel isolation transistor 128 allows making a trade off between metal complexity and the extra layout area required by the presence of a simple volatile n-channel transistor isolation transistor 128 added to the cell.

As will be appreciated by persons of ordinary skill in the art, both the arrangements of FIGS. 5B and 5C both provide a single-bit-line solution. The programming channel voltage is merely passed from the bit line directly to the adjacent non-volatile memory transistor device or is passed to the complementary non-volatile memory transistor device through the on device.

Referring now to FIGS. 6A and 6B, schematic diagrams of illustrative push-pull non-volatile memory cells show other various aspects of the present invention. Because FIGS. 6A and 6B include some of the same devices as shown in FIGS. 3A and 3B and FIGS. 5B and 5C, devices in FIGS. 6A and 6B corresponding to devices in FIGS. 3A and 3B and FIGS. 5B and 5C will be designated using the same reference numerals as used in FIGS. 3A and 3B and FIGS. 5B and 5C.

More specifically, FIGS. 6A and 6B illustrate an embodiment of the present invention in which one of the bit lines shown in FIG. 5A. In the cell shown in FIG. 5A, two bit lines are shown, one connected to the source of the non-volatile p-channel transistors and one connected to the sources of the non-volatile n-channel transistors in an array. Both of these bit lines must be decoded as the transistor channels will be on during programming, meaning that both bit lines must be at the same potential to avoid drawing DC power. Since approximately ½ the programming voltage comes from the bit lines, the bit lines must be decoded, resulting in larger memory cell width.

According to one aspect of the present invention, an isolation transistor and a stress-relieving transistor are both added to the transistor stack in the memory cell. The isolation transistor may be either a p-channel transistor at the source of the non-volatile p-channel transistor, or an n-channel isolation transistor at the source of the non-volatile n-channel transistor. This additional transistor can be turned off during programming. By configuring the memory cell in this manner, only one addressed bit line is necessary. The other bit line can be a global line saving significant area. The function of the stress-relieving transistor was disclosed with reference to FIGS. 3A through 3C.

Referring now to FIG. 6A, memory cell 140 is shown to include non-volatile n-channel transistor 102, non-volatile p-channel transistor 104, and volatile n-channel switch transistor 106. Non-volatile n-channel transistor 102 has its source coupled to bit line 116 and its drain coupled to the gate of volatile n-channel switch transistor 106. Non-volatile p-channel transistor 104 has its drain coupled to the drain of non-volatile n-channel transistor 102 through p-channel transistor 28. In this respect, the embodiment of FIG. 6A is similar to the embodiment shown in FIG. 3A.

In addition to the p-channel transistor 28, memory cell 140 of FIG. 6A includes a p-channel isolation transistor 108 connected between the source of non-volatile p-channel transistor 104 and the array V_DD node 142. Non-volatile n-channel transistor 102 has its source coupled to bit line 116 and its drain coupled to the gate of volatile n-channel switch transistor 106.

The gate of non-volatile n-channel transistor 102 is coupled to a gate line 110. The gate of non-volatile p-channel transistor 104 is coupled to a gate line 112. The gate of p-channel isolation transistor 108 is coupled to a gate line 114. The gate of p-channel transistor 28 is coupled to a gate line 34.

In the memory cell 140, the source of non-volatile p-channel transistor 104 is coupled to array V_DD node 142 through p-channel isolation transistor 108 so that its source can be coupled to a common V_DD line. The addition of p-channel isolation transistor 108 allows making a trade off between metal complexity and the extra layout area required by the presence of a simple volatile p-channel transistor added to the cell. As in the embodiment of FIG. 3A, p-channel transistor 28 reduces stress on the non-volatile p-channel transistor 104 as previously described.

Referring now to FIG. 5C, memory cell 150 is shown to include non-volatile n-channel transistor 122, non-volatile p-channel transistor 124, and volatile n-channel switch transistor 126. Non-volatile n-channel transistor 122 has its source coupled to ground through an n-channel isolation transistor 128 and its drain coupled to the gate of volatile n-channel switch transistor 126. Non-volatile p-channel transistor 124 has its source coupled to bit line 136 and its drain coupled to the drain of non-volatile n-channel transistor 122 and the gate of volatile n-channel switch transistor 126 through transistor 28.

The gate of non-volatile n-channel transistor 122 is coupled to a gate line 130. The gate of non-volatile p-channel transistor 124 is coupled to a gate line 132. The gate of n-channel isolation transistor 128 is coupled to a gate line 134. The gate of p-channel transistor 28 is coupled to a gate line 34.

In the memory cell 150, the source of non-volatile n-channel transistor 122 is coupled to ground 152 through n-channel isolation transistor 128 so that its bit line can be a line 136 at the source of non-volatile p-channel transistor 124. The addition of n-channel isolation transistor 128 allows making a trade off between metal complexity and the extra layout area required by the presence of a simple volatile n-channel transistor isolation transistor 128 added to the cell. As in the embodiment of FIG. 3A, p-channel transistor 28 reduces stress on the non-volatile p-channel transistor 104 as previously described.

Persons of ordinary skill in the art will readily recognize that an n-channel stress-reducing transistor like n-channel transistor 48 in FIG. 3B could be used in place of or in addition to p-channel transistor 28 in either of the circuits of FIGS. 6A and 6B. Such embodiments are intended to fall within the scope of the present invention.

Referring now to FIG. 7, a set of four tables that provides illustrative voltages for the various nodes of the circuits shown in FIGS. 3A, 3B, 3C, 5B, 5C, 6A, and 6B. The numbers appearing next to the transistor element names in the “Terminals” column of the tables correspond to the reference numerals in the figures to which the terminals pertain. Persons of ordinary skill in the art will appreciate that these voltage values are illustrative only, and that actual voltages that will be encountered in real implementations of these circuits will depend on various factors such as process and geometry.

While embodiments and applications of this invention have been shown and described, it would be apparent to those skilled in the art that many more modifications than mentioned above are possible without departing from the inventive concepts herein. The invention, therefore, is not to be restricted except in the spirit of the appended claims.

Claims

1. A memory cell including: a non-volatile p-channel transistor having a source coupled to a first potential, a drain, and a gate;a non-volatile n-channel transistor having a source coupled to a second potential, a drain, and a gate; anda stress transistor having a source and drain directly connected between the drain of the non-volatile p-channel transistor and the drain of the non-volatile n-channel transistor, the stress transistor having a gate coupled to a gate bias circuit.

2. The memory cell of claim 1, further including a switch transistor having a gate coupled to a switch node, a source, and a drain.

3. The memory cell of claim 1 wherein: the stress transistor is an n-channel transistor having a source directly connected to the drain of the non-volatile n-channel transistor and a drain directly connected to the drain of the non-volatile p-channel transistor; andthe memory cell further including an n-channel switch transistor having a gate coupled to the drain of the stress transistor and the drain of the non-volatile n-channel transistor, a source, and a drain; andthe switch node is coupled to the drain of the non-volatile p-channel transistor.

4. The memory cell of claim 1 wherein: the stress transistor is a p-channel transistor having a source directly connected to thedrain of the non-volatile p-channel transistor and a drain directly connected to the drain of the non-volatile n-channel; andthe memory cell further including an n-channel switch transistor having a gate directly connected to the drain of the stress transistor and the drain of the non-volatile n-channel transistor, a source, and a drain; andthe switch node is coupled to the drain of the non-volatile n-channel transistor.

5. The memory cell of claim 2 wherein the switch transistor is an n-channel transistor.

6. A memory cell including: a non-volatile p-channel transistor having a drain coupled to a switch node, a source, and a gate;a non-volatile n-channel transistor having a source coupled to a bit line, a drain coupled to the switch node, and a gate; andan isolation transistor having a source and drain coupled between a first potential and the drain of the non-volatile p-channel transistor, the isolation transistor having a gate.

7. The memory cell of claim 6, further including a switch transistor having a gate coupled to the switch node and to the drain of the non-volatile p-channel transistor, a source, and a drain.

8. The memory cell of claim 6 wherein the isolation transistor is a p-channel transistor having a source coupled to the first potential, a drain coupled to the source of the non-volatile p-channel transistor, and a gate.

9. The memory cell of claim 7 wherein the switch transistor is an n-channel transistor.

10. A memory cell including: a non-volatile p-channel transistor having a source coupled to a bit line, a drain coupled to a switch node, and a gate;a non-volatile n-channel transistor having a source, a drain coupled to the switch node, and a gate; andan isolation transistor having a source and drain coupled between a first potential and the source of the non-volatile n-channel transistor, the isolation transistor having a gate.

11. The memory cell of claim 10, further including a switch transistor having a source, a drain, and a gate coupled to the switch node and to the drain of the non-volatile p-channel transistor.

12. The memory cell of claim 10 wherein the isolation transistor is an n-channel transistor having a source coupled to the first potential, a drain coupled to the source of the non-volatile n-channel transistor, and a gate.

13. The memory cell of claim 11 wherein the switch transistor is an n-channel transistor.

14. A memory cell including: a non-volatile p-channel transistor having a source, a drain, and a gate;a non-volatile n-channel transistor having a source coupled to a bit line, a drain coupled to a switch node, and a gate;a p-channel isolation transistor having a source coupled to a first potential, a drain coupled to the source of the non-volatile p-channel transistor, and a gate; anda p-channel stress transistor having a source coupled to the drain of the non-volatile p-channel transistor, a drain coupled to the switch node, and a gate.

15. The memory cell of claim 14, further including a switch transistor having a source, a drain, and a gate coupled to the switch node.

16. A memory cell including: a non-volatile p-channel transistor having a source coupled to a bit line, a drain, and a gate;a non-volatile n-channel transistor having a source, a drain coupled to a switch node, and a gate;an n-channel isolation transistor having a source coupled to a first potential, a drain coupled to the source of the non-volatile n-channel transistor, and a gate; anda p-channel stress transistor having a source coupled to the drain of the non-volatile p-channel transistor, a drain coupled to the switch node, and a gate.

17. The memory cell of claim 16, further including a switch transistor having a source, a drain, and a gate coupled to the switch node.